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Searched defs:Reg0 (Results 1 – 25 of 39) sorted by relevance

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/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DLocked.cpp86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DLocked.cpp89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp129 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
138 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
148 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
180 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
186 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp146 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
155 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
165 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
170 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
185 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
197 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
203 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
209 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.cpp117 unsigned Reg0 = MI->getOperand(0).getReg(); in commuteInstruction() local
139 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstruction() local
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1861 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1991 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2156 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
2254 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
2356 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2403 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2424 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2444 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2776 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
2795 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
DThumb2SizeReduction.cpp706 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1796 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1930 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2099 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
2218 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
2316 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2364 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2386 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2407 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2690 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
2709 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
DThumb2SizeReduction.cpp736 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp241 unsigned Reg0 = Op0.getReg(); in runOnMachineFunction() local
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp243 unsigned Reg0 = Op0.getReg(); in runOnMachineFunction() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp225 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp225 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelDAGToDAG.cpp1603 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1721 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
1877 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
1973 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
2069 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectV6T2BitfieldExtractOp() local
2092 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectV6T2BitfieldExtractOp() local
2487 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
2503 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
DThumb2SizeReduction.cpp587 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp219 unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, in buildEXP()
263 unsigned Reg0 = I.getOperand(3).getReg(); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp464 unsigned Reg0 = in emitPrologue() local
482 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp438 unsigned Reg0 = in emitPrologue() local
456 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
/external/capstone/arch/ARM/
DARMInstPrinter.c2247 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwo() local
2270 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwoSpaced() local
2370 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwoAllLanes() local
2458 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwoSpacedAllLanes() local
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTargetInstrInfoImpl.cpp77 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstruction() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp1360 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1373 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1428 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1475 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp1476 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1489 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1544 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1591 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp348 unsigned Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
378 unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCRegisterInfo.h642 uint16_t Reg0 = 0; variable
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h613 uint16_t Reg0; variable

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