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Searched defs:Reg1 (Results 1 – 25 of 82) sorted by relevance

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/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DLocked.cpp86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DLocked.cpp89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrBuilder.h84 unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) { in addRegReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMicroMipsSizeReduction.cpp372 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters()
400 unsigned Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
472 unsigned Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
DMipsAsmPrinter.cpp824 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg()
844 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg()
855 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair()
DMipsSEFrameLowering.cpp466 unsigned Reg1 = in emitPrologue() local
483 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrBuilder.h116 unsigned Reg1, bool isKill1, in addRegReg()
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp769 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg()
789 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg()
800 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair()
DMipsSEFrameLowering.cpp440 unsigned Reg1 = in emitPrologue() local
457 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h144 unsigned Reg1, bool isKill1, in addRegReg()
/external/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp875 unsigned Reg1; member
974 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
1037 unsigned Reg1 = RPI.Reg1; in restoreCalleeSavedRegisters() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp596 unsigned Reg1 = Reg; in lowerCRSpilling() local
641 unsigned Reg1 = Reg; in lowerCRRestore() local
685 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp515 unsigned Reg1 = Reg; in lowerCRSpilling() local
560 unsigned Reg1 = Reg; in lowerCRRestore() local
604 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp170 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
185 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
197 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
203 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
210 unsigned Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrBuilder.h166 unsigned Reg1, bool isKill1, in addRegReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp226 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
180 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
186 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp1142 unsigned Reg1 = AArch64::NoRegister; member
1272 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
1335 unsigned Reg1 = RPI.Reg1; in restoreCalleeSavedRegisters() local
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp226 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCRegisterInfo.h79 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
643 uint16_t Reg1 = 0; variable
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
614 uint16_t Reg1; variable
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp219 unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, in buildEXP()
264 unsigned Reg1 = I.getOperand(4).getReg(); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1384 StringRef Reg1(R1); in processInstruction() local
1399 StringRef Reg1(R1); in processInstruction() local
1415 StringRef Reg1(R1); in processInstruction() local
1747 StringRef Reg1(R1); in processInstruction() local
1891 StringRef Reg1(R1); in processInstruction() local
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCRegisterInfo.h85 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
/external/capstone/arch/ARM/
DARMInstPrinter.c2248 unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); in printVectorListTwo() local
2271 unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); in printVectorListTwoSpaced() local
2371 unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); in printVectorListTwoAllLanes() local
2459 unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); in printVectorListTwoSpacedAllLanes() local

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