| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| D | RegisterAliasing.cpp | 34 const llvm::MCRegisterClass &RegClass) in RegisterAliasingTracker()
77 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 35 const TargetRegisterClass &RegClass) { in constrainRegToClass()
57 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterClassInfo.h | 41 OwningArrayPtr<RCInfo> RegClass; variable
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| D | MachineRegisterInfo.cpp | 97 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister()
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| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 51 #define DECODE_OPERAND2(RegClass, DecName) \ argument
60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 48 std::unique_ptr<RCInfo[]> RegClass; variable
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| D | RegisterScavenging.h | 163 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 120 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 45 std::unique_ptr<RCInfo[]> RegClass; variable
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| D | RegisterScavenging.h | 145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetInstrInfo.cpp | 36 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTypes.h | 36 enum RegClass : uint8_t { enum
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| /external/capstone/ |
| D | MCInstrDesc.h | 63 int16_t RegClass; member
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| /external/v8/src/wasm/baseline/ |
| D | liftoff-register.h | 21 enum RegClass : uint8_t { enum
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.h | 137 const TargetRegisterClass *RegClass = nullptr; member
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegStackify.cpp | 103 const auto *RegClass = in ConvertImplicitDefToConstZero() local
582 const auto *RegClass = MRI.getRegClass(Reg); in MoveAndTeeForMultiUse() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
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| D | MachineRegisterInfo.cpp | 166 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister()
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| /external/llvm/lib/CodeGen/ |
| D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
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| D | MachineRegisterInfo.cpp | 95 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1598 SDValue RegClass = in createGPRPairNode() local
1609 SDValue RegClass = in createSRegPairNode() local
1620 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1631 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1643 SDValue RegClass = in createQuadSRegsNode() local
1658 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1673 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1513 SDValue RegClass = in createGPRPairNode() local
1524 SDValue RegClass = in createSRegPairNode() local
1535 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1546 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1558 SDValue RegClass = in createQuadSRegsNode() local
1573 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1588 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1454 SDValue RegClass = in PairSRegs() local
1466 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); in PairDRegs() local
1477 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in PairQRegs() local
1489 SDValue RegClass = in QuadSRegs() local
1505 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in QuadDRegs() local
1520 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32); in QuadQRegs() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUMachineCFGStructurizer.cpp | 1932 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1999 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2059 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2174 const TargetRegisterClass *RegClass = in createEntryPHI() local
2312 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2449 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | RISCVCompressInstEmitter.cpp | 132 bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister()
|