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Searched defs:RegLo (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp1261 unsigned RegLo = VA.getLocReg(); in LowerCall() local
1507 unsigned RegLo = VA.getLocReg(); in LowerReturn() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp1031 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp873 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp856 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp912 unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringMIPS32.cpp3885 Variable *RegHi, *RegLo; in lowerCast() local
3894 auto *RegLo = legalizeToReg(loOperand(Var64On32)); in lowerCast() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp1273 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp1713 int64_t RegLo, RegHi; in ParseAMDGPURegister() local