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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2014 Google, Inc
4  *
5  * From Coreboot file of the same name
6  *
7  * Copyright (C) 2007-2008 coresystems GmbH
8  * Copyright (C) 2011 Google Inc.
9  */
10 
11 #ifndef _ACH_ASM_SANDYBRIDGE_H
12 #define _ACH_ASM_SANDYBRIDGE_H
13 
14 /* Chipset types */
15 #define SANDYBRIDGE_MOBILE	0
16 #define SANDYBRIDGE_DESKTOP	1
17 #define SANDYBRIDGE_SERVER	2
18 
19 /* Device ID for SandyBridge and IvyBridge */
20 #define BASE_REV_SNB	0x00
21 #define BASE_REV_IVB	0x50
22 #define BASE_REV_MASK	0x50
23 
24 /* SandyBridge CPU stepping */
25 #define SNB_STEP_D0	(BASE_REV_SNB + 5) /* Also J0 */
26 #define SNB_STEP_D1	(BASE_REV_SNB + 6)
27 #define SNB_STEP_D2	(BASE_REV_SNB + 7) /* Also J1/Q0 */
28 
29 /* IvyBridge CPU stepping */
30 #define IVB_STEP_A0	(BASE_REV_IVB + 0)
31 #define IVB_STEP_B0	(BASE_REV_IVB + 2)
32 #define IVB_STEP_C0	(BASE_REV_IVB + 4)
33 #define IVB_STEP_K0	(BASE_REV_IVB + 5)
34 #define IVB_STEP_D0	(BASE_REV_IVB + 6)
35 
36 /* Intel Enhanced Debug region must be 4MB */
37 #define IED_SIZE	0x400000
38 
39 /* Northbridge BARs */
40 #define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
41 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
42 #define DEFAULT_RCBABASE	0xfed1c000
43 /* 4 KB per PCIe device */
44 #define DEFAULT_PCIEXBAR	CONFIG_PCIE_ECAM_BASE
45 
46 /* Device 0:0.0 PCI configuration space (Host Bridge) */
47 #define EPBAR		0x40
48 #define MCHBAR		0x48
49 #define PCIEXBAR	0x60
50 #define DMIBAR		0x68
51 #define X60BAR		0x60
52 
53 #define GGC		0x50			/* GMCH Graphics Control */
54 
55 #define DEVEN		0x54			/* Device Enable */
56 #define  DEVEN_PEG60	(1 << 13)
57 #define  DEVEN_IGD	(1 << 4)
58 #define  DEVEN_PEG10	(1 << 3)
59 #define  DEVEN_PEG11	(1 << 2)
60 #define  DEVEN_PEG12	(1 << 1)
61 #define  DEVEN_HOST	(1 << 0)
62 
63 #define PAM0		0x80
64 #define PAM1		0x81
65 #define PAM2		0x82
66 #define PAM3		0x83
67 #define PAM4		0x84
68 #define PAM5		0x85
69 #define PAM6		0x86
70 
71 #define LAC		0x87	/* Legacy Access Control */
72 #define SMRAM		0x88	/* System Management RAM Control */
73 #define  D_OPEN		(1 << 6)
74 #define  D_CLS		(1 << 5)
75 #define  D_LCK		(1 << 4)
76 #define  G_SMRAME	(1 << 3)
77 #define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
78 
79 #define TOM		0xa0
80 #define TOUUD		0xa8	/* Top of Upper Usable DRAM */
81 #define TSEG		0xb8	/* TSEG base */
82 #define TOLUD		0xbc	/* Top of Low Used Memory */
83 
84 #define SKPAD		0xdc	/* Scratchpad Data */
85 
86 /* Device 0:1.0 PCI configuration space (PCI Express) */
87 #define BCTRL1		0x3e	/* 16bit */
88 
89 /* Device 0:2.0 PCI configuration space (Graphics Device) */
90 
91 #define MSAC		0x62	/* Multi Size Aperture Control */
92 #define SWSCI		0xe8	/* SWSCI  enable */
93 #define ASLS		0xfc	/* OpRegion Base */
94 
95 /*
96  * MCHBAR
97  */
98 #define SSKPD		0x5d14	/* 16bit (scratchpad) */
99 #define BIOS_RESET_CPL	0x5da8	/* 8bit */
100 
101 /*
102  * DMIBAR
103  */
104 
105 #define DMIBAR_REG(x)	(DEFAULT_DMIBAR + x)
106 
107 /**
108  * bridge_silicon_revision() - Get the Northbridge revision
109  *
110  * @dev:	Northbridge device
111  * @return revision ID (bits 3:0) and bridge ID (bits 7:4)
112  */
113 int bridge_silicon_revision(struct udevice *dev);
114 
115 #endif
116