| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 65 SHL, SRA, SRL enumerator
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 65 SHL, SRA, SRL enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 65 SHL, SRA, SRL enumerator
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 38 SRA = 0x37, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 38 SRA = 0x37, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 91 SRL, SRA, SHL, enumerator
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 106 SRL, SRA, SHL, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 150 SRL, SRA, SHL, enumerator
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 382 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 339 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_common.c | 169 #define SRA (OPC1(0x2) | OPC3(0x27)) macro
|
| D | sljitNativeMIPS_common.c | 181 #define SRA (HI(0) | LO(3)) macro
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 835 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; in LowerSRXParts() local
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1011 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; in LowerSRXParts() local
|
| /external/llvm/include/llvm/TableGen/ |
| D | Record.h | 801 enum BinaryOp : uint8_t { ADD, AND, SHL, SRA, SRL, LISTCONCAT, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/TableGen/ |
| D | Record.h | 801 enum BinaryOp : uint8_t { ADD, AND, OR, SHL, SRA, SRL, LISTCONCAT, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1798 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, in visitSDIV() local
3488 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, in visitSRA() local
|
| /external/swiftshader/third_party/LLVM/include/llvm/TableGen/ |
| D | Record.h | 954 enum BinaryOp { SHL, SRA, SRL, STRCONCAT, CONCAT, EQ }; enumerator
|
| /external/v8/src/mips/ |
| D | constants-mips.h | 502 SRA = ((0U << 3) + 3), enumerator
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 484 SRA = ((0U << 3) + 3), enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2283 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, ADD, in visitSDIV() local
4737 SDValue SRA = DAG.getNode(ISD::SRA, DL, LargeVT, in visitSRA() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2751 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt); in visitSUB() local
6667 SDValue SRA = DAG.getNode(ISD::SRA, DL, LargeVT, in visitSRA() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 7525 SDValue SRA = in BuildSDIVPow2() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 8643 SDValue SRA = in BuildSDIVPow2() local
|