1VIXL Supported Instruction List 2=============================== 3 4This is a list of the AArch64 instructions supported by the VIXL assembler, 5disassembler and simulator. The simulator may not support all floating point 6operations to the precision required by AArch64 - please check the simulator 7source code for details. 8 9AArch64 integer instructions 10---------------------------- 11 12### ADC ### 13 14Add with carry bit. 15 16 void adc(const Register& rd, const Register& rn, const Operand& operand) 17 18 19### ADCS ### 20 21Add with carry bit and update status flags. 22 23 void adcs(const Register& rd, const Register& rn, const Operand& operand) 24 25 26### ADD ### 27 28Add. 29 30 void add(const Register& rd, const Register& rn, const Operand& operand) 31 32 33### ADDS ### 34 35Add and update status flags. 36 37 void adds(const Register& rd, const Register& rn, const Operand& operand) 38 39 40### ADR ### 41 42Calculate the address of a PC offset. 43 44 void adr(const Register& xd, int64_t imm21) 45 46 47### ADR ### 48 49Calculate the address of a label. 50 51 void adr(const Register& xd, Label* label) 52 53 54### ADRP ### 55 56Calculate the page address of a PC offset. 57 58 void adrp(const Register& xd, int64_t imm21) 59 60 61### ADRP ### 62 63Calculate the page address of a label. 64 65 void adrp(const Register& xd, Label* label) 66 67 68### AND ### 69 70Bitwise and (A & B). 71 72 void and_(const Register& rd, const Register& rn, const Operand& operand) 73 74 75### ANDS ### 76 77Bitwise and (A & B) and update status flags. 78 79 void ands(const Register& rd, const Register& rn, const Operand& operand) 80 81 82### ASR ### 83 84Arithmetic shift right. 85 86 void asr(const Register& rd, const Register& rn, unsigned shift) 87 88 89### ASRV ### 90 91Arithmetic shift right by variable. 92 93 void asrv(const Register& rd, const Register& rn, const Register& rm) 94 95 96### B ### 97 98Conditional branch to PC offset. 99 100 void b(int64_t imm19, Condition cond) 101 102 103### B ### 104 105Conditional branch to label. 106 107 void b(Label* label, Condition cond) 108 109 110### B ### 111 112Unconditional branch to PC offset. 113 114 void b(int64_t imm26) 115 116 117### B ### 118 119Unconditional branch to label. 120 121 void b(Label* label) 122 123 124### BFI ### 125 126Bitfield insert. 127 128 void bfi(const Register& rd, 129 const Register& rn, 130 unsigned lsb, 131 unsigned width) 132 133 134### BFM ### 135 136Bitfield move. 137 138 void bfm(const Register& rd, 139 const Register& rn, 140 unsigned immr, 141 unsigned imms) 142 143 144### BFXIL ### 145 146Bitfield extract and insert low. 147 148 void bfxil(const Register& rd, 149 const Register& rn, 150 unsigned lsb, 151 unsigned width) 152 153 154### BIC ### 155 156Bit clear (A & ~B). 157 158 void bic(const Register& rd, const Register& rn, const Operand& operand) 159 160 161### BICS ### 162 163Bit clear (A & ~B) and update status flags. 164 165 void bics(const Register& rd, const Register& rn, const Operand& operand) 166 167 168### BL ### 169 170Branch with link to PC offset. 171 172 void bl(int64_t imm26) 173 174 175### BL ### 176 177Branch with link to label. 178 179 void bl(Label* label) 180 181 182### BLR ### 183 184Branch with link to register. 185 186 void blr(const Register& xn) 187 188 189### BR ### 190 191Branch to register. 192 193 void br(const Register& xn) 194 195 196### BRK ### 197 198Monitor debug-mode breakpoint. 199 200 void brk(int code) 201 202 203### CBNZ ### 204 205Compare and branch to PC offset if not zero. 206 207 void cbnz(const Register& rt, int64_t imm19) 208 209 210### CBNZ ### 211 212Compare and branch to label if not zero. 213 214 void cbnz(const Register& rt, Label* label) 215 216 217### CBZ ### 218 219Compare and branch to PC offset if zero. 220 221 void cbz(const Register& rt, int64_t imm19) 222 223 224### CBZ ### 225 226Compare and branch to label if zero. 227 228 void cbz(const Register& rt, Label* label) 229 230 231### CCMN ### 232 233Conditional compare negative. 234 235 void ccmn(const Register& rn, 236 const Operand& operand, 237 StatusFlags nzcv, 238 Condition cond) 239 240 241### CCMP ### 242 243Conditional compare. 244 245 void ccmp(const Register& rn, 246 const Operand& operand, 247 StatusFlags nzcv, 248 Condition cond) 249 250 251### CINC ### 252 253Conditional increment: rd = cond ? rn + 1 : rn. 254 255 void cinc(const Register& rd, const Register& rn, Condition cond) 256 257 258### CINV ### 259 260Conditional invert: rd = cond ? ~rn : rn. 261 262 void cinv(const Register& rd, const Register& rn, Condition cond) 263 264 265### CLREX ### 266 267Clear exclusive monitor. 268 269 void clrex(int imm4 = 0xf) 270 271 272### CLS ### 273 274Count leading sign bits. 275 276 void cls(const Register& rd, const Register& rn) 277 278 279### CLZ ### 280 281Count leading zeroes. 282 283 void clz(const Register& rd, const Register& rn) 284 285 286### CMN ### 287 288Compare negative. 289 290 void cmn(const Register& rn, const Operand& operand) 291 292 293### CMP ### 294 295Compare. 296 297 void cmp(const Register& rn, const Operand& operand) 298 299 300### CNEG ### 301 302Conditional negate: rd = cond ? -rn : rn. 303 304 void cneg(const Register& rd, const Register& rn, Condition cond) 305 306 307### CRC32B ### 308 309CRC-32 checksum from byte. 310 311 void crc32b(const Register& wd, const Register& wn, const Register& wm) 312 313 314### CRC32CB ### 315 316CRC-32 C checksum from byte. 317 318 void crc32cb(const Register& wd, const Register& wn, const Register& wm) 319 320 321### CRC32CH ### 322 323CRC-32 C checksum from half-word. 324 325 void crc32ch(const Register& wd, const Register& wn, const Register& wm) 326 327 328### CRC32CW ### 329 330CRC-32 C checksum from word. 331 332 void crc32cw(const Register& wd, const Register& wn, const Register& wm) 333 334 335### CRC32CX ### 336 337CRC-32C checksum from double word. 338 339 void crc32cx(const Register& wd, const Register& wn, const Register& xm) 340 341 342### CRC32H ### 343 344CRC-32 checksum from half-word. 345 346 void crc32h(const Register& wd, const Register& wn, const Register& wm) 347 348 349### CRC32W ### 350 351CRC-32 checksum from word. 352 353 void crc32w(const Register& wd, const Register& wn, const Register& wm) 354 355 356### CRC32X ### 357 358CRC-32 checksum from double word. 359 360 void crc32x(const Register& wd, const Register& wn, const Register& xm) 361 362 363### CSEL ### 364 365Conditional select: rd = cond ? rn : rm. 366 367 void csel(const Register& rd, 368 const Register& rn, 369 const Register& rm, 370 Condition cond) 371 372 373### CSET ### 374 375Conditional set: rd = cond ? 1 : 0. 376 377 void cset(const Register& rd, Condition cond) 378 379 380### CSETM ### 381 382Conditional set mask: rd = cond ? -1 : 0. 383 384 void csetm(const Register& rd, Condition cond) 385 386 387### CSINC ### 388 389Conditional select increment: rd = cond ? rn : rm + 1. 390 391 void csinc(const Register& rd, 392 const Register& rn, 393 const Register& rm, 394 Condition cond) 395 396 397### CSINV ### 398 399Conditional select inversion: rd = cond ? rn : ~rm. 400 401 void csinv(const Register& rd, 402 const Register& rn, 403 const Register& rm, 404 Condition cond) 405 406 407### CSNEG ### 408 409Conditional select negation: rd = cond ? rn : -rm. 410 411 void csneg(const Register& rd, 412 const Register& rn, 413 const Register& rm, 414 Condition cond) 415 416 417### DC ### 418 419 420 421 void dc(T data) 422 423 424### DC ### 425 426System data cache operation. 427 428 void dc(DataCacheOp op, const Register& rt) 429 430 431### DMB ### 432 433Data memory barrier. 434 435 void dmb(BarrierDomain domain, BarrierType type) 436 437 438### DSB ### 439 440Data synchronization barrier. 441 442 void dsb(BarrierDomain domain, BarrierType type) 443 444 445### EON ### 446 447Bitwise enor/xnor (A ^ ~B). 448 449 void eon(const Register& rd, const Register& rn, const Operand& operand) 450 451 452### EOR ### 453 454Bitwise eor/xor (A ^ B). 455 456 void eor(const Register& rd, const Register& rn, const Operand& operand) 457 458 459### EXTR ### 460 461Extract. 462 463 void extr(const Register& rd, 464 const Register& rn, 465 const Register& rm, 466 unsigned lsb) 467 468 469### HINT ### 470 471System hint. 472 473 void hint(SystemHint code) 474 475 476### HLT ### 477 478Halting debug-mode breakpoint. 479 480 void hlt(int code) 481 482 483### IC ### 484 485System instruction cache operation. 486 487 void ic(InstructionCacheOp op, const Register& rt) 488 489 490### ISB ### 491 492Instruction synchronization barrier. 493 494 void isb() 495 496 497### LDAR ### 498 499Load-acquire register. 500 501 void ldar(const Register& rt, const MemOperand& src) 502 503 504### LDARB ### 505 506Load-acquire byte. 507 508 void ldarb(const Register& rt, const MemOperand& src) 509 510 511### LDARH ### 512 513Load-acquire half-word. 514 515 void ldarh(const Register& rt, const MemOperand& src) 516 517 518### LDAXP ### 519 520Load-acquire exclusive register pair. 521 522 void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) 523 524 525### LDAXR ### 526 527Load-acquire exclusive register. 528 529 void ldaxr(const Register& rt, const MemOperand& src) 530 531 532### LDAXRB ### 533 534Load-acquire exclusive byte. 535 536 void ldaxrb(const Register& rt, const MemOperand& src) 537 538 539### LDAXRH ### 540 541Load-acquire exclusive half-word. 542 543 void ldaxrh(const Register& rt, const MemOperand& src) 544 545 546### LDNP ### 547 548Load integer or FP register pair, non-temporal. 549 550 void ldnp(const CPURegister& rt, 551 const CPURegister& rt2, 552 const MemOperand& src) 553 554 555### LDP ### 556 557Load integer or FP register pair. 558 559 void ldp(const CPURegister& rt, 560 const CPURegister& rt2, 561 const MemOperand& src) 562 563 564### LDPSW ### 565 566Load word pair with sign extension. 567 568 void ldpsw(const Register& xt, const Register& xt2, const MemOperand& src) 569 570 571### LDR ### 572 573Load integer or FP register from literal pool. 574 575 void ldr(const CPURegister& rt, RawLiteral* literal) 576 577 578### LDR ### 579 580Load integer or FP register from pc + imm19 << 2. 581 582 void ldr(const CPURegister& rt, int64_t imm19) 583 584 585### LDR ### 586 587Load integer or FP register. 588 589 void ldr(const CPURegister& rt, 590 const MemOperand& src, 591 LoadStoreScalingOption option = PreferScaledOffset) 592 593 594### LDRB ### 595 596Load byte. 597 598 void ldrb(const Register& rt, 599 const MemOperand& src, 600 LoadStoreScalingOption option = PreferScaledOffset) 601 602 603### LDRH ### 604 605Load half-word. 606 607 void ldrh(const Register& rt, 608 const MemOperand& src, 609 LoadStoreScalingOption option = PreferScaledOffset) 610 611 612### LDRSB ### 613 614Load byte with sign extension. 615 616 void ldrsb(const Register& rt, 617 const MemOperand& src, 618 LoadStoreScalingOption option = PreferScaledOffset) 619 620 621### LDRSH ### 622 623Load half-word with sign extension. 624 625 void ldrsh(const Register& rt, 626 const MemOperand& src, 627 LoadStoreScalingOption option = PreferScaledOffset) 628 629 630### LDRSW ### 631 632Load word with sign extension from literal pool. 633 634 void ldrsw(const Register& xt, RawLiteral* literal) 635 636 637### LDRSW ### 638 639Load word with sign extension from pc + imm19 << 2. 640 641 void ldrsw(const Register& xt, int64_t imm19) 642 643 644### LDRSW ### 645 646Load word with sign extension. 647 648 void ldrsw(const Register& xt, 649 const MemOperand& src, 650 LoadStoreScalingOption option = PreferScaledOffset) 651 652 653### LDUR ### 654 655Load integer or FP register (with unscaled offset). 656 657 void ldur(const CPURegister& rt, 658 const MemOperand& src, 659 LoadStoreScalingOption option = PreferUnscaledOffset) 660 661 662### LDURB ### 663 664Load byte (with unscaled offset). 665 666 void ldurb(const Register& rt, 667 const MemOperand& src, 668 LoadStoreScalingOption option = PreferUnscaledOffset) 669 670 671### LDURH ### 672 673Load half-word (with unscaled offset). 674 675 void ldurh(const Register& rt, 676 const MemOperand& src, 677 LoadStoreScalingOption option = PreferUnscaledOffset) 678 679 680### LDURSB ### 681 682Load byte with sign extension (and unscaled offset). 683 684 void ldursb(const Register& rt, 685 const MemOperand& src, 686 LoadStoreScalingOption option = PreferUnscaledOffset) 687 688 689### LDURSH ### 690 691Load half-word with sign extension (and unscaled offset). 692 693 void ldursh(const Register& rt, 694 const MemOperand& src, 695 LoadStoreScalingOption option = PreferUnscaledOffset) 696 697 698### LDURSW ### 699 700Load word with sign extension. 701 702 void ldursw(const Register& xt, 703 const MemOperand& src, 704 LoadStoreScalingOption option = PreferUnscaledOffset) 705 706 707### LDXP ### 708 709Load exclusive register pair. 710 711 void ldxp(const Register& rt, const Register& rt2, const MemOperand& src) 712 713 714### LDXR ### 715 716Load exclusive register. 717 718 void ldxr(const Register& rt, const MemOperand& src) 719 720 721### LDXRB ### 722 723Load exclusive byte. 724 725 void ldxrb(const Register& rt, const MemOperand& src) 726 727 728### LDXRH ### 729 730Load exclusive half-word. 731 732 void ldxrh(const Register& rt, const MemOperand& src) 733 734 735### LSL ### 736 737Logical shift left. 738 739 void lsl(const Register& rd, const Register& rn, unsigned shift) 740 741 742### LSLV ### 743 744Logical shift left by variable. 745 746 void lslv(const Register& rd, const Register& rn, const Register& rm) 747 748 749### LSR ### 750 751Logical shift right. 752 753 void lsr(const Register& rd, const Register& rn, unsigned shift) 754 755 756### LSRV ### 757 758Logical shift right by variable. 759 760 void lsrv(const Register& rd, const Register& rn, const Register& rm) 761 762 763### MADD ### 764 765Multiply and accumulate. 766 767 void madd(const Register& rd, 768 const Register& rn, 769 const Register& rm, 770 const Register& ra) 771 772 773### MNEG ### 774 775Negated multiply. 776 777 void mneg(const Register& rd, const Register& rn, const Register& rm) 778 779 780### MOV ### 781 782Move register to register. 783 784 void mov(const Register& rd, const Register& rn) 785 786 787### MOVK ### 788 789Move immediate and keep. 790 791 void movk(const Register& rd, uint64_t imm, int shift = -1) 792 793 794### MOVN ### 795 796Move inverted immediate. 797 798 void movn(const Register& rd, uint64_t imm, int shift = -1) 799 800 801### MOVZ ### 802 803Move immediate. 804 805 void movz(const Register& rd, uint64_t imm, int shift = -1) 806 807 808### MRS ### 809 810Move to register from system register. 811 812 void mrs(const Register& xt, SystemRegister sysreg) 813 814 815### MSR ### 816 817Move from register to system register. 818 819 void msr(SystemRegister sysreg, const Register& xt) 820 821 822### MSUB ### 823 824Multiply and subtract. 825 826 void msub(const Register& rd, 827 const Register& rn, 828 const Register& rm, 829 const Register& ra) 830 831 832### MUL ### 833 834Multiply. 835 836 void mul(const Register& rd, const Register& rn, const Register& rm) 837 838 839### MVN ### 840 841Move inverted operand to register. 842 843 void mvn(const Register& rd, const Operand& operand) 844 845 846### NEG ### 847 848Negate. 849 850 void neg(const Register& rd, const Operand& operand) 851 852 853### NEGS ### 854 855Negate and update status flags. 856 857 void negs(const Register& rd, const Operand& operand) 858 859 860### NGC ### 861 862Negate with carry bit. 863 864 void ngc(const Register& rd, const Operand& operand) 865 866 867### NGCS ### 868 869Negate with carry bit and update status flags. 870 871 void ngcs(const Register& rd, const Operand& operand) 872 873 874### NOP ### 875 876No-op. 877 878 void nop() 879 880 881### ORN ### 882 883Bitwise nor (A | ~B). 884 885 void orn(const Register& rd, const Register& rn, const Operand& operand) 886 887 888### ORR ### 889 890Bitwise or (A | B). 891 892 void orr(const Register& rd, const Register& rn, const Operand& operand) 893 894 895### PRFM ### 896 897Prefetch from pc + imm19 << 2. 898 899 void prfm(PrefetchOperation op, int64_t imm19) 900 901 902### PRFM ### 903 904Prefetch memory in the literal pool. 905 906 void prfm(PrefetchOperation op, RawLiteral* literal) 907 908 909### PRFM ### 910 911Prefetch memory. 912 913 void prfm(PrefetchOperation op, 914 const MemOperand& addr, 915 LoadStoreScalingOption option = PreferScaledOffset) 916 917 918### PRFUM ### 919 920Prefetch memory (with unscaled offset). 921 922 void prfum(PrefetchOperation op, 923 const MemOperand& addr, 924 LoadStoreScalingOption option = PreferUnscaledOffset) 925 926 927### RBIT ### 928 929Bit reverse. 930 931 void rbit(const Register& rd, const Register& rn) 932 933 934### RET ### 935 936Branch to register with return hint. 937 938 void ret(const Register& xn = lr) 939 940 941### REV ### 942 943Reverse bytes. 944 945 void rev(const Register& rd, const Register& rn) 946 947 948### REV16 ### 949 950Reverse bytes in 16-bit half words. 951 952 void rev16(const Register& rd, const Register& rn) 953 954 955### REV32 ### 956 957Reverse bytes in 32-bit words. 958 959 void rev32(const Register& xd, const Register& xn) 960 961 962### ROR ### 963 964Rotate right. 965 966 void ror(const Register& rd, const Register& rs, unsigned shift) 967 968 969### RORV ### 970 971Rotate right by variable. 972 973 void rorv(const Register& rd, const Register& rn, const Register& rm) 974 975 976### SBC ### 977 978Subtract with carry bit. 979 980 void sbc(const Register& rd, const Register& rn, const Operand& operand) 981 982 983### SBCS ### 984 985Subtract with carry bit and update status flags. 986 987 void sbcs(const Register& rd, const Register& rn, const Operand& operand) 988 989 990### SBFIZ ### 991 992Signed bitfield insert with zero at right. 993 994 void sbfiz(const Register& rd, 995 const Register& rn, 996 unsigned lsb, 997 unsigned width) 998 999 1000### SBFM ### 1001 1002Signed bitfield move. 1003 1004 void sbfm(const Register& rd, 1005 const Register& rn, 1006 unsigned immr, 1007 unsigned imms) 1008 1009 1010### SBFX ### 1011 1012Signed bitfield extract. 1013 1014 void sbfx(const Register& rd, 1015 const Register& rn, 1016 unsigned lsb, 1017 unsigned width) 1018 1019 1020### SDIV ### 1021 1022Signed integer divide. 1023 1024 void sdiv(const Register& rd, const Register& rn, const Register& rm) 1025 1026 1027### SMADDL ### 1028 1029Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 1030 1031 void smaddl(const Register& xd, 1032 const Register& wn, 1033 const Register& wm, 1034 const Register& xa) 1035 1036 1037### SMSUBL ### 1038 1039Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit. 1040 1041 void smsubl(const Register& xd, 1042 const Register& wn, 1043 const Register& wm, 1044 const Register& xa) 1045 1046 1047### SMULH ### 1048 1049Signed multiply high: 64 x 64 -> 64-bit <127:64>. 1050 1051 void smulh(const Register& xd, const Register& xn, const Register& xm) 1052 1053 1054### SMULL ### 1055 1056Signed long multiply: 32 x 32 -> 64-bit. 1057 1058 void smull(const Register& xd, const Register& wn, const Register& wm) 1059 1060 1061### STLR ### 1062 1063Store-release register. 1064 1065 void stlr(const Register& rt, const MemOperand& dst) 1066 1067 1068### STLRB ### 1069 1070Store-release byte. 1071 1072 void stlrb(const Register& rt, const MemOperand& dst) 1073 1074 1075### STLRH ### 1076 1077Store-release half-word. 1078 1079 void stlrh(const Register& rt, const MemOperand& dst) 1080 1081 1082### STLXP ### 1083 1084Store-release exclusive register pair. 1085 1086 void stlxp(const Register& rs, 1087 const Register& rt, 1088 const Register& rt2, 1089 const MemOperand& dst) 1090 1091 1092### STLXR ### 1093 1094Store-release exclusive register. 1095 1096 void stlxr(const Register& rs, const Register& rt, const MemOperand& dst) 1097 1098 1099### STLXRB ### 1100 1101Store-release exclusive byte. 1102 1103 void stlxrb(const Register& rs, const Register& rt, const MemOperand& dst) 1104 1105 1106### STLXRH ### 1107 1108Store-release exclusive half-word. 1109 1110 void stlxrh(const Register& rs, const Register& rt, const MemOperand& dst) 1111 1112 1113### STNP ### 1114 1115Store integer or FP register pair, non-temporal. 1116 1117 void stnp(const CPURegister& rt, 1118 const CPURegister& rt2, 1119 const MemOperand& dst) 1120 1121 1122### STP ### 1123 1124Store integer or FP register pair. 1125 1126 void stp(const CPURegister& rt, 1127 const CPURegister& rt2, 1128 const MemOperand& dst) 1129 1130 1131### STR ### 1132 1133Store integer or FP register. 1134 1135 void str(const CPURegister& rt, 1136 const MemOperand& dst, 1137 LoadStoreScalingOption option = PreferScaledOffset) 1138 1139 1140### STRB ### 1141 1142Store byte. 1143 1144 void strb(const Register& rt, 1145 const MemOperand& dst, 1146 LoadStoreScalingOption option = PreferScaledOffset) 1147 1148 1149### STRH ### 1150 1151Store half-word. 1152 1153 void strh(const Register& rt, 1154 const MemOperand& dst, 1155 LoadStoreScalingOption option = PreferScaledOffset) 1156 1157 1158### STUR ### 1159 1160Store integer or FP register (with unscaled offset). 1161 1162 void stur(const CPURegister& rt, 1163 const MemOperand& src, 1164 LoadStoreScalingOption option = PreferUnscaledOffset) 1165 1166 1167### STURB ### 1168 1169Store byte (with unscaled offset). 1170 1171 void sturb(const Register& rt, 1172 const MemOperand& dst, 1173 LoadStoreScalingOption option = PreferUnscaledOffset) 1174 1175 1176### STURH ### 1177 1178Store half-word (with unscaled offset). 1179 1180 void sturh(const Register& rt, 1181 const MemOperand& dst, 1182 LoadStoreScalingOption option = PreferUnscaledOffset) 1183 1184 1185### STXP ### 1186 1187Store exclusive register pair. 1188 1189 void stxp(const Register& rs, 1190 const Register& rt, 1191 const Register& rt2, 1192 const MemOperand& dst) 1193 1194 1195### STXR ### 1196 1197Store exclusive register. 1198 1199 void stxr(const Register& rs, const Register& rt, const MemOperand& dst) 1200 1201 1202### STXRB ### 1203 1204Store exclusive byte. 1205 1206 void stxrb(const Register& rs, const Register& rt, const MemOperand& dst) 1207 1208 1209### STXRH ### 1210 1211Store exclusive half-word. 1212 1213 void stxrh(const Register& rs, const Register& rt, const MemOperand& dst) 1214 1215 1216### SUB ### 1217 1218Subtract. 1219 1220 void sub(const Register& rd, const Register& rn, const Operand& operand) 1221 1222 1223### SUBS ### 1224 1225Subtract and update status flags. 1226 1227 void subs(const Register& rd, const Register& rn, const Operand& operand) 1228 1229 1230### SVC ### 1231 1232Generate exception targeting EL1. 1233 1234 void svc(int code) 1235 1236 1237### SXTB ### 1238 1239Signed extend byte. 1240 1241 void sxtb(const Register& rd, const Register& rn) 1242 1243 1244### SXTH ### 1245 1246Signed extend halfword. 1247 1248 void sxth(const Register& rd, const Register& rn) 1249 1250 1251### SXTW ### 1252 1253Signed extend word. 1254 1255 void sxtw(const Register& rd, const Register& rn) 1256 1257 1258### SYS ### 1259 1260System instruction with pre-encoded op (op1:crn:crm:op2). 1261 1262 void sys(int op, const Register& xt = xzr) 1263 1264 1265### SYS ### 1266 1267System instruction. 1268 1269 void sys(int op1, int crn, int crm, int op2, const Register& xt = xzr) 1270 1271 1272### TBNZ ### 1273 1274Test bit and branch to PC offset if not zero. 1275 1276 void tbnz(const Register& rt, unsigned bit_pos, int64_t imm14) 1277 1278 1279### TBNZ ### 1280 1281Test bit and branch to label if not zero. 1282 1283 void tbnz(const Register& rt, unsigned bit_pos, Label* label) 1284 1285 1286### TBZ ### 1287 1288Test bit and branch to PC offset if zero. 1289 1290 void tbz(const Register& rt, unsigned bit_pos, int64_t imm14) 1291 1292 1293### TBZ ### 1294 1295Test bit and branch to label if zero. 1296 1297 void tbz(const Register& rt, unsigned bit_pos, Label* label) 1298 1299 1300### TST ### 1301 1302Bit test and set flags. 1303 1304 void tst(const Register& rn, const Operand& operand) 1305 1306 1307### UBFIZ ### 1308 1309Unsigned bitfield insert with zero at right. 1310 1311 void ubfiz(const Register& rd, 1312 const Register& rn, 1313 unsigned lsb, 1314 unsigned width) 1315 1316 1317### UBFM ### 1318 1319Unsigned bitfield move. 1320 1321 void ubfm(const Register& rd, 1322 const Register& rn, 1323 unsigned immr, 1324 unsigned imms) 1325 1326 1327### UBFX ### 1328 1329Unsigned bitfield extract. 1330 1331 void ubfx(const Register& rd, 1332 const Register& rn, 1333 unsigned lsb, 1334 unsigned width) 1335 1336 1337### UDIV ### 1338 1339Unsigned integer divide. 1340 1341 void udiv(const Register& rd, const Register& rn, const Register& rm) 1342 1343 1344### UMADDL ### 1345 1346Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 1347 1348 void umaddl(const Register& xd, 1349 const Register& wn, 1350 const Register& wm, 1351 const Register& xa) 1352 1353 1354### UMSUBL ### 1355 1356Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit. 1357 1358 void umsubl(const Register& xd, 1359 const Register& wn, 1360 const Register& wm, 1361 const Register& xa) 1362 1363 1364### UMULH ### 1365 1366Unsigned multiply high: 64 x 64 -> 64-bit <127:64>. 1367 1368 void umulh(const Register& xd, const Register& xn, const Register& xm) 1369 1370 1371### UMULL ### 1372 1373Unsigned long multiply: 32 x 32 -> 64-bit. 1374 1375 void umull(const Register& xd, const Register& wn, const Register& wm) 1376 1377 1378### UXTB ### 1379 1380Unsigned extend byte. 1381 1382 void uxtb(const Register& rd, const Register& rn) 1383 1384 1385### UXTH ### 1386 1387Unsigned extend halfword. 1388 1389 void uxth(const Register& rd, const Register& rn) 1390 1391 1392### UXTW ### 1393 1394Unsigned extend word. 1395 1396 void uxtw(const Register& rd, const Register& rn) 1397 1398 1399 1400AArch64 floating point and NEON instructions 1401-------------------------------------------- 1402 1403### ABS ### 1404 1405Absolute value. 1406 1407 void abs(const VRegister& vd, const VRegister& vn) 1408 1409 1410### ADD ### 1411 1412Add. 1413 1414 void add(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1415 1416 1417### ADDHN ### 1418 1419Add narrow returning high half. 1420 1421 void addhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1422 1423 1424### ADDHN2 ### 1425 1426Add narrow returning high half (second part). 1427 1428 void addhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1429 1430 1431### ADDP ### 1432 1433Add pair of elements scalar. 1434 1435 void addp(const VRegister& vd, const VRegister& vn) 1436 1437 1438### ADDP ### 1439 1440Add pairwise. 1441 1442 void addp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1443 1444 1445### ADDV ### 1446 1447Add across vector. 1448 1449 void addv(const VRegister& vd, const VRegister& vn) 1450 1451 1452### AND ### 1453 1454Bitwise and. 1455 1456 void and_(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1457 1458 1459### BIC ### 1460 1461Bit clear immediate. 1462 1463 void bic(const VRegister& vd, const int imm8, const int left_shift = 0) 1464 1465 1466### BIC ### 1467 1468Bit clear. 1469 1470 void bic(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1471 1472 1473### BIF ### 1474 1475Bitwise insert if false. 1476 1477 void bif(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1478 1479 1480### BIT ### 1481 1482Bitwise insert if true. 1483 1484 void bit(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1485 1486 1487### BSL ### 1488 1489Bitwise select. 1490 1491 void bsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1492 1493 1494### CLS ### 1495 1496Count leading sign bits. 1497 1498 void cls(const VRegister& vd, const VRegister& vn) 1499 1500 1501### CLZ ### 1502 1503Count leading zero bits (vector). 1504 1505 void clz(const VRegister& vd, const VRegister& vn) 1506 1507 1508### CMEQ ### 1509 1510Compare bitwise to zero. 1511 1512 void cmeq(const VRegister& vd, const VRegister& vn, int value) 1513 1514 1515### CMEQ ### 1516 1517Compare equal. 1518 1519 void cmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1520 1521 1522### CMGE ### 1523 1524Compare signed greater than or equal to zero. 1525 1526 void cmge(const VRegister& vd, const VRegister& vn, int value) 1527 1528 1529### CMGE ### 1530 1531Compare signed greater than or equal. 1532 1533 void cmge(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1534 1535 1536### CMGT ### 1537 1538Compare signed greater than zero. 1539 1540 void cmgt(const VRegister& vd, const VRegister& vn, int value) 1541 1542 1543### CMGT ### 1544 1545Compare signed greater than. 1546 1547 void cmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1548 1549 1550### CMHI ### 1551 1552Compare unsigned higher. 1553 1554 void cmhi(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1555 1556 1557### CMHS ### 1558 1559Compare unsigned higher or same. 1560 1561 void cmhs(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1562 1563 1564### CMLE ### 1565 1566Compare signed less than or equal to zero. 1567 1568 void cmle(const VRegister& vd, const VRegister& vn, int value) 1569 1570 1571### CMLT ### 1572 1573Compare signed less than zero. 1574 1575 void cmlt(const VRegister& vd, const VRegister& vn, int value) 1576 1577 1578### CMTST ### 1579 1580Compare bitwise test bits nonzero. 1581 1582 void cmtst(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1583 1584 1585### CNT ### 1586 1587Population count per byte. 1588 1589 void cnt(const VRegister& vd, const VRegister& vn) 1590 1591 1592### DUP ### 1593 1594Duplicate general-purpose register to vector. 1595 1596 void dup(const VRegister& vd, const Register& rn) 1597 1598 1599### DUP ### 1600 1601Duplicate vector element to vector or scalar. 1602 1603 void dup(const VRegister& vd, const VRegister& vn, int vn_index) 1604 1605 1606### EOR ### 1607 1608Bitwise eor. 1609 1610 void eor(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1611 1612 1613### EXT ### 1614 1615Extract vector from pair of vectors. 1616 1617 void ext(const VRegister& vd, 1618 const VRegister& vn, 1619 const VRegister& vm, 1620 int index) 1621 1622 1623### FABD ### 1624 1625FP absolute difference. 1626 1627 void fabd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1628 1629 1630### FABS ### 1631 1632FP absolute. 1633 1634 void fabs(const VRegister& vd, const VRegister& vn) 1635 1636 1637### FACGE ### 1638 1639FP absolute greater than or equal. 1640 1641 void facge(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1642 1643 1644### FACGT ### 1645 1646FP absolute greater than. 1647 1648 void facgt(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1649 1650 1651### FADD ### 1652 1653FP add. 1654 1655 void fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1656 1657 1658### FADDP ### 1659 1660FP pairwise add scalar. 1661 1662 void faddp(const VRegister& vd, const VRegister& vn) 1663 1664 1665### FADDP ### 1666 1667FP pairwise add vector. 1668 1669 void faddp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1670 1671 1672### FCADD ### 1673 1674FP complex add [Armv8.3]. 1675 1676 void fcadd(const VRegister& vd, 1677 const VRegister& vn, 1678 const VRegister& vm, 1679 int rot) 1680 1681 1682### FCCMP ### 1683 1684FP conditional compare. 1685 1686 void fccmp(const VRegister& vn, 1687 const VRegister& vm, 1688 StatusFlags nzcv, 1689 Condition cond) 1690 1691 1692### FCCMPE ### 1693 1694FP conditional signaling compare. 1695 1696 void fccmpe(const VRegister& vn, 1697 const VRegister& vm, 1698 StatusFlags nzcv, 1699 Condition cond) 1700 1701 1702### FCMEQ ### 1703 1704FP compare equal to zero. 1705 1706 void fcmeq(const VRegister& vd, const VRegister& vn, double imm) 1707 1708 1709### FCMEQ ### 1710 1711FP compare equal. 1712 1713 void fcmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1714 1715 1716### FCMGE ### 1717 1718FP greater than or equal to zero. 1719 1720 void fcmge(const VRegister& vd, const VRegister& vn, double imm) 1721 1722 1723### FCMGE ### 1724 1725FP greater than or equal. 1726 1727 void fcmge(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1728 1729 1730### FCMGT ### 1731 1732FP greater than zero. 1733 1734 void fcmgt(const VRegister& vd, const VRegister& vn, double imm) 1735 1736 1737### FCMGT ### 1738 1739FP greater than. 1740 1741 void fcmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1742 1743 1744### FCMLA ### 1745 1746FP complex multiply accumulate (by element) [Armv8.3]. 1747 1748 void fcmla(const VRegister& vd, 1749 const VRegister& vn, 1750 const VRegister& vm, 1751 int vm_index, 1752 int rot) 1753 1754 1755### FCMLA ### 1756 1757FP complex multiply accumulate [Armv8.3]. 1758 1759 void fcmla(const VRegister& vd, 1760 const VRegister& vn, 1761 const VRegister& vm, 1762 int rot) 1763 1764 1765### FCMLE ### 1766 1767FP less than or equal to zero. 1768 1769 void fcmle(const VRegister& vd, const VRegister& vn, double imm) 1770 1771 1772### FCMLT ### 1773 1774FP less than to zero. 1775 1776 void fcmlt(const VRegister& vd, const VRegister& vn, double imm) 1777 1778 1779### FCMP ### 1780 1781FP compare immediate. 1782 1783 void fcmp(const VRegister& vn, double value) 1784 1785 1786### FCMP ### 1787 1788FP compare registers. 1789 1790 void fcmp(const VRegister& vn, const VRegister& vm) 1791 1792 1793### FCMPE ### 1794 1795FP signaling compare immediate. 1796 1797 void fcmpe(const VRegister& vn, double value) 1798 1799 1800### FCMPE ### 1801 1802FP signaling compare registers. 1803 1804 void fcmpe(const VRegister& vn, const VRegister& vm) 1805 1806 1807### FCSEL ### 1808 1809FP conditional select. 1810 1811 void fcsel(const VRegister& vd, 1812 const VRegister& vn, 1813 const VRegister& vm, 1814 Condition cond) 1815 1816 1817### FCVT ### 1818 1819FP convert between precisions. 1820 1821 void fcvt(const VRegister& vd, const VRegister& vn) 1822 1823 1824### FCVTAS ### 1825 1826FP convert to signed integer, nearest with ties to away. 1827 1828 void fcvtas(const Register& rd, const VRegister& vn) 1829 1830 1831### FCVTAS ### 1832 1833FP convert to signed integer, nearest with ties to away. 1834 1835 void fcvtas(const VRegister& vd, const VRegister& vn) 1836 1837 1838### FCVTAU ### 1839 1840FP convert to unsigned integer, nearest with ties to away. 1841 1842 void fcvtau(const Register& rd, const VRegister& vn) 1843 1844 1845### FCVTAU ### 1846 1847FP convert to unsigned integer, nearest with ties to away. 1848 1849 void fcvtau(const VRegister& vd, const VRegister& vn) 1850 1851 1852### FCVTL ### 1853 1854FP convert to higher precision. 1855 1856 void fcvtl(const VRegister& vd, const VRegister& vn) 1857 1858 1859### FCVTL2 ### 1860 1861FP convert to higher precision (second part). 1862 1863 void fcvtl2(const VRegister& vd, const VRegister& vn) 1864 1865 1866### FCVTMS ### 1867 1868FP convert to signed integer, round towards -infinity. 1869 1870 void fcvtms(const Register& rd, const VRegister& vn) 1871 1872 1873### FCVTMS ### 1874 1875FP convert to signed integer, round towards -infinity. 1876 1877 void fcvtms(const VRegister& vd, const VRegister& vn) 1878 1879 1880### FCVTMU ### 1881 1882FP convert to unsigned integer, round towards -infinity. 1883 1884 void fcvtmu(const Register& rd, const VRegister& vn) 1885 1886 1887### FCVTMU ### 1888 1889FP convert to unsigned integer, round towards -infinity. 1890 1891 void fcvtmu(const VRegister& vd, const VRegister& vn) 1892 1893 1894### FCVTN ### 1895 1896FP convert to lower precision. 1897 1898 void fcvtn(const VRegister& vd, const VRegister& vn) 1899 1900 1901### FCVTN2 ### 1902 1903FP convert to lower prevision (second part). 1904 1905 void fcvtn2(const VRegister& vd, const VRegister& vn) 1906 1907 1908### FCVTNS ### 1909 1910FP convert to signed integer, nearest with ties to even. 1911 1912 void fcvtns(const Register& rd, const VRegister& vn) 1913 1914 1915### FCVTNS ### 1916 1917FP convert to signed integer, nearest with ties to even. 1918 1919 void fcvtns(const VRegister& rd, const VRegister& vn) 1920 1921 1922### FCVTNU ### 1923 1924FP convert to unsigned integer, nearest with ties to even. 1925 1926 void fcvtnu(const Register& rd, const VRegister& vn) 1927 1928 1929### FCVTNU ### 1930 1931FP convert to unsigned integer, nearest with ties to even. 1932 1933 void fcvtnu(const VRegister& rd, const VRegister& vn) 1934 1935 1936### FCVTPS ### 1937 1938FP convert to signed integer, round towards +infinity. 1939 1940 void fcvtps(const Register& rd, const VRegister& vn) 1941 1942 1943### FCVTPS ### 1944 1945FP convert to signed integer, round towards +infinity. 1946 1947 void fcvtps(const VRegister& vd, const VRegister& vn) 1948 1949 1950### FCVTPU ### 1951 1952FP convert to unsigned integer, round towards +infinity. 1953 1954 void fcvtpu(const Register& rd, const VRegister& vn) 1955 1956 1957### FCVTPU ### 1958 1959FP convert to unsigned integer, round towards +infinity. 1960 1961 void fcvtpu(const VRegister& vd, const VRegister& vn) 1962 1963 1964### FCVTXN ### 1965 1966FP convert to lower precision, rounding to odd. 1967 1968 void fcvtxn(const VRegister& vd, const VRegister& vn) 1969 1970 1971### FCVTXN2 ### 1972 1973FP convert to lower precision, rounding to odd (second part). 1974 1975 void fcvtxn2(const VRegister& vd, const VRegister& vn) 1976 1977 1978### FCVTZS ### 1979 1980FP convert to signed integer or fixed-point, round towards zero. 1981 1982 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) 1983 1984 1985### FCVTZS ### 1986 1987FP convert to signed integer or fixed-point, round towards zero. 1988 1989 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) 1990 1991 1992### FCVTZU ### 1993 1994FP convert to unsigned integer or fixed-point, round towards zero. 1995 1996 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) 1997 1998 1999### FCVTZU ### 2000 2001FP convert to unsigned integer or fixed-point, round towards zero. 2002 2003 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) 2004 2005 2006### FDIV ### 2007 2008FP divide. 2009 2010 void fdiv(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2011 2012 2013### FMADD ### 2014 2015FP fused multiply-add. 2016 2017 void fmadd(const VRegister& vd, 2018 const VRegister& vn, 2019 const VRegister& vm, 2020 const VRegister& va) 2021 2022 2023### FMAX ### 2024 2025FP maximum. 2026 2027 void fmax(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2028 2029 2030### FMAXNM ### 2031 2032FP maximum number. 2033 2034 void fmaxnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2035 2036 2037### FMAXNMP ### 2038 2039FP pairwise maximum number scalar. 2040 2041 void fmaxnmp(const VRegister& vd, const VRegister& vn) 2042 2043 2044### FMAXNMP ### 2045 2046FP pairwise maximum number vector. 2047 2048 void fmaxnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2049 2050 2051### FMAXNMV ### 2052 2053FP maximum number across vector. 2054 2055 void fmaxnmv(const VRegister& vd, const VRegister& vn) 2056 2057 2058### FMAXP ### 2059 2060FP pairwise maximum scalar. 2061 2062 void fmaxp(const VRegister& vd, const VRegister& vn) 2063 2064 2065### FMAXP ### 2066 2067FP pairwise maximum vector. 2068 2069 void fmaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2070 2071 2072### FMAXV ### 2073 2074FP maximum across vector. 2075 2076 void fmaxv(const VRegister& vd, const VRegister& vn) 2077 2078 2079### FMIN ### 2080 2081FP minimum. 2082 2083 void fmin(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2084 2085 2086### FMINNM ### 2087 2088FP minimum number. 2089 2090 void fminnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2091 2092 2093### FMINNMP ### 2094 2095FP pairwise minimum number scalar. 2096 2097 void fminnmp(const VRegister& vd, const VRegister& vn) 2098 2099 2100### FMINNMP ### 2101 2102FP pairwise minimum number vector. 2103 2104 void fminnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2105 2106 2107### FMINNMV ### 2108 2109FP minimum number across vector. 2110 2111 void fminnmv(const VRegister& vd, const VRegister& vn) 2112 2113 2114### FMINP ### 2115 2116FP pairwise minimum scalar. 2117 2118 void fminp(const VRegister& vd, const VRegister& vn) 2119 2120 2121### FMINP ### 2122 2123FP pairwise minimum vector. 2124 2125 void fminp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2126 2127 2128### FMINV ### 2129 2130FP minimum across vector. 2131 2132 void fminv(const VRegister& vd, const VRegister& vn) 2133 2134 2135### FMLA ### 2136 2137FP fused multiply-add to accumulator by element. 2138 2139 void fmla(const VRegister& vd, 2140 const VRegister& vn, 2141 const VRegister& vm, 2142 int vm_index) 2143 2144 2145### FMLA ### 2146 2147FP vector multiply accumulate. 2148 2149 void fmla(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2150 2151 2152### FMLS ### 2153 2154FP fused multiply-sub from accumulator by element. 2155 2156 void fmls(const VRegister& vd, 2157 const VRegister& vn, 2158 const VRegister& vm, 2159 int vm_index) 2160 2161 2162### FMLS ### 2163 2164FP vector multiply subtract. 2165 2166 void fmls(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2167 2168 2169### FMOV ### 2170 2171Move 64-bit register to top half of 128-bit FP register. 2172 2173 void fmov(const VRegister& vd, int index, const Register& rn) 2174 2175 2176### FMOV ### 2177 2178Move FP register to FP register. 2179 2180 void fmov(const VRegister& vd, const VRegister& fn) 2181 2182 2183### FMOV ### 2184 2185Move FP register to register. 2186 2187 void fmov(const Register& rd, const VRegister& fn) 2188 2189 2190### FMOV ### 2191 2192Move double precision immediate to FP register. 2193 2194 void fmov(const VRegister& vd, double imm) 2195 2196 2197### FMOV ### 2198 2199Move register to FP register. 2200 2201 void fmov(const VRegister& vd, const Register& rn) 2202 2203 2204### FMOV ### 2205 2206Move single precision immediate to FP register. 2207 2208 void fmov(const VRegister& vd, float imm) 2209 2210 2211### FMOV ### 2212 2213Move top half of 128-bit FP register to 64-bit register. 2214 2215 void fmov(const Register& rd, const VRegister& vn, int index) 2216 2217 2218### FMSUB ### 2219 2220FP fused multiply-subtract. 2221 2222 void fmsub(const VRegister& vd, 2223 const VRegister& vn, 2224 const VRegister& vm, 2225 const VRegister& va) 2226 2227 2228### FMUL ### 2229 2230FP multiply by element. 2231 2232 void fmul(const VRegister& vd, 2233 const VRegister& vn, 2234 const VRegister& vm, 2235 int vm_index) 2236 2237 2238### FMUL ### 2239 2240FP multiply. 2241 2242 void fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2243 2244 2245### FMULX ### 2246 2247FP multiply extended by element. 2248 2249 void fmulx(const VRegister& vd, 2250 const VRegister& vn, 2251 const VRegister& vm, 2252 int vm_index) 2253 2254 2255### FMULX ### 2256 2257FP vector multiply extended. 2258 2259 void fmulx(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2260 2261 2262### FNEG ### 2263 2264FP negate. 2265 2266 void fneg(const VRegister& vd, const VRegister& vn) 2267 2268 2269### FNMADD ### 2270 2271FP fused multiply-add and negate. 2272 2273 void fnmadd(const VRegister& vd, 2274 const VRegister& vn, 2275 const VRegister& vm, 2276 const VRegister& va) 2277 2278 2279### FNMSUB ### 2280 2281FP fused multiply-subtract and negate. 2282 2283 void fnmsub(const VRegister& vd, 2284 const VRegister& vn, 2285 const VRegister& vm, 2286 const VRegister& va) 2287 2288 2289### FNMUL ### 2290 2291FP multiply-negate scalar. 2292 2293 void fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2294 2295 2296### FRECPE ### 2297 2298FP reciprocal estimate. 2299 2300 void frecpe(const VRegister& vd, const VRegister& vn) 2301 2302 2303### FRECPS ### 2304 2305FP reciprocal step. 2306 2307 void frecps(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2308 2309 2310### FRECPX ### 2311 2312FP reciprocal exponent scalar. 2313 2314 void frecpx(const VRegister& vd, const VRegister& vn) 2315 2316 2317### FRINTA ### 2318 2319FP round to integer, nearest with ties to away. 2320 2321 void frinta(const VRegister& vd, const VRegister& vn) 2322 2323 2324### FRINTI ### 2325 2326FP round to integer, implicit rounding. 2327 2328 void frinti(const VRegister& vd, const VRegister& vn) 2329 2330 2331### FRINTM ### 2332 2333FP round to integer, toward minus infinity. 2334 2335 void frintm(const VRegister& vd, const VRegister& vn) 2336 2337 2338### FRINTN ### 2339 2340FP round to integer, nearest with ties to even. 2341 2342 void frintn(const VRegister& vd, const VRegister& vn) 2343 2344 2345### FRINTP ### 2346 2347FP round to integer, toward plus infinity. 2348 2349 void frintp(const VRegister& vd, const VRegister& vn) 2350 2351 2352### FRINTX ### 2353 2354FP round to integer, exact, implicit rounding. 2355 2356 void frintx(const VRegister& vd, const VRegister& vn) 2357 2358 2359### FRINTZ ### 2360 2361FP round to integer, towards zero. 2362 2363 void frintz(const VRegister& vd, const VRegister& vn) 2364 2365 2366### FRSQRTE ### 2367 2368FP reciprocal square root estimate. 2369 2370 void frsqrte(const VRegister& vd, const VRegister& vn) 2371 2372 2373### FRSQRTS ### 2374 2375FP reciprocal square root step. 2376 2377 void frsqrts(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2378 2379 2380### FSQRT ### 2381 2382FP square root. 2383 2384 void fsqrt(const VRegister& vd, const VRegister& vn) 2385 2386 2387### FSUB ### 2388 2389FP subtract. 2390 2391 void fsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2392 2393 2394### INS ### 2395 2396Insert vector element from another vector element. 2397 2398 void ins(const VRegister& vd, 2399 int vd_index, 2400 const VRegister& vn, 2401 int vn_index) 2402 2403 2404### INS ### 2405 2406Insert vector element from general-purpose register. 2407 2408 void ins(const VRegister& vd, int vd_index, const Register& rn) 2409 2410 2411### LD1 ### 2412 2413One-element single structure load to one lane. 2414 2415 void ld1(const VRegister& vt, int lane, const MemOperand& src) 2416 2417 2418### LD1 ### 2419 2420One-element structure load to four registers. 2421 2422 void ld1(const VRegister& vt, 2423 const VRegister& vt2, 2424 const VRegister& vt3, 2425 const VRegister& vt4, 2426 const MemOperand& src) 2427 2428 2429### LD1 ### 2430 2431One-element structure load to one register. 2432 2433 void ld1(const VRegister& vt, const MemOperand& src) 2434 2435 2436### LD1 ### 2437 2438One-element structure load to three registers. 2439 2440 void ld1(const VRegister& vt, 2441 const VRegister& vt2, 2442 const VRegister& vt3, 2443 const MemOperand& src) 2444 2445 2446### LD1 ### 2447 2448One-element structure load to two registers. 2449 2450 void ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 2451 2452 2453### LD1R ### 2454 2455One-element single structure load to all lanes. 2456 2457 void ld1r(const VRegister& vt, const MemOperand& src) 2458 2459 2460### LD2 ### 2461 2462Two-element single structure load to one lane. 2463 2464 void ld2(const VRegister& vt, 2465 const VRegister& vt2, 2466 int lane, 2467 const MemOperand& src) 2468 2469 2470### LD2 ### 2471 2472Two-element structure load. 2473 2474 void ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 2475 2476 2477### LD2R ### 2478 2479Two-element single structure load to all lanes. 2480 2481 void ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 2482 2483 2484### LD3 ### 2485 2486Three-element single structure load to one lane. 2487 2488 void ld3(const VRegister& vt, 2489 const VRegister& vt2, 2490 const VRegister& vt3, 2491 int lane, 2492 const MemOperand& src) 2493 2494 2495### LD3 ### 2496 2497Three-element structure load. 2498 2499 void ld3(const VRegister& vt, 2500 const VRegister& vt2, 2501 const VRegister& vt3, 2502 const MemOperand& src) 2503 2504 2505### LD3R ### 2506 2507Three-element single structure load to all lanes. 2508 2509 void ld3r(const VRegister& vt, 2510 const VRegister& vt2, 2511 const VRegister& vt3, 2512 const MemOperand& src) 2513 2514 2515### LD4 ### 2516 2517Four-element single structure load to one lane. 2518 2519 void ld4(const VRegister& vt, 2520 const VRegister& vt2, 2521 const VRegister& vt3, 2522 const VRegister& vt4, 2523 int lane, 2524 const MemOperand& src) 2525 2526 2527### LD4 ### 2528 2529Four-element structure load. 2530 2531 void ld4(const VRegister& vt, 2532 const VRegister& vt2, 2533 const VRegister& vt3, 2534 const VRegister& vt4, 2535 const MemOperand& src) 2536 2537 2538### LD4R ### 2539 2540Four-element single structure load to all lanes. 2541 2542 void ld4r(const VRegister& vt, 2543 const VRegister& vt2, 2544 const VRegister& vt3, 2545 const VRegister& vt4, 2546 const MemOperand& src) 2547 2548 2549### MLA ### 2550 2551Multiply-add by scalar element. 2552 2553 void mla(const VRegister& vd, 2554 const VRegister& vn, 2555 const VRegister& vm, 2556 int vm_index) 2557 2558 2559### MLA ### 2560 2561Multiply-add to accumulator. 2562 2563 void mla(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2564 2565 2566### MLS ### 2567 2568Multiply-subtract by scalar element. 2569 2570 void mls(const VRegister& vd, 2571 const VRegister& vn, 2572 const VRegister& vm, 2573 int vm_index) 2574 2575 2576### MLS ### 2577 2578Multiply-subtract to accumulator. 2579 2580 void mls(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2581 2582 2583### MOV ### 2584 2585Move general-purpose register to a vector element. 2586 2587 void mov(const VRegister& vd, int vd_index, const Register& rn) 2588 2589 2590### MOV ### 2591 2592Move register to register. 2593 2594 void mov(const VRegister& vd, const VRegister& vn) 2595 2596 2597### MOV ### 2598 2599Move vector element to another vector element. 2600 2601 void mov(const VRegister& vd, 2602 int vd_index, 2603 const VRegister& vn, 2604 int vn_index) 2605 2606 2607### MOV ### 2608 2609Move vector element to general-purpose register. 2610 2611 void mov(const Register& rd, const VRegister& vn, int vn_index) 2612 2613 2614### MOV ### 2615 2616Move vector element to scalar. 2617 2618 void mov(const VRegister& vd, const VRegister& vn, int vn_index) 2619 2620 2621### MOVI ### 2622 2623Vector move immediate. 2624 2625 void movi(const VRegister& vd, 2626 const uint64_t imm, 2627 Shift shift = LSL, 2628 const int shift_amount = 0) 2629 2630 2631### MUL ### 2632 2633Multiply by scalar element. 2634 2635 void mul(const VRegister& vd, 2636 const VRegister& vn, 2637 const VRegister& vm, 2638 int vm_index) 2639 2640 2641### MUL ### 2642 2643Multiply. 2644 2645 void mul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2646 2647 2648### MVN ### 2649 2650Bitwise not. 2651 2652 void mvn(const VRegister& vd, const VRegister& vn) 2653 2654 2655### MVNI ### 2656 2657Vector move inverted immediate. 2658 2659 void mvni(const VRegister& vd, 2660 const int imm8, 2661 Shift shift = LSL, 2662 const int shift_amount = 0) 2663 2664 2665### NEG ### 2666 2667Negate. 2668 2669 void neg(const VRegister& vd, const VRegister& vn) 2670 2671 2672### NOT ### 2673 2674Bitwise not. 2675 2676 void not_(const VRegister& vd, const VRegister& vn) 2677 2678 2679### ORN ### 2680 2681Bitwise orn. 2682 2683 void orn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2684 2685 2686### ORR ### 2687 2688Bitwise or immediate. 2689 2690 void orr(const VRegister& vd, const int imm8, const int left_shift = 0) 2691 2692 2693### ORR ### 2694 2695Bitwise or. 2696 2697 void orr(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2698 2699 2700### PMUL ### 2701 2702Polynomial multiply. 2703 2704 void pmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2705 2706 2707### PMULL ### 2708 2709Polynomial multiply long. 2710 2711 void pmull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2712 2713 2714### PMULL2 ### 2715 2716Polynomial multiply long (second part). 2717 2718 void pmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2719 2720 2721### RADDHN ### 2722 2723Rounding add narrow returning high half. 2724 2725 void raddhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2726 2727 2728### RADDHN2 ### 2729 2730Rounding add narrow returning high half (second part). 2731 2732 void raddhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2733 2734 2735### RBIT ### 2736 2737Reverse bit order. 2738 2739 void rbit(const VRegister& vd, const VRegister& vn) 2740 2741 2742### REV16 ### 2743 2744Reverse elements in 16-bit halfwords. 2745 2746 void rev16(const VRegister& vd, const VRegister& vn) 2747 2748 2749### REV32 ### 2750 2751Reverse elements in 32-bit words. 2752 2753 void rev32(const VRegister& vd, const VRegister& vn) 2754 2755 2756### REV64 ### 2757 2758Reverse elements in 64-bit doublewords. 2759 2760 void rev64(const VRegister& vd, const VRegister& vn) 2761 2762 2763### RSHRN ### 2764 2765Rounding shift right narrow by immediate. 2766 2767 void rshrn(const VRegister& vd, const VRegister& vn, int shift) 2768 2769 2770### RSHRN2 ### 2771 2772Rounding shift right narrow by immediate (second part). 2773 2774 void rshrn2(const VRegister& vd, const VRegister& vn, int shift) 2775 2776 2777### RSUBHN ### 2778 2779Rounding subtract narrow returning high half. 2780 2781 void rsubhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2782 2783 2784### RSUBHN2 ### 2785 2786Rounding subtract narrow returning high half (second part). 2787 2788 void rsubhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2789 2790 2791### SABA ### 2792 2793Signed absolute difference and accumulate. 2794 2795 void saba(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2796 2797 2798### SABAL ### 2799 2800Signed absolute difference and accumulate long. 2801 2802 void sabal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2803 2804 2805### SABAL2 ### 2806 2807Signed absolute difference and accumulate long (second part). 2808 2809 void sabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2810 2811 2812### SABD ### 2813 2814Signed absolute difference. 2815 2816 void sabd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2817 2818 2819### SABDL ### 2820 2821Signed absolute difference long. 2822 2823 void sabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2824 2825 2826### SABDL2 ### 2827 2828Signed absolute difference long (second part). 2829 2830 void sabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2831 2832 2833### SADALP ### 2834 2835Signed pairwise long add and accumulate. 2836 2837 void sadalp(const VRegister& vd, const VRegister& vn) 2838 2839 2840### SADDL ### 2841 2842Signed add long. 2843 2844 void saddl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2845 2846 2847### SADDL2 ### 2848 2849Signed add long (second part). 2850 2851 void saddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2852 2853 2854### SADDLP ### 2855 2856Signed pairwise long add. 2857 2858 void saddlp(const VRegister& vd, const VRegister& vn) 2859 2860 2861### SADDLV ### 2862 2863Signed add long across vector. 2864 2865 void saddlv(const VRegister& vd, const VRegister& vn) 2866 2867 2868### SADDW ### 2869 2870Signed add wide. 2871 2872 void saddw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2873 2874 2875### SADDW2 ### 2876 2877Signed add wide (second part). 2878 2879 void saddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2880 2881 2882### SCVTF ### 2883 2884Convert signed integer or fixed point to FP. 2885 2886 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0) 2887 2888 2889### SCVTF ### 2890 2891Convert signed integer or fixed-point to FP. 2892 2893 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 2894 2895 2896### SHADD ### 2897 2898Signed halving add. 2899 2900 void shadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2901 2902 2903### SHL ### 2904 2905Shift left by immediate. 2906 2907 void shl(const VRegister& vd, const VRegister& vn, int shift) 2908 2909 2910### SHLL ### 2911 2912Shift left long by element size. 2913 2914 void shll(const VRegister& vd, const VRegister& vn, int shift) 2915 2916 2917### SHLL2 ### 2918 2919Shift left long by element size (second part). 2920 2921 void shll2(const VRegister& vd, const VRegister& vn, int shift) 2922 2923 2924### SHRN ### 2925 2926Shift right narrow by immediate. 2927 2928 void shrn(const VRegister& vd, const VRegister& vn, int shift) 2929 2930 2931### SHRN2 ### 2932 2933Shift right narrow by immediate (second part). 2934 2935 void shrn2(const VRegister& vd, const VRegister& vn, int shift) 2936 2937 2938### SHSUB ### 2939 2940Signed halving sub. 2941 2942 void shsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2943 2944 2945### SLI ### 2946 2947Shift left by immediate and insert. 2948 2949 void sli(const VRegister& vd, const VRegister& vn, int shift) 2950 2951 2952### SMAX ### 2953 2954Signed maximum. 2955 2956 void smax(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2957 2958 2959### SMAXP ### 2960 2961Signed pairwise maximum. 2962 2963 void smaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2964 2965 2966### SMAXV ### 2967 2968Signed maximum across vector. 2969 2970 void smaxv(const VRegister& vd, const VRegister& vn) 2971 2972 2973### SMIN ### 2974 2975Signed minimum. 2976 2977 void smin(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2978 2979 2980### SMINP ### 2981 2982Signed minimum pairwise. 2983 2984 void sminp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2985 2986 2987### SMINV ### 2988 2989Signed minimum across vector. 2990 2991 void sminv(const VRegister& vd, const VRegister& vn) 2992 2993 2994### SMLAL ### 2995 2996Signed long multiply-add by scalar element. 2997 2998 void smlal(const VRegister& vd, 2999 const VRegister& vn, 3000 const VRegister& vm, 3001 int vm_index) 3002 3003 3004### SMLAL ### 3005 3006Signed long multiply-add. 3007 3008 void smlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3009 3010 3011### SMLAL2 ### 3012 3013Signed long multiply-add (second part). 3014 3015 void smlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3016 3017 3018### SMLAL2 ### 3019 3020Signed long multiply-add by scalar element (second part). 3021 3022 void smlal2(const VRegister& vd, 3023 const VRegister& vn, 3024 const VRegister& vm, 3025 int vm_index) 3026 3027 3028### SMLSL ### 3029 3030Signed long multiply-sub by scalar element. 3031 3032 void smlsl(const VRegister& vd, 3033 const VRegister& vn, 3034 const VRegister& vm, 3035 int vm_index) 3036 3037 3038### SMLSL ### 3039 3040Signed long multiply-sub. 3041 3042 void smlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3043 3044 3045### SMLSL2 ### 3046 3047Signed long multiply-sub (second part). 3048 3049 void smlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3050 3051 3052### SMLSL2 ### 3053 3054Signed long multiply-sub by scalar element (second part). 3055 3056 void smlsl2(const VRegister& vd, 3057 const VRegister& vn, 3058 const VRegister& vm, 3059 int vm_index) 3060 3061 3062### SMOV ### 3063 3064Signed move vector element to general-purpose register. 3065 3066 void smov(const Register& rd, const VRegister& vn, int vn_index) 3067 3068 3069### SMULL ### 3070 3071Signed long multiply by scalar element. 3072 3073 void smull(const VRegister& vd, 3074 const VRegister& vn, 3075 const VRegister& vm, 3076 int vm_index) 3077 3078 3079### SMULL ### 3080 3081Signed long multiply. 3082 3083 void smull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3084 3085 3086### SMULL2 ### 3087 3088Signed long multiply (second part). 3089 3090 void smull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3091 3092 3093### SMULL2 ### 3094 3095Signed long multiply by scalar element (second part). 3096 3097 void smull2(const VRegister& vd, 3098 const VRegister& vn, 3099 const VRegister& vm, 3100 int vm_index) 3101 3102 3103### SQABS ### 3104 3105Signed saturating absolute value. 3106 3107 void sqabs(const VRegister& vd, const VRegister& vn) 3108 3109 3110### SQADD ### 3111 3112Signed saturating add. 3113 3114 void sqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3115 3116 3117### SQDMLAL ### 3118 3119Signed saturating doubling long multiply-add by element. 3120 3121 void sqdmlal(const VRegister& vd, 3122 const VRegister& vn, 3123 const VRegister& vm, 3124 int vm_index) 3125 3126 3127### SQDMLAL ### 3128 3129Signed saturating doubling long multiply-add. 3130 3131 void sqdmlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3132 3133 3134### SQDMLAL2 ### 3135 3136Signed saturating doubling long multiply-add (second part). 3137 3138 void sqdmlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3139 3140 3141### SQDMLAL2 ### 3142 3143Signed saturating doubling long multiply-add by element (second part). 3144 3145 void sqdmlal2(const VRegister& vd, 3146 const VRegister& vn, 3147 const VRegister& vm, 3148 int vm_index) 3149 3150 3151### SQDMLSL ### 3152 3153Signed saturating doubling long multiply-sub by element. 3154 3155 void sqdmlsl(const VRegister& vd, 3156 const VRegister& vn, 3157 const VRegister& vm, 3158 int vm_index) 3159 3160 3161### SQDMLSL ### 3162 3163Signed saturating doubling long multiply-subtract. 3164 3165 void sqdmlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3166 3167 3168### SQDMLSL2 ### 3169 3170Signed saturating doubling long multiply-sub by element (second part). 3171 3172 void sqdmlsl2(const VRegister& vd, 3173 const VRegister& vn, 3174 const VRegister& vm, 3175 int vm_index) 3176 3177 3178### SQDMLSL2 ### 3179 3180Signed saturating doubling long multiply-subtract (second part). 3181 3182 void sqdmlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3183 3184 3185### SQDMULH ### 3186 3187Signed saturating doubling multiply element returning high half. 3188 3189 void sqdmulh(const VRegister& vd, 3190 const VRegister& vn, 3191 const VRegister& vm, 3192 int vm_index) 3193 3194 3195### SQDMULH ### 3196 3197Signed saturating doubling multiply returning high half. 3198 3199 void sqdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3200 3201 3202### SQDMULL ### 3203 3204Signed saturating double long multiply by element. 3205 3206 void sqdmull(const VRegister& vd, 3207 const VRegister& vn, 3208 const VRegister& vm, 3209 int vm_index) 3210 3211 3212### SQDMULL ### 3213 3214Signed saturating doubling long multiply. 3215 3216 void sqdmull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3217 3218 3219### SQDMULL2 ### 3220 3221Signed saturating double long multiply by element (second part). 3222 3223 void sqdmull2(const VRegister& vd, 3224 const VRegister& vn, 3225 const VRegister& vm, 3226 int vm_index) 3227 3228 3229### SQDMULL2 ### 3230 3231Signed saturating doubling long multiply (second part). 3232 3233 void sqdmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3234 3235 3236### SQNEG ### 3237 3238Signed saturating negate. 3239 3240 void sqneg(const VRegister& vd, const VRegister& vn) 3241 3242 3243### SQRDMULH ### 3244 3245Signed saturating rounding doubling multiply element returning high half. 3246 3247 void sqrdmulh(const VRegister& vd, 3248 const VRegister& vn, 3249 const VRegister& vm, 3250 int vm_index) 3251 3252 3253### SQRDMULH ### 3254 3255Signed saturating rounding doubling multiply returning high half. 3256 3257 void sqrdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3258 3259 3260### SQRSHL ### 3261 3262Signed saturating rounding shift left by register. 3263 3264 void sqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3265 3266 3267### SQRSHRN ### 3268 3269Signed saturating rounded shift right narrow by immediate. 3270 3271 void sqrshrn(const VRegister& vd, const VRegister& vn, int shift) 3272 3273 3274### SQRSHRN2 ### 3275 3276Signed saturating rounded shift right narrow by immediate (second part). 3277 3278 void sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) 3279 3280 3281### SQRSHRUN ### 3282 3283Signed sat rounded shift right unsigned narrow by immediate. 3284 3285 void sqrshrun(const VRegister& vd, const VRegister& vn, int shift) 3286 3287 3288### SQRSHRUN2 ### 3289 3290Signed sat rounded shift right unsigned narrow by immediate (second part). 3291 3292 void sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) 3293 3294 3295### SQSHL ### 3296 3297Signed saturating shift left by immediate. 3298 3299 void sqshl(const VRegister& vd, const VRegister& vn, int shift) 3300 3301 3302### SQSHL ### 3303 3304Signed saturating shift left by register. 3305 3306 void sqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3307 3308 3309### SQSHLU ### 3310 3311Signed saturating shift left unsigned by immediate. 3312 3313 void sqshlu(const VRegister& vd, const VRegister& vn, int shift) 3314 3315 3316### SQSHRN ### 3317 3318Signed saturating shift right narrow by immediate. 3319 3320 void sqshrn(const VRegister& vd, const VRegister& vn, int shift) 3321 3322 3323### SQSHRN2 ### 3324 3325Signed saturating shift right narrow by immediate (second part). 3326 3327 void sqshrn2(const VRegister& vd, const VRegister& vn, int shift) 3328 3329 3330### SQSHRUN ### 3331 3332Signed saturating shift right unsigned narrow by immediate. 3333 3334 void sqshrun(const VRegister& vd, const VRegister& vn, int shift) 3335 3336 3337### SQSHRUN2 ### 3338 3339Signed saturating shift right unsigned narrow by immediate (second part). 3340 3341 void sqshrun2(const VRegister& vd, const VRegister& vn, int shift) 3342 3343 3344### SQSUB ### 3345 3346Signed saturating subtract. 3347 3348 void sqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3349 3350 3351### SQXTN ### 3352 3353Signed saturating extract narrow. 3354 3355 void sqxtn(const VRegister& vd, const VRegister& vn) 3356 3357 3358### SQXTN2 ### 3359 3360Signed saturating extract narrow (second part). 3361 3362 void sqxtn2(const VRegister& vd, const VRegister& vn) 3363 3364 3365### SQXTUN ### 3366 3367Signed saturating extract unsigned narrow. 3368 3369 void sqxtun(const VRegister& vd, const VRegister& vn) 3370 3371 3372### SQXTUN2 ### 3373 3374Signed saturating extract unsigned narrow (second part). 3375 3376 void sqxtun2(const VRegister& vd, const VRegister& vn) 3377 3378 3379### SRHADD ### 3380 3381Signed rounding halving add. 3382 3383 void srhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3384 3385 3386### SRI ### 3387 3388Shift right by immediate and insert. 3389 3390 void sri(const VRegister& vd, const VRegister& vn, int shift) 3391 3392 3393### SRSHL ### 3394 3395Signed rounding shift left by register. 3396 3397 void srshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3398 3399 3400### SRSHR ### 3401 3402Signed rounding shift right by immediate. 3403 3404 void srshr(const VRegister& vd, const VRegister& vn, int shift) 3405 3406 3407### SRSRA ### 3408 3409Signed rounding shift right by immediate and accumulate. 3410 3411 void srsra(const VRegister& vd, const VRegister& vn, int shift) 3412 3413 3414### SSHL ### 3415 3416Signed shift left by register. 3417 3418 void sshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3419 3420 3421### SSHLL ### 3422 3423Signed shift left long by immediate. 3424 3425 void sshll(const VRegister& vd, const VRegister& vn, int shift) 3426 3427 3428### SSHLL2 ### 3429 3430Signed shift left long by immediate (second part). 3431 3432 void sshll2(const VRegister& vd, const VRegister& vn, int shift) 3433 3434 3435### SSHR ### 3436 3437Signed shift right by immediate. 3438 3439 void sshr(const VRegister& vd, const VRegister& vn, int shift) 3440 3441 3442### SSRA ### 3443 3444Signed shift right by immediate and accumulate. 3445 3446 void ssra(const VRegister& vd, const VRegister& vn, int shift) 3447 3448 3449### SSUBL ### 3450 3451Signed subtract long. 3452 3453 void ssubl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3454 3455 3456### SSUBL2 ### 3457 3458Signed subtract long (second part). 3459 3460 void ssubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3461 3462 3463### SSUBW ### 3464 3465Signed integer subtract wide. 3466 3467 void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3468 3469 3470### SSUBW2 ### 3471 3472Signed integer subtract wide (second part). 3473 3474 void ssubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3475 3476 3477### ST1 ### 3478 3479One-element single structure store from one lane. 3480 3481 void st1(const VRegister& vt, int lane, const MemOperand& src) 3482 3483 3484### ST1 ### 3485 3486One-element structure store from four registers. 3487 3488 void st1(const VRegister& vt, 3489 const VRegister& vt2, 3490 const VRegister& vt3, 3491 const VRegister& vt4, 3492 const MemOperand& src) 3493 3494 3495### ST1 ### 3496 3497One-element structure store from one register. 3498 3499 void st1(const VRegister& vt, const MemOperand& src) 3500 3501 3502### ST1 ### 3503 3504One-element structure store from three registers. 3505 3506 void st1(const VRegister& vt, 3507 const VRegister& vt2, 3508 const VRegister& vt3, 3509 const MemOperand& src) 3510 3511 3512### ST1 ### 3513 3514One-element structure store from two registers. 3515 3516 void st1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 3517 3518 3519### ST2 ### 3520 3521Two-element single structure store from two lanes. 3522 3523 void st2(const VRegister& vt, 3524 const VRegister& vt2, 3525 int lane, 3526 const MemOperand& src) 3527 3528 3529### ST2 ### 3530 3531Two-element structure store from two registers. 3532 3533 void st2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 3534 3535 3536### ST3 ### 3537 3538Three-element single structure store from three lanes. 3539 3540 void st3(const VRegister& vt, 3541 const VRegister& vt2, 3542 const VRegister& vt3, 3543 int lane, 3544 const MemOperand& src) 3545 3546 3547### ST3 ### 3548 3549Three-element structure store from three registers. 3550 3551 void st3(const VRegister& vt, 3552 const VRegister& vt2, 3553 const VRegister& vt3, 3554 const MemOperand& src) 3555 3556 3557### ST4 ### 3558 3559Four-element single structure store from four lanes. 3560 3561 void st4(const VRegister& vt, 3562 const VRegister& vt2, 3563 const VRegister& vt3, 3564 const VRegister& vt4, 3565 int lane, 3566 const MemOperand& src) 3567 3568 3569### ST4 ### 3570 3571Four-element structure store from four registers. 3572 3573 void st4(const VRegister& vt, 3574 const VRegister& vt2, 3575 const VRegister& vt3, 3576 const VRegister& vt4, 3577 const MemOperand& src) 3578 3579 3580### SUB ### 3581 3582Subtract. 3583 3584 void sub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3585 3586 3587### SUBHN ### 3588 3589Subtract narrow returning high half. 3590 3591 void subhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3592 3593 3594### SUBHN2 ### 3595 3596Subtract narrow returning high half (second part). 3597 3598 void subhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3599 3600 3601### SUQADD ### 3602 3603Signed saturating accumulate of unsigned value. 3604 3605 void suqadd(const VRegister& vd, const VRegister& vn) 3606 3607 3608### SXTL ### 3609 3610Signed extend long. 3611 3612 void sxtl(const VRegister& vd, const VRegister& vn) 3613 3614 3615### SXTL2 ### 3616 3617Signed extend long (second part). 3618 3619 void sxtl2(const VRegister& vd, const VRegister& vn) 3620 3621 3622### TBL ### 3623 3624Table lookup from four registers. 3625 3626 void tbl(const VRegister& vd, 3627 const VRegister& vn, 3628 const VRegister& vn2, 3629 const VRegister& vn3, 3630 const VRegister& vn4, 3631 const VRegister& vm) 3632 3633 3634### TBL ### 3635 3636Table lookup from one register. 3637 3638 void tbl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3639 3640 3641### TBL ### 3642 3643Table lookup from three registers. 3644 3645 void tbl(const VRegister& vd, 3646 const VRegister& vn, 3647 const VRegister& vn2, 3648 const VRegister& vn3, 3649 const VRegister& vm) 3650 3651 3652### TBL ### 3653 3654Table lookup from two registers. 3655 3656 void tbl(const VRegister& vd, 3657 const VRegister& vn, 3658 const VRegister& vn2, 3659 const VRegister& vm) 3660 3661 3662### TBX ### 3663 3664Table lookup extension from four registers. 3665 3666 void tbx(const VRegister& vd, 3667 const VRegister& vn, 3668 const VRegister& vn2, 3669 const VRegister& vn3, 3670 const VRegister& vn4, 3671 const VRegister& vm) 3672 3673 3674### TBX ### 3675 3676Table lookup extension from one register. 3677 3678 void tbx(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3679 3680 3681### TBX ### 3682 3683Table lookup extension from three registers. 3684 3685 void tbx(const VRegister& vd, 3686 const VRegister& vn, 3687 const VRegister& vn2, 3688 const VRegister& vn3, 3689 const VRegister& vm) 3690 3691 3692### TBX ### 3693 3694Table lookup extension from two registers. 3695 3696 void tbx(const VRegister& vd, 3697 const VRegister& vn, 3698 const VRegister& vn2, 3699 const VRegister& vm) 3700 3701 3702### TRN1 ### 3703 3704Transpose vectors (primary). 3705 3706 void trn1(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3707 3708 3709### TRN2 ### 3710 3711Transpose vectors (secondary). 3712 3713 void trn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3714 3715 3716### UABA ### 3717 3718Unsigned absolute difference and accumulate. 3719 3720 void uaba(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3721 3722 3723### UABAL ### 3724 3725Unsigned absolute difference and accumulate long. 3726 3727 void uabal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3728 3729 3730### UABAL2 ### 3731 3732Unsigned absolute difference and accumulate long (second part). 3733 3734 void uabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3735 3736 3737### UABD ### 3738 3739Unsigned absolute difference. 3740 3741 void uabd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3742 3743 3744### UABDL ### 3745 3746Unsigned absolute difference long. 3747 3748 void uabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3749 3750 3751### UABDL2 ### 3752 3753Unsigned absolute difference long (second part). 3754 3755 void uabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3756 3757 3758### UADALP ### 3759 3760Unsigned pairwise long add and accumulate. 3761 3762 void uadalp(const VRegister& vd, const VRegister& vn) 3763 3764 3765### UADDL ### 3766 3767Unsigned add long. 3768 3769 void uaddl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3770 3771 3772### UADDL2 ### 3773 3774Unsigned add long (second part). 3775 3776 void uaddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3777 3778 3779### UADDLP ### 3780 3781Unsigned pairwise long add. 3782 3783 void uaddlp(const VRegister& vd, const VRegister& vn) 3784 3785 3786### UADDLV ### 3787 3788Unsigned add long across vector. 3789 3790 void uaddlv(const VRegister& vd, const VRegister& vn) 3791 3792 3793### UADDW ### 3794 3795Unsigned add wide. 3796 3797 void uaddw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3798 3799 3800### UADDW2 ### 3801 3802Unsigned add wide (second part). 3803 3804 void uaddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3805 3806 3807### UCVTF ### 3808 3809Convert unsigned integer or fixed point to FP. 3810 3811 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0) 3812 3813 3814### UCVTF ### 3815 3816Convert unsigned integer or fixed-point to FP. 3817 3818 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 3819 3820 3821### UHADD ### 3822 3823Unsigned halving add. 3824 3825 void uhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3826 3827 3828### UHSUB ### 3829 3830Unsigned halving sub. 3831 3832 void uhsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3833 3834 3835### UMAX ### 3836 3837Unsigned maximum. 3838 3839 void umax(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3840 3841 3842### UMAXP ### 3843 3844Unsigned pairwise maximum. 3845 3846 void umaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3847 3848 3849### UMAXV ### 3850 3851Unsigned maximum across vector. 3852 3853 void umaxv(const VRegister& vd, const VRegister& vn) 3854 3855 3856### UMIN ### 3857 3858Unsigned minimum. 3859 3860 void umin(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3861 3862 3863### UMINP ### 3864 3865Unsigned pairwise minimum. 3866 3867 void uminp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3868 3869 3870### UMINV ### 3871 3872Unsigned minimum across vector. 3873 3874 void uminv(const VRegister& vd, const VRegister& vn) 3875 3876 3877### UMLAL ### 3878 3879Unsigned long multiply-add by scalar element. 3880 3881 void umlal(const VRegister& vd, 3882 const VRegister& vn, 3883 const VRegister& vm, 3884 int vm_index) 3885 3886 3887### UMLAL ### 3888 3889Unsigned long multiply-add. 3890 3891 void umlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3892 3893 3894### UMLAL2 ### 3895 3896Unsigned long multiply-add (second part). 3897 3898 void umlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3899 3900 3901### UMLAL2 ### 3902 3903Unsigned long multiply-add by scalar element (second part). 3904 3905 void umlal2(const VRegister& vd, 3906 const VRegister& vn, 3907 const VRegister& vm, 3908 int vm_index) 3909 3910 3911### UMLSL ### 3912 3913Unsigned long multiply-sub by scalar element. 3914 3915 void umlsl(const VRegister& vd, 3916 const VRegister& vn, 3917 const VRegister& vm, 3918 int vm_index) 3919 3920 3921### UMLSL ### 3922 3923Unsigned long multiply-sub. 3924 3925 void umlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3926 3927 3928### UMLSL2 ### 3929 3930Unsigned long multiply-sub (second part). 3931 3932 void umlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3933 3934 3935### UMLSL2 ### 3936 3937Unsigned long multiply-sub by scalar element (second part). 3938 3939 void umlsl2(const VRegister& vd, 3940 const VRegister& vn, 3941 const VRegister& vm, 3942 int vm_index) 3943 3944 3945### UMOV ### 3946 3947Unsigned move vector element to general-purpose register. 3948 3949 void umov(const Register& rd, const VRegister& vn, int vn_index) 3950 3951 3952### UMULL ### 3953 3954Unsigned long multiply by scalar element. 3955 3956 void umull(const VRegister& vd, 3957 const VRegister& vn, 3958 const VRegister& vm, 3959 int vm_index) 3960 3961 3962### UMULL ### 3963 3964Unsigned long multiply long. 3965 3966 void umull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3967 3968 3969### UMULL2 ### 3970 3971Unsigned long multiply (second part). 3972 3973 void umull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3974 3975 3976### UMULL2 ### 3977 3978Unsigned long multiply by scalar element (second part). 3979 3980 void umull2(const VRegister& vd, 3981 const VRegister& vn, 3982 const VRegister& vm, 3983 int vm_index) 3984 3985 3986### UQADD ### 3987 3988Unsigned saturating add. 3989 3990 void uqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3991 3992 3993### UQRSHL ### 3994 3995Unsigned saturating rounding shift left by register. 3996 3997 void uqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3998 3999 4000### UQRSHRN ### 4001 4002Unsigned saturating rounding shift right narrow by immediate. 4003 4004 void uqrshrn(const VRegister& vd, const VRegister& vn, int shift) 4005 4006 4007### UQRSHRN2 ### 4008 4009Unsigned saturating rounding shift right narrow by immediate (second part). 4010 4011 void uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) 4012 4013 4014### UQSHL ### 4015 4016Unsigned saturating shift left by immediate. 4017 4018 void uqshl(const VRegister& vd, const VRegister& vn, int shift) 4019 4020 4021### UQSHL ### 4022 4023Unsigned saturating shift left by register. 4024 4025 void uqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4026 4027 4028### UQSHRN ### 4029 4030Unsigned saturating shift right narrow by immediate. 4031 4032 void uqshrn(const VRegister& vd, const VRegister& vn, int shift) 4033 4034 4035### UQSHRN2 ### 4036 4037Unsigned saturating shift right narrow by immediate (second part). 4038 4039 void uqshrn2(const VRegister& vd, const VRegister& vn, int shift) 4040 4041 4042### UQSUB ### 4043 4044Unsigned saturating subtract. 4045 4046 void uqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4047 4048 4049### UQXTN ### 4050 4051Unsigned saturating extract narrow. 4052 4053 void uqxtn(const VRegister& vd, const VRegister& vn) 4054 4055 4056### UQXTN2 ### 4057 4058Unsigned saturating extract narrow (second part). 4059 4060 void uqxtn2(const VRegister& vd, const VRegister& vn) 4061 4062 4063### URECPE ### 4064 4065Unsigned reciprocal estimate. 4066 4067 void urecpe(const VRegister& vd, const VRegister& vn) 4068 4069 4070### URHADD ### 4071 4072Unsigned rounding halving add. 4073 4074 void urhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4075 4076 4077### URSHL ### 4078 4079Unsigned rounding shift left by register. 4080 4081 void urshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4082 4083 4084### URSHR ### 4085 4086Unsigned rounding shift right by immediate. 4087 4088 void urshr(const VRegister& vd, const VRegister& vn, int shift) 4089 4090 4091### URSQRTE ### 4092 4093Unsigned reciprocal square root estimate. 4094 4095 void ursqrte(const VRegister& vd, const VRegister& vn) 4096 4097 4098### URSRA ### 4099 4100Unsigned rounding shift right by immediate and accumulate. 4101 4102 void ursra(const VRegister& vd, const VRegister& vn, int shift) 4103 4104 4105### USHL ### 4106 4107Unsigned shift left by register. 4108 4109 void ushl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4110 4111 4112### USHLL ### 4113 4114Unsigned shift left long by immediate. 4115 4116 void ushll(const VRegister& vd, const VRegister& vn, int shift) 4117 4118 4119### USHLL2 ### 4120 4121Unsigned shift left long by immediate (second part). 4122 4123 void ushll2(const VRegister& vd, const VRegister& vn, int shift) 4124 4125 4126### USHR ### 4127 4128Unsigned shift right by immediate. 4129 4130 void ushr(const VRegister& vd, const VRegister& vn, int shift) 4131 4132 4133### USQADD ### 4134 4135Unsigned saturating accumulate of signed value. 4136 4137 void usqadd(const VRegister& vd, const VRegister& vn) 4138 4139 4140### USRA ### 4141 4142Unsigned shift right by immediate and accumulate. 4143 4144 void usra(const VRegister& vd, const VRegister& vn, int shift) 4145 4146 4147### USUBL ### 4148 4149Unsigned subtract long. 4150 4151 void usubl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4152 4153 4154### USUBL2 ### 4155 4156Unsigned subtract long (second part). 4157 4158 void usubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4159 4160 4161### USUBW ### 4162 4163Unsigned subtract wide. 4164 4165 void usubw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4166 4167 4168### USUBW2 ### 4169 4170Unsigned subtract wide (second part). 4171 4172 void usubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4173 4174 4175### UXTL ### 4176 4177Unsigned extend long. 4178 4179 void uxtl(const VRegister& vd, const VRegister& vn) 4180 4181 4182### UXTL2 ### 4183 4184Unsigned extend long (second part). 4185 4186 void uxtl2(const VRegister& vd, const VRegister& vn) 4187 4188 4189### UZP1 ### 4190 4191Unzip vectors (primary). 4192 4193 void uzp1(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4194 4195 4196### UZP2 ### 4197 4198Unzip vectors (secondary). 4199 4200 void uzp2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4201 4202 4203### XTN ### 4204 4205Extract narrow. 4206 4207 void xtn(const VRegister& vd, const VRegister& vn) 4208 4209 4210### XTN2 ### 4211 4212Extract narrow (second part). 4213 4214 void xtn2(const VRegister& vd, const VRegister& vn) 4215 4216 4217### ZIP1 ### 4218 4219Zip vectors (primary). 4220 4221 void zip1(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4222 4223 4224### ZIP2 ### 4225 4226Zip vectors (secondary). 4227 4228 void zip2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4229 4230 4231 4232Additional or pseudo instructions 4233--------------------------------- 4234 4235### BIND ### 4236 4237Bind a label to the current PC. 4238 4239 void bind(Label* label) 4240 4241 4242### DC32 ### 4243 4244Emit 32 bits of data into the instruction stream. 4245 4246 void dc32(uint32_t data) 4247 4248 4249### DC64 ### 4250 4251Emit 64 bits of data into the instruction stream. 4252 4253 void dc64(uint64_t data) 4254 4255 4256### DCI ### 4257 4258Emit raw instructions into the instruction stream. 4259 4260 void dci(Instr raw_inst) 4261 4262 4263### PLACE ### 4264 4265Place a literal at the current PC. 4266 4267 void place(RawLiteral* literal) 4268 4269 4270 4271