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1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares codegen opcodes and related utilities.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_ISDOPCODES_H
15 #define LLVM_CODEGEN_ISDOPCODES_H
16 
17 namespace llvm {
18 
19 /// ISD namespace - This namespace contains an enum which represents all of the
20 /// SelectionDAG node types and value types.
21 ///
22 namespace ISD {
23 
24   //===--------------------------------------------------------------------===//
25   /// ISD::NodeType enum - This enum defines the target-independent operators
26   /// for a SelectionDAG.
27   ///
28   /// Targets may also define target-dependent operator codes for SDNodes. For
29   /// example, on x86, these are the enum values in the X86ISD namespace.
30   /// Targets should aim to use target-independent operators to model their
31   /// instruction sets as much as possible, and only use target-dependent
32   /// operators when they have special requirements.
33   ///
34   /// Finally, during and after selection proper, SNodes may use special
35   /// operator codes that correspond directly with MachineInstr opcodes. These
36   /// are used to represent selected instructions. See the isMachineOpcode()
37   /// and getMachineOpcode() member functions of SDNode.
38   ///
39   enum NodeType {
40     /// DELETED_NODE - This is an illegal value that is used to catch
41     /// errors.  This opcode is not a legal opcode for any node.
42     DELETED_NODE,
43 
44     /// EntryToken - This is the marker used to indicate the start of a region.
45     EntryToken,
46 
47     /// TokenFactor - This node takes multiple tokens as input and produces a
48     /// single token result. This is used to represent the fact that the operand
49     /// operators are independent of each other.
50     TokenFactor,
51 
52     /// AssertSext, AssertZext - These nodes record if a register contains a
53     /// value that has already been zero or sign extended from a narrower type.
54     /// These nodes take two operands.  The first is the node that has already
55     /// been extended, and the second is a value type node indicating the width
56     /// of the extension
57     AssertSext, AssertZext,
58 
59     /// Various leaf nodes.
60     BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
61     Constant, ConstantFP,
62     GlobalAddress, GlobalTLSAddress, FrameIndex,
63     JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
64 
65     /// The address of the GOT
66     GLOBAL_OFFSET_TABLE,
67 
68     /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
69     /// llvm.returnaddress on the DAG.  These nodes take one operand, the index
70     /// of the frame or return address to return.  An index of zero corresponds
71     /// to the current function's frame or return address, an index of one to
72     /// the parent's frame or return address, and so on.
73     FRAMEADDR, RETURNADDR, ADDROFRETURNADDR,
74 
75     /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
76     /// Materializes the offset from the local object pointer of another
77     /// function to a particular local object passed to llvm.localescape. The
78     /// operand is the MCSymbol label used to represent this offset, since
79     /// typically the offset is not known until after code generation of the
80     /// parent.
81     LOCAL_RECOVER,
82 
83     /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
84     /// the DAG, which implements the named register global variables extension.
85     READ_REGISTER,
86     WRITE_REGISTER,
87 
88     /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
89     /// first (possible) on-stack argument. This is needed for correct stack
90     /// adjustment during unwind.
91     FRAME_TO_ARGS_OFFSET,
92 
93     /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical
94     /// Frame Address (CFA), generally the value of the stack pointer at the
95     /// call site in the previous frame.
96     EH_DWARF_CFA,
97 
98     /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
99     /// 'eh_return' gcc dwarf builtin, which is used to return from
100     /// exception. The general meaning is: adjust stack by OFFSET and pass
101     /// execution to HANDLER. Many platform-related details also :)
102     EH_RETURN,
103 
104     /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
105     /// This corresponds to the eh.sjlj.setjmp intrinsic.
106     /// It takes an input chain and a pointer to the jump buffer as inputs
107     /// and returns an outchain.
108     EH_SJLJ_SETJMP,
109 
110     /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
111     /// This corresponds to the eh.sjlj.longjmp intrinsic.
112     /// It takes an input chain and a pointer to the jump buffer as inputs
113     /// and returns an outchain.
114     EH_SJLJ_LONGJMP,
115 
116     /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
117     /// The target initializes the dispatch table here.
118     EH_SJLJ_SETUP_DISPATCH,
119 
120     /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
121     /// simplification, or lowering of the constant. They are used for constants
122     /// which are known to fit in the immediate fields of their users, or for
123     /// carrying magic numbers which are not values which need to be
124     /// materialized in registers.
125     TargetConstant,
126     TargetConstantFP,
127 
128     /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
129     /// anything else with this node, and this is valid in the target-specific
130     /// dag, turning into a GlobalAddress operand.
131     TargetGlobalAddress,
132     TargetGlobalTLSAddress,
133     TargetFrameIndex,
134     TargetJumpTable,
135     TargetConstantPool,
136     TargetExternalSymbol,
137     TargetBlockAddress,
138 
139     MCSymbol,
140 
141     /// TargetIndex - Like a constant pool entry, but with completely
142     /// target-dependent semantics. Holds target flags, a 32-bit index, and a
143     /// 64-bit index. Targets can use this however they like.
144     TargetIndex,
145 
146     /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
147     /// This node represents a target intrinsic function with no side effects.
148     /// The first operand is the ID number of the intrinsic from the
149     /// llvm::Intrinsic namespace.  The operands to the intrinsic follow.  The
150     /// node returns the result of the intrinsic.
151     INTRINSIC_WO_CHAIN,
152 
153     /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
154     /// This node represents a target intrinsic function with side effects that
155     /// returns a result.  The first operand is a chain pointer.  The second is
156     /// the ID number of the intrinsic from the llvm::Intrinsic namespace.  The
157     /// operands to the intrinsic follow.  The node has two results, the result
158     /// of the intrinsic and an output chain.
159     INTRINSIC_W_CHAIN,
160 
161     /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
162     /// This node represents a target intrinsic function with side effects that
163     /// does not return a result.  The first operand is a chain pointer.  The
164     /// second is the ID number of the intrinsic from the llvm::Intrinsic
165     /// namespace.  The operands to the intrinsic follow.
166     INTRINSIC_VOID,
167 
168     /// CopyToReg - This node has three operands: a chain, a register number to
169     /// set to this value, and a value.
170     CopyToReg,
171 
172     /// CopyFromReg - This node indicates that the input value is a virtual or
173     /// physical register that is defined outside of the scope of this
174     /// SelectionDAG.  The register is available from the RegisterSDNode object.
175     CopyFromReg,
176 
177     /// UNDEF - An undefined node.
178     UNDEF,
179 
180     /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
181     /// a Constant, which is required to be operand #1) half of the integer or
182     /// float value specified as operand #0.  This is only for use before
183     /// legalization, for values that will be broken into multiple registers.
184     EXTRACT_ELEMENT,
185 
186     /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
187     /// Given two values of the same integer value type, this produces a value
188     /// twice as big.  Like EXTRACT_ELEMENT, this can only be used before
189     /// legalization. The lower part of the composite value should be in
190     /// element 0 and the upper part should be in element 1.
191     BUILD_PAIR,
192 
193     /// MERGE_VALUES - This node takes multiple discrete operands and returns
194     /// them all as its individual results.  This nodes has exactly the same
195     /// number of inputs and outputs. This node is useful for some pieces of the
196     /// code generator that want to think about a single node with multiple
197     /// results, not multiple nodes.
198     MERGE_VALUES,
199 
200     /// Simple integer binary arithmetic operators.
201     ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
202 
203     /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
204     /// a signed/unsigned value of type i[2*N], and return the full value as
205     /// two results, each of type iN.
206     SMUL_LOHI, UMUL_LOHI,
207 
208     /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
209     /// remainder result.
210     SDIVREM, UDIVREM,
211 
212     /// CARRY_FALSE - This node is used when folding other nodes,
213     /// like ADDC/SUBC, which indicate the carry result is always false.
214     CARRY_FALSE,
215 
216     /// Carry-setting nodes for multiple precision addition and subtraction.
217     /// These nodes take two operands of the same value type, and produce two
218     /// results.  The first result is the normal add or sub result, the second
219     /// result is the carry flag result.
220     /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
221     /// They are kept around for now to provide a smooth transition path
222     /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
223     ADDC, SUBC,
224 
225     /// Carry-using nodes for multiple precision addition and subtraction. These
226     /// nodes take three operands: The first two are the normal lhs and rhs to
227     /// the add or sub, and the third is the input carry flag.  These nodes
228     /// produce two results; the normal result of the add or sub, and the output
229     /// carry flag.  These nodes both read and write a carry flag to allow them
230     /// to them to be chained together for add and sub of arbitrarily large
231     /// values.
232     ADDE, SUBE,
233 
234     /// Carry-using nodes for multiple precision addition and subtraction.
235     /// These nodes take three operands: The first two are the normal lhs and
236     /// rhs to the add or sub, and the third is a boolean indicating if there
237     /// is an incoming carry. These nodes produce two results: the normal
238     /// result of the add or sub, and the output carry so they can be chained
239     /// together. The use of this opcode is preferable to adde/sube if the
240     /// target supports it, as the carry is a regular value rather than a
241     /// glue, which allows further optimisation.
242     ADDCARRY, SUBCARRY,
243 
244     /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
245     /// These nodes take two operands: the normal LHS and RHS to the add. They
246     /// produce two results: the normal result of the add, and a boolean that
247     /// indicates if an overflow occurred (*not* a flag, because it may be store
248     /// to memory, etc.).  If the type of the boolean is not i1 then the high
249     /// bits conform to getBooleanContents.
250     /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
251     SADDO, UADDO,
252 
253     /// Same for subtraction.
254     SSUBO, USUBO,
255 
256     /// Same for multiplication.
257     SMULO, UMULO,
258 
259     /// Simple binary floating point operators.
260     FADD, FSUB, FMUL, FDIV, FREM,
261 
262     /// Constrained versions of the binary floating point operators.
263     /// These will be lowered to the simple operators before final selection.
264     /// They are used to limit optimizations while the DAG is being
265     /// optimized.
266     STRICT_FADD, STRICT_FSUB, STRICT_FMUL, STRICT_FDIV, STRICT_FREM,
267     STRICT_FMA,
268 
269     /// Constrained versions of libm-equivalent floating point intrinsics.
270     /// These will be lowered to the equivalent non-constrained pseudo-op
271     /// (or expanded to the equivalent library call) before final selection.
272     /// They are used to limit optimizations while the DAG is being optimized.
273     STRICT_FSQRT, STRICT_FPOW, STRICT_FPOWI, STRICT_FSIN, STRICT_FCOS,
274     STRICT_FEXP, STRICT_FEXP2, STRICT_FLOG, STRICT_FLOG10, STRICT_FLOG2,
275     STRICT_FRINT, STRICT_FNEARBYINT,
276 
277     /// FMA - Perform a * b + c with no intermediate rounding step.
278     FMA,
279 
280     /// FMAD - Perform a * b + c, while getting the same result as the
281     /// separately rounded operations.
282     FMAD,
283 
284     /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.  NOTE: This
285     /// DAG node does not require that X and Y have the same type, just that
286     /// they are both floating point.  X and the result must have the same type.
287     /// FCOPYSIGN(f32, f64) is allowed.
288     FCOPYSIGN,
289 
290     /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
291     /// value as an integer 0/1 value.
292     FGETSIGN,
293 
294     /// Returns platform specific canonical encoding of a floating point number.
295     FCANONICALIZE,
296 
297     /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
298     /// specified, possibly variable, elements.  The number of elements is
299     /// required to be a power of two.  The types of the operands must all be
300     /// the same and must match the vector element type, except that integer
301     /// types are allowed to be larger than the element type, in which case
302     /// the operands are implicitly truncated.
303     BUILD_VECTOR,
304 
305     /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
306     /// at IDX replaced with VAL.  If the type of VAL is larger than the vector
307     /// element type then VAL is truncated before replacement.
308     INSERT_VECTOR_ELT,
309 
310     /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
311     /// identified by the (potentially variable) element number IDX.  If the
312     /// return type is an integer type larger than the element type of the
313     /// vector, the result is extended to the width of the return type. In
314     /// that case, the high bits are undefined.
315     EXTRACT_VECTOR_ELT,
316 
317     /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
318     /// vector type with the same length and element type, this produces a
319     /// concatenated vector result value, with length equal to the sum of the
320     /// lengths of the input vectors.
321     CONCAT_VECTORS,
322 
323     /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
324     /// with VECTOR2 inserted into VECTOR1 at the (potentially
325     /// variable) element number IDX, which must be a multiple of the
326     /// VECTOR2 vector length.  The elements of VECTOR1 starting at
327     /// IDX are overwritten with VECTOR2.  Elements IDX through
328     /// vector_length(VECTOR2) must be valid VECTOR1 indices.
329     INSERT_SUBVECTOR,
330 
331     /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
332     /// vector value) starting with the element number IDX, which must be a
333     /// constant multiple of the result vector length.
334     EXTRACT_SUBVECTOR,
335 
336     /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
337     /// VEC1/VEC2.  A VECTOR_SHUFFLE node also contains an array of constant int
338     /// values that indicate which value (or undef) each result element will
339     /// get.  These constant ints are accessible through the
340     /// ShuffleVectorSDNode class.  This is quite similar to the Altivec
341     /// 'vperm' instruction, except that the indices must be constants and are
342     /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
343     VECTOR_SHUFFLE,
344 
345     /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
346     /// scalar value into element 0 of the resultant vector type.  The top
347     /// elements 1 to N-1 of the N-element vector are undefined.  The type
348     /// of the operand must match the vector element type, except when they
349     /// are integer types.  In this case the operand is allowed to be wider
350     /// than the vector element type, and is implicitly truncated to it.
351     SCALAR_TO_VECTOR,
352 
353     /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
354     /// producing an unsigned/signed value of type i[2*N], then return the top
355     /// part.
356     MULHU, MULHS,
357 
358     /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned
359     /// integers.
360     SMIN, SMAX, UMIN, UMAX,
361 
362     /// Bitwise operators - logical and, logical or, logical xor.
363     AND, OR, XOR,
364 
365     /// ABS - Determine the unsigned absolute value of a signed integer value of
366     /// the same bitwidth.
367     /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
368     /// is performed.
369     ABS,
370 
371     /// Shift and rotation operations.  After legalization, the type of the
372     /// shift amount is known to be TLI.getShiftAmountTy().  Before legalization
373     /// the shift amount can be any type, but care must be taken to ensure it is
374     /// large enough.  TLI.getShiftAmountTy() is i8 on some targets, but before
375     /// legalization, types like i1024 can occur and i8 doesn't have enough bits
376     /// to represent the shift amount.
377     /// When the 1st operand is a vector, the shift amount must be in the same
378     /// type. (TLI.getShiftAmountTy() will return the same type when the input
379     /// type is a vector.)
380     /// For rotates, the shift amount is treated as an unsigned amount modulo
381     /// the element size of the first operand.
382     SHL, SRA, SRL, ROTL, ROTR,
383 
384     /// Byte Swap and Counting operators.
385     BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE,
386 
387     /// Bit counting operators with an undefined result for zero inputs.
388     CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
389 
390     /// Select(COND, TRUEVAL, FALSEVAL).  If the type of the boolean COND is not
391     /// i1 then the high bits must conform to getBooleanContents.
392     SELECT,
393 
394     /// Select with a vector condition (op #0) and two vector operands (ops #1
395     /// and #2), returning a vector result.  All vectors have the same length.
396     /// Much like the scalar select and setcc, each bit in the condition selects
397     /// whether the corresponding result element is taken from op #1 or op #2.
398     /// At first, the VSELECT condition is of vXi1 type. Later, targets may
399     /// change the condition type in order to match the VSELECT node using a
400     /// pattern. The condition follows the BooleanContent format of the target.
401     VSELECT,
402 
403     /// Select with condition operator - This selects between a true value and
404     /// a false value (ops #2 and #3) based on the boolean result of comparing
405     /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
406     /// condition code in op #4, a CondCodeSDNode.
407     SELECT_CC,
408 
409     /// SetCC operator - This evaluates to a true value iff the condition is
410     /// true.  If the result value type is not i1 then the high bits conform
411     /// to getBooleanContents.  The operands to this are the left and right
412     /// operands to compare (ops #0, and #1) and the condition code to compare
413     /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
414     /// then the result type must also be a vector type.
415     SETCC,
416 
417     /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
418     /// op #2 is a boolean indicating if there is an incoming carry. This
419     /// operator checks the result of "LHS - RHS - Carry", and can be used to
420     /// compare two wide integers:
421     /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc).
422     /// Only valid for integers.
423     SETCCCARRY,
424 
425     /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
426     /// integer shift operations.  The operation ordering is:
427     ///       [Lo,Hi] = op [LoLHS,HiLHS], Amt
428     SHL_PARTS, SRA_PARTS, SRL_PARTS,
429 
430     /// Conversion operators.  These are all single input single output
431     /// operations.  For all of these, the result type must be strictly
432     /// wider or narrower (depending on the operation) than the source
433     /// type.
434 
435     /// SIGN_EXTEND - Used for integer types, replicating the sign bit
436     /// into new bits.
437     SIGN_EXTEND,
438 
439     /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
440     ZERO_EXTEND,
441 
442     /// ANY_EXTEND - Used for integer types.  The high bits are undefined.
443     ANY_EXTEND,
444 
445     /// TRUNCATE - Completely drop the high bits.
446     TRUNCATE,
447 
448     /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
449     /// depends on the first letter) to floating point.
450     SINT_TO_FP,
451     UINT_TO_FP,
452 
453     /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
454     /// sign extend a small value in a large integer register (e.g. sign
455     /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
456     /// with the 7th bit).  The size of the smaller type is indicated by the 1th
457     /// operand, a ValueType node.
458     SIGN_EXTEND_INREG,
459 
460     /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
461     /// in-register any-extension of the low lanes of an integer vector. The
462     /// result type must have fewer elements than the operand type, and those
463     /// elements must be larger integer types such that the total size of the
464     /// operand type and the result type match. Each of the low operand
465     /// elements is any-extended into the corresponding, wider result
466     /// elements with the high bits becoming undef.
467     ANY_EXTEND_VECTOR_INREG,
468 
469     /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
470     /// in-register sign-extension of the low lanes of an integer vector. The
471     /// result type must have fewer elements than the operand type, and those
472     /// elements must be larger integer types such that the total size of the
473     /// operand type and the result type match. Each of the low operand
474     /// elements is sign-extended into the corresponding, wider result
475     /// elements.
476     // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to
477     // scalars, but it also doesn't handle vectors well. Either it should be
478     // restricted to scalars or this node (and its handling) should be merged
479     // into it.
480     SIGN_EXTEND_VECTOR_INREG,
481 
482     /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
483     /// in-register zero-extension of the low lanes of an integer vector. The
484     /// result type must have fewer elements than the operand type, and those
485     /// elements must be larger integer types such that the total size of the
486     /// operand type and the result type match. Each of the low operand
487     /// elements is zero-extended into the corresponding, wider result
488     /// elements.
489     ZERO_EXTEND_VECTOR_INREG,
490 
491     /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
492     /// integer. These have the same semantics as fptosi and fptoui in IR. If
493     /// the FP value cannot fit in the integer type, the results are undefined.
494     FP_TO_SINT,
495     FP_TO_UINT,
496 
497     /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
498     /// down to the precision of the destination VT.  TRUNC is a flag, which is
499     /// always an integer that is zero or one.  If TRUNC is 0, this is a
500     /// normal rounding, if it is 1, this FP_ROUND is known to not change the
501     /// value of Y.
502     ///
503     /// The TRUNC = 1 case is used in cases where we know that the value will
504     /// not be modified by the node, because Y is not using any of the extra
505     /// precision of source type.  This allows certain transformations like
506     /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
507     /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
508     FP_ROUND,
509 
510     /// FLT_ROUNDS_ - Returns current rounding mode:
511     /// -1 Undefined
512     ///  0 Round to 0
513     ///  1 Round to nearest
514     ///  2 Round to +inf
515     ///  3 Round to -inf
516     FLT_ROUNDS_,
517 
518     /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
519     /// rounds it to a floating point value.  It then promotes it and returns it
520     /// in a register of the same size.  This operation effectively just
521     /// discards excess precision.  The type to round down to is specified by
522     /// the VT operand, a VTSDNode.
523     FP_ROUND_INREG,
524 
525     /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
526     FP_EXTEND,
527 
528     /// BITCAST - This operator converts between integer, vector and FP
529     /// values, as if the value was stored to memory with one type and loaded
530     /// from the same address with the other type (or equivalently for vector
531     /// format conversions, etc).  The source and result are required to have
532     /// the same bit size (e.g.  f32 <-> i32).  This can also be used for
533     /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
534     /// getNode().
535     ///
536     /// This operator is subtly different from the bitcast instruction from
537     /// LLVM-IR since this node may change the bits in the register. For
538     /// example, this occurs on big-endian NEON and big-endian MSA where the
539     /// layout of the bits in the register depends on the vector type and this
540     /// operator acts as a shuffle operation for some vector type combinations.
541     BITCAST,
542 
543     /// ADDRSPACECAST - This operator converts between pointers of different
544     /// address spaces.
545     ADDRSPACECAST,
546 
547     /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
548     /// and truncation for half-precision (16 bit) floating numbers. These nodes
549     /// form a semi-softened interface for dealing with f16 (as an i16), which
550     /// is often a storage-only type but has native conversions.
551     FP16_TO_FP, FP_TO_FP16,
552 
553     /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
554     /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
555     /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary
556     /// floating point operations. These are inspired by libm.
557     FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
558     FLOG, FLOG2, FLOG10, FEXP, FEXP2,
559     FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
560     /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
561     /// values.
562     /// In the case where a single input is NaN, the non-NaN input is returned.
563     ///
564     /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
565     FMINNUM, FMAXNUM,
566     /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that
567     /// when a single input is NaN, NaN is returned.
568     FMINNAN, FMAXNAN,
569 
570     /// FSINCOS - Compute both fsin and fcos as a single operation.
571     FSINCOS,
572 
573     /// LOAD and STORE have token chains as their first operand, then the same
574     /// operands as an LLVM load/store instruction, then an offset node that
575     /// is added / subtracted from the base pointer to form the address (for
576     /// indexed memory ops).
577     LOAD, STORE,
578 
579     /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
580     /// to a specified boundary.  This node always has two return values: a new
581     /// stack pointer value and a chain. The first operand is the token chain,
582     /// the second is the number of bytes to allocate, and the third is the
583     /// alignment boundary.  The size is guaranteed to be a multiple of the
584     /// stack alignment, and the alignment is guaranteed to be bigger than the
585     /// stack alignment (if required) or 0 to get standard stack alignment.
586     DYNAMIC_STACKALLOC,
587 
588     /// Control flow instructions.  These all have token chains.
589 
590     /// BR - Unconditional branch.  The first operand is the chain
591     /// operand, the second is the MBB to branch to.
592     BR,
593 
594     /// BRIND - Indirect branch.  The first operand is the chain, the second
595     /// is the value to branch to, which must be of the same type as the
596     /// target's pointer type.
597     BRIND,
598 
599     /// BR_JT - Jumptable branch. The first operand is the chain, the second
600     /// is the jumptable index, the last one is the jumptable entry index.
601     BR_JT,
602 
603     /// BRCOND - Conditional branch.  The first operand is the chain, the
604     /// second is the condition, the third is the block to branch to if the
605     /// condition is true.  If the type of the condition is not i1, then the
606     /// high bits must conform to getBooleanContents.
607     BRCOND,
608 
609     /// BR_CC - Conditional branch.  The behavior is like that of SELECT_CC, in
610     /// that the condition is represented as condition code, and two nodes to
611     /// compare, rather than as a combined SetCC node.  The operands in order
612     /// are chain, cc, lhs, rhs, block to branch to if condition is true.
613     BR_CC,
614 
615     /// INLINEASM - Represents an inline asm block.  This node always has two
616     /// return values: a chain and a flag result.  The inputs are as follows:
617     ///   Operand #0  : Input chain.
618     ///   Operand #1  : a ExternalSymbolSDNode with a pointer to the asm string.
619     ///   Operand #2  : a MDNodeSDNode with the !srcloc metadata.
620     ///   Operand #3  : HasSideEffect, IsAlignStack bits.
621     ///   After this, it is followed by a list of operands with this format:
622     ///     ConstantSDNode: Flags that encode whether it is a mem or not, the
623     ///                     of operands that follow, etc.  See InlineAsm.h.
624     ///     ... however many operands ...
625     ///   Operand #last: Optional, an incoming flag.
626     ///
627     /// The variable width operands are required to represent target addressing
628     /// modes as a single "operand", even though they may have multiple
629     /// SDOperands.
630     INLINEASM,
631 
632     /// EH_LABEL - Represents a label in mid basic block used to track
633     /// locations needed for debug and exception handling tables.  These nodes
634     /// take a chain as input and return a chain.
635     EH_LABEL,
636 
637     /// ANNOTATION_LABEL - Represents a mid basic block label used by
638     /// annotations. This should remain within the basic block and be ordered
639     /// with respect to other call instructions, but loads and stores may float
640     /// past it.
641     ANNOTATION_LABEL,
642 
643     /// CATCHPAD - Represents a catchpad instruction.
644     CATCHPAD,
645 
646     /// CATCHRET - Represents a return from a catch block funclet. Used for
647     /// MSVC compatible exception handling. Takes a chain operand and a
648     /// destination basic block operand.
649     CATCHRET,
650 
651     /// CLEANUPRET - Represents a return from a cleanup block funclet.  Used for
652     /// MSVC compatible exception handling. Takes only a chain operand.
653     CLEANUPRET,
654 
655     /// STACKSAVE - STACKSAVE has one operand, an input chain.  It produces a
656     /// value, the same type as the pointer type for the system, and an output
657     /// chain.
658     STACKSAVE,
659 
660     /// STACKRESTORE has two operands, an input chain and a pointer to restore
661     /// to it returns an output chain.
662     STACKRESTORE,
663 
664     /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
665     /// of a call sequence, and carry arbitrary information that target might
666     /// want to know.  The first operand is a chain, the rest are specified by
667     /// the target and not touched by the DAG optimizers.
668     /// Targets that may use stack to pass call arguments define additional
669     /// operands:
670     /// - size of the call frame part that must be set up within the
671     ///   CALLSEQ_START..CALLSEQ_END pair,
672     /// - part of the call frame prepared prior to CALLSEQ_START.
673     /// Both these parameters must be constants, their sum is the total call
674     /// frame size.
675     /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
676     CALLSEQ_START,  // Beginning of a call sequence
677     CALLSEQ_END,    // End of a call sequence
678 
679     /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
680     /// and the alignment. It returns a pair of values: the vaarg value and a
681     /// new chain.
682     VAARG,
683 
684     /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
685     /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
686     /// source.
687     VACOPY,
688 
689     /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
690     /// pointer, and a SRCVALUE.
691     VAEND, VASTART,
692 
693     /// SRCVALUE - This is a node type that holds a Value* that is used to
694     /// make reference to a value in the LLVM IR.
695     SRCVALUE,
696 
697     /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
698     /// reference metadata in the IR.
699     MDNODE_SDNODE,
700 
701     /// PCMARKER - This corresponds to the pcmarker intrinsic.
702     PCMARKER,
703 
704     /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
705     /// It produces a chain and one i64 value. The only operand is a chain.
706     /// If i64 is not legal, the result will be expanded into smaller values.
707     /// Still, it returns an i64, so targets should set legality for i64.
708     /// The result is the content of the architecture-specific cycle
709     /// counter-like register (or other high accuracy low latency clock source).
710     READCYCLECOUNTER,
711 
712     /// HANDLENODE node - Used as a handle for various purposes.
713     HANDLENODE,
714 
715     /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.  It
716     /// takes as input a token chain, the pointer to the trampoline, the pointer
717     /// to the nested function, the pointer to pass for the 'nest' parameter, a
718     /// SRCVALUE for the trampoline and another for the nested function
719     /// (allowing targets to access the original Function*).
720     /// It produces a token chain as output.
721     INIT_TRAMPOLINE,
722 
723     /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
724     /// It takes a pointer to the trampoline and produces a (possibly) new
725     /// pointer to the same trampoline with platform-specific adjustments
726     /// applied.  The pointer it returns points to an executable block of code.
727     ADJUST_TRAMPOLINE,
728 
729     /// TRAP - Trapping instruction
730     TRAP,
731 
732     /// DEBUGTRAP - Trap intended to get the attention of a debugger.
733     DEBUGTRAP,
734 
735     /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
736     /// is the chain.  The other operands are the address to prefetch,
737     /// read / write specifier, locality specifier and instruction / data cache
738     /// specifier.
739     PREFETCH,
740 
741     /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
742     /// This corresponds to the fence instruction. It takes an input chain, and
743     /// two integer constants: an AtomicOrdering and a SynchronizationScope.
744     ATOMIC_FENCE,
745 
746     /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
747     /// This corresponds to "load atomic" instruction.
748     ATOMIC_LOAD,
749 
750     /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
751     /// This corresponds to "store atomic" instruction.
752     ATOMIC_STORE,
753 
754     /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
755     /// For double-word atomic operations:
756     /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
757     ///                                          swapLo, swapHi)
758     /// This corresponds to the cmpxchg instruction.
759     ATOMIC_CMP_SWAP,
760 
761     /// Val, Success, OUTCHAIN
762     ///     = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
763     /// N.b. this is still a strong cmpxchg operation, so
764     /// Success == "Val == cmp".
765     ATOMIC_CMP_SWAP_WITH_SUCCESS,
766 
767     /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
768     /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
769     /// For double-word atomic operations:
770     /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
771     /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
772     /// These correspond to the atomicrmw instruction.
773     ATOMIC_SWAP,
774     ATOMIC_LOAD_ADD,
775     ATOMIC_LOAD_SUB,
776     ATOMIC_LOAD_AND,
777     ATOMIC_LOAD_CLR,
778     ATOMIC_LOAD_OR,
779     ATOMIC_LOAD_XOR,
780     ATOMIC_LOAD_NAND,
781     ATOMIC_LOAD_MIN,
782     ATOMIC_LOAD_MAX,
783     ATOMIC_LOAD_UMIN,
784     ATOMIC_LOAD_UMAX,
785 
786     // Masked load and store - consecutive vector load and store operations
787     // with additional mask operand that prevents memory accesses to the
788     // masked-off lanes.
789     MLOAD, MSTORE,
790 
791     // Masked gather and scatter - load and store operations for a vector of
792     // random addresses with additional mask operand that prevents memory
793     // accesses to the masked-off lanes.
794     MGATHER, MSCATTER,
795 
796     /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
797     /// is the chain and the second operand is the alloca pointer.
798     LIFETIME_START, LIFETIME_END,
799 
800     /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
801     /// beginning and end of GC transition  sequence, and carry arbitrary
802     /// information that target might need for lowering.  The first operand is
803     /// a chain, the rest are specified by the target and not touched by the DAG
804     /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
805     /// nested.
806     GC_TRANSITION_START,
807     GC_TRANSITION_END,
808 
809     /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of
810     /// the most recent dynamic alloca. For most targets that would be 0, but
811     /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time
812     /// known nonzero constant. The only operand here is the chain.
813     GET_DYNAMIC_AREA_OFFSET,
814 
815     /// Generic reduction nodes. These nodes represent horizontal vector
816     /// reduction operations, producing a scalar result.
817     /// The STRICT variants perform reductions in sequential order. The first
818     /// operand is an initial scalar accumulator value, and the second operand
819     /// is the vector to reduce.
820     VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL,
821     /// These reductions are non-strict, and have a single vector operand.
822     VECREDUCE_FADD, VECREDUCE_FMUL,
823     VECREDUCE_ADD, VECREDUCE_MUL,
824     VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR,
825     VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN,
826     /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
827     VECREDUCE_FMAX, VECREDUCE_FMIN,
828 
829     /// BUILTIN_OP_END - This must be the last enum value in this list.
830     /// The target-specific pre-isel opcode values start here.
831     BUILTIN_OP_END
832   };
833 
834   /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
835   /// which do not reference a specific memory location should be less than
836   /// this value. Those that do must not be less than this value, and can
837   /// be used with SelectionDAG::getMemIntrinsicNode.
838   static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+400;
839 
840   //===--------------------------------------------------------------------===//
841   /// MemIndexedMode enum - This enum defines the load / store indexed
842   /// addressing modes.
843   ///
844   /// UNINDEXED    "Normal" load / store. The effective address is already
845   ///              computed and is available in the base pointer. The offset
846   ///              operand is always undefined. In addition to producing a
847   ///              chain, an unindexed load produces one value (result of the
848   ///              load); an unindexed store does not produce a value.
849   ///
850   /// PRE_INC      Similar to the unindexed mode where the effective address is
851   /// PRE_DEC      the value of the base pointer add / subtract the offset.
852   ///              It considers the computation as being folded into the load /
853   ///              store operation (i.e. the load / store does the address
854   ///              computation as well as performing the memory transaction).
855   ///              The base operand is always undefined. In addition to
856   ///              producing a chain, pre-indexed load produces two values
857   ///              (result of the load and the result of the address
858   ///              computation); a pre-indexed store produces one value (result
859   ///              of the address computation).
860   ///
861   /// POST_INC     The effective address is the value of the base pointer. The
862   /// POST_DEC     value of the offset operand is then added to / subtracted
863   ///              from the base after memory transaction. In addition to
864   ///              producing a chain, post-indexed load produces two values
865   ///              (the result of the load and the result of the base +/- offset
866   ///              computation); a post-indexed store produces one value (the
867   ///              the result of the base +/- offset computation).
868   enum MemIndexedMode {
869     UNINDEXED = 0,
870     PRE_INC,
871     PRE_DEC,
872     POST_INC,
873     POST_DEC
874   };
875 
876   static const int LAST_INDEXED_MODE = POST_DEC + 1;
877 
878   //===--------------------------------------------------------------------===//
879   /// LoadExtType enum - This enum defines the three variants of LOADEXT
880   /// (load with extension).
881   ///
882   /// SEXTLOAD loads the integer operand and sign extends it to a larger
883   ///          integer result type.
884   /// ZEXTLOAD loads the integer operand and zero extends it to a larger
885   ///          integer result type.
886   /// EXTLOAD  is used for two things: floating point extending loads and
887   ///          integer extending loads [the top bits are undefined].
888   enum LoadExtType {
889     NON_EXTLOAD = 0,
890     EXTLOAD,
891     SEXTLOAD,
892     ZEXTLOAD
893   };
894 
895   static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
896 
897   NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
898 
899   //===--------------------------------------------------------------------===//
900   /// ISD::CondCode enum - These are ordered carefully to make the bitfields
901   /// below work out, when considering SETFALSE (something that never exists
902   /// dynamically) as 0.  "U" -> Unsigned (for integer operands) or Unordered
903   /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
904   /// to.  If the "N" column is 1, the result of the comparison is undefined if
905   /// the input is a NAN.
906   ///
907   /// All of these (except for the 'always folded ops') should be handled for
908   /// floating point.  For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
909   /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
910   ///
911   /// Note that these are laid out in a specific order to allow bit-twiddling
912   /// to transform conditions.
913   enum CondCode {
914     // Opcode          N U L G E       Intuitive operation
915     SETFALSE,      //    0 0 0 0       Always false (always folded)
916     SETOEQ,        //    0 0 0 1       True if ordered and equal
917     SETOGT,        //    0 0 1 0       True if ordered and greater than
918     SETOGE,        //    0 0 1 1       True if ordered and greater than or equal
919     SETOLT,        //    0 1 0 0       True if ordered and less than
920     SETOLE,        //    0 1 0 1       True if ordered and less than or equal
921     SETONE,        //    0 1 1 0       True if ordered and operands are unequal
922     SETO,          //    0 1 1 1       True if ordered (no nans)
923     SETUO,         //    1 0 0 0       True if unordered: isnan(X) | isnan(Y)
924     SETUEQ,        //    1 0 0 1       True if unordered or equal
925     SETUGT,        //    1 0 1 0       True if unordered or greater than
926     SETUGE,        //    1 0 1 1       True if unordered, greater than, or equal
927     SETULT,        //    1 1 0 0       True if unordered or less than
928     SETULE,        //    1 1 0 1       True if unordered, less than, or equal
929     SETUNE,        //    1 1 1 0       True if unordered or not equal
930     SETTRUE,       //    1 1 1 1       Always true (always folded)
931     // Don't care operations: undefined if the input is a nan.
932     SETFALSE2,     //  1 X 0 0 0       Always false (always folded)
933     SETEQ,         //  1 X 0 0 1       True if equal
934     SETGT,         //  1 X 0 1 0       True if greater than
935     SETGE,         //  1 X 0 1 1       True if greater than or equal
936     SETLT,         //  1 X 1 0 0       True if less than
937     SETLE,         //  1 X 1 0 1       True if less than or equal
938     SETNE,         //  1 X 1 1 0       True if not equal
939     SETTRUE2,      //  1 X 1 1 1       Always true (always folded)
940 
941     SETCC_INVALID       // Marker value.
942   };
943 
944   /// Return true if this is a setcc instruction that performs a signed
945   /// comparison when used with integer operands.
isSignedIntSetCC(CondCode Code)946   inline bool isSignedIntSetCC(CondCode Code) {
947     return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
948   }
949 
950   /// Return true if this is a setcc instruction that performs an unsigned
951   /// comparison when used with integer operands.
isUnsignedIntSetCC(CondCode Code)952   inline bool isUnsignedIntSetCC(CondCode Code) {
953     return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
954   }
955 
956   /// Return true if the specified condition returns true if the two operands to
957   /// the condition are equal. Note that if one of the two operands is a NaN,
958   /// this value is meaningless.
isTrueWhenEqual(CondCode Cond)959   inline bool isTrueWhenEqual(CondCode Cond) {
960     return ((int)Cond & 1) != 0;
961   }
962 
963   /// This function returns 0 if the condition is always false if an operand is
964   /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
965   /// the condition is undefined if the operand is a NaN.
getUnorderedFlavor(CondCode Cond)966   inline unsigned getUnorderedFlavor(CondCode Cond) {
967     return ((int)Cond >> 3) & 3;
968   }
969 
970   /// Return the operation corresponding to !(X op Y), where 'op' is a valid
971   /// SetCC operation.
972   CondCode getSetCCInverse(CondCode Operation, bool isInteger);
973 
974   /// Return the operation corresponding to (Y op X) when given the operation
975   /// for (X op Y).
976   CondCode getSetCCSwappedOperands(CondCode Operation);
977 
978   /// Return the result of a logical OR between different comparisons of
979   /// identical values: ((X op1 Y) | (X op2 Y)). This function returns
980   /// SETCC_INVALID if it is not possible to represent the resultant comparison.
981   CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
982 
983   /// Return the result of a logical AND between different comparisons of
984   /// identical values: ((X op1 Y) & (X op2 Y)). This function returns
985   /// SETCC_INVALID if it is not possible to represent the resultant comparison.
986   CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
987 
988 } // end llvm::ISD namespace
989 
990 } // end llvm namespace
991 
992 #endif
993