| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 343 ARM_AM::ShiftOpc ShiftTy; member
352 ARM_AM::ShiftOpc ShiftTy; member
358 ARM_AM::ShiftOpc ShiftTy; member
1629 ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
1869 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister() local
2715 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; in parsePostIdxReg() local
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1831 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1865 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1897 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
|
| D | LegalizeIntegerTypes.cpp | 2363 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
|
| D | SelectionDAGBuilder.cpp | 2637 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 759 ARM_AM::ShiftOpc ShiftTy; member
769 ARM_AM::ShiftOpc ShiftTy; member
776 ARM_AM::ShiftOpc ShiftTy; member
3138 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
3425 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister() local
4877 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; in parsePostIdxReg() local
8489 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
8514 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 525 ARM_AM::ShiftOpc ShiftTy; member
535 ARM_AM::ShiftOpc ShiftTy; member
542 ARM_AM::ShiftOpc ShiftTy; member
2822 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
3098 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister() local
4666 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; in parsePostIdxReg() local
8183 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
8208 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 1116 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandCTLZ() local
|
| D | TargetLowering.cpp | 2465 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL, in SimplifySetCC() local
2498 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL, in SimplifySetCC() local
2529 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL, in SimplifySetCC() local
|
| D | LegalizeIntegerTypes.cpp | 2549 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
|
| D | SelectionDAGBuilder.cpp | 2817 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2308 EVT ShiftTy = DCI.isBeforeLegalize() ? in SimplifySetCC() local
|
| D | SelectionDAGBuilder.cpp | 2562 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); in visitShift() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2775 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2747 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 797 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 785 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 28563 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 35246 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
|