| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 48 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy() local
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| D | HexagonRDFOpt.cpp | 113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY()
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| D | HexagonFrameLowering.cpp | 1544 unsigned SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1568 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1631 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1718 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1807 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
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| D | HexagonGenInsert.cpp | 467 unsigned SrcR, InsR; member
483 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
680 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm()
877 unsigned SrcR = *I; in findRecordInsertForms() local
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| D | HexagonConstPropagation.cpp | 1932 Register SrcR(MI.getOperand(1)); in evaluate() local
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| D | HexagonBitSimplify.cpp | 2209 unsigned SrcR = B0.RefI.Reg; in genBitSplit() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 36 RegisterRef SrcR = { Src.getReg(), Src.getSubReg() }; in interpretAsCopy() local
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| D | HexagonRDFOpt.cpp | 98 auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in interpretAsCopy()
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| D | HexagonFrameLowering.cpp | 1381 unsigned SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1403 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1466 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1549 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1653 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
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| D | HexagonGenInsert.cpp | 433 unsigned SrcR, InsR; member
447 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
637 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm()
839 unsigned SrcR = *I; in findRecordInsertForms() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 388 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 448 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 1852 Variable *SrcR; in legalizeMovFp() local
1883 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
1973 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
3086 Operand *SrcR; in lowerAssign() local
4935 auto *SrcR = legalizeToReg(Src); in lowerIntrinsicCall() local
4951 auto *SrcR = legalizeToReg(Src); in lowerIntrinsicCall() local
5028 auto *SrcR = legalizeToReg(Src); in lowerIntrinsicCall() local
5068 auto *SrcR = legalizeToReg(Src); in lowerIntrinsicCall() local
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| D | IceTargetLoweringARM32.cpp | 1876 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
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