| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 135 const TargetRegisterClass *SrcRC = in getCopyRegClasses() local
151 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy()
157 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy()
193 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence() local
264 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local
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| D | SILowerI1Copies.cpp | 103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 167 const TargetRegisterClass *SrcRC = in getCopyRegClasses() local
183 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy()
189 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy()
254 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
284 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence() local
597 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local
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| D | SILowerI1Copies.cpp | 103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction() local
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| D | SIRegisterInfo.cpp | 1357 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc()
1512 const TargetRegisterClass *SrcRC, in shouldCoalesce()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 247 const TargetRegisterClass *SrcRC = in selectCopy() local
285 const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg); in selectCopy() local
665 const TargetRegisterClass *SrcRC) { in canTurnIntoCOPY()
709 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt() local
791 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectZext() local
884 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectAnyext() local
1108 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI); in emitExtractSubreg() local
1146 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI); in emitInsertSubreg() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | InstructionSelect.cpp | 171 auto SrcRC = MRI.getRegClass(SrcReg); in runOnMachineFunction() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 104 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass; in processBlock() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 106 const TargetRegisterClass *SrcRC = in processBlock() local
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 292 const TargetRegisterClass *SrcRC, in shareSameRegisterFile()
322 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc()
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| D | DetectDeadLanes.cpp | 161 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 353 const TargetRegisterClass *SrcRC, in shareSameRegisterFile()
383 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc()
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| D | DetectDeadLanes.cpp | 159 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 248 const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 248 const TargetRegisterClass *SrcRC, in shouldCoalesce()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 353 const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank( in selectCopy() local
392 const TargetRegisterClass *SrcRC = in selectCopy() local
1170 const TargetRegisterClass *SrcRC = in select() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 289 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
306 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
1103 const TargetRegisterClass *SrcRC, in isWinToJoinCrossClass()
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.cpp | 73 const TargetRegisterClass *SrcRC, in copyRegToReg()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 382 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 384 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 389 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 784 const TargetRegisterClass *SrcRC, in shouldCoalesce()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 803 const TargetRegisterClass *SrcRC, in shouldCoalesce()
|