/external/llvm/lib/MC/ |
D | MCRegisterInfo.cpp | 32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg() local 43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
D | MCRegisterInfo.cpp | 37 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg() local 48 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex() local
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/external/vixl/examples/aarch32/ |
D | mandelbrot.cc | 128 __ Subs(r1, r1, 1); in GenerateMandelBrot() local 172 __ Subs(r5, r5, 1); in GenerateMandelBrot() local 185 __ Subs(r4, r4, 1); in GenerateMandelBrot() local
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D | pi.cc | 70 __ Subs(r0, r0, 1); in GenerateApproximatePi() local
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/external/eigen/Eigen/src/Core/ |
D | BandMatrix.h | 30 Subs = internal::traits<Derived>::Subs, enumerator
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Support/ |
D | CommandLine.cpp | 1791 SmallVectorImpl<std::pair<const char *, SubCommand *>> &Subs) { in sortSubCommands() 1815 void printSubCommands(StrSubCommandPairVector &Subs, size_t MaxSubLen) { in printSubCommands() 1849 StrSubCommandPairVector Subs; in printHelp() local 2200 auto &Subs = GlobalParser->RegisteredSubCommands; in getRegisteredOptions() local
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/external/llvm/lib/Support/ |
D | CommandLine.cpp | 1710 SmallVectorImpl<std::pair<const char *, SubCommand *>> &Subs) { in sortSubCommands() 1734 void printSubCommands(StrSubCommandPairVector &Subs, size_t MaxSubLen) { in printSubCommands() 1762 StrSubCommandPairVector Subs; in operator =() local 2119 auto &Subs = GlobalParser->RegisteredSubCommands; in getRegisteredOptions() local
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/external/swiftshader/third_party/llvm-subzero/lib/Support/ |
D | CommandLine.cpp | 1735 SmallVectorImpl<std::pair<const char *, SubCommand *>> &Subs) { in sortSubCommands() 1759 void printSubCommands(StrSubCommandPairVector &Subs, size_t MaxSubLen) { in printSubCommands() 1787 StrSubCommandPairVector Subs; in operator =() local 2146 auto &Subs = GlobalParser->RegisteredSubCommands; in getRegisteredOptions() local
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
D | CommandLine.h | 269 SmallPtrSet<SubCommand *, 4> Subs; // The subcommands this option belongs to. variable
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/external/llvm/include/llvm/Support/ |
D | CommandLine.h | 254 SmallPtrSet<SubCommand *, 4> Subs; // The subcommands this option belongs to. variable
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/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/ |
D | CommandLine.h | 260 SmallPtrSet<SubCommand *, 4> Subs; // The subcommands this option belongs to. variable
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
D | DebugInfo.cpp | 931 auto Subs = unwrap(Builder)->getOrCreateArray({unwrap(Subscripts), in LLVMDIBuilderCreateArrayType() local 942 auto Subs = unwrap(Builder)->getOrCreateArray({unwrap(Subscripts), in LLVMDIBuilderCreateVectorType() local
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/external/v8/src/compiler/arm64/ |
D | code-generator-arm64.cc | 1123 __ Subs(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local 1132 __ Subs(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
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/external/v8/src/regexp/arm64/ |
D | regexp-macro-assembler-arm64.cc | 756 __ Subs(x10, sp, x10); in GetCode() local
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/external/v8/src/arm64/ |
D | macro-assembler-arm64-inl.h | 146 void TurboAssembler::Subs(const Register& rd, const Register& rn, in Subs() function
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/external/v8/src/builtins/arm64/ |
D | builtins-arm64.cc | 2053 __ Subs(len, len, start_index); in Generate_CallOrConstructForwardVarargs() local 2581 __ Subs(scratch1, argc_actual, argc_expected); in Generate_ArgumentsAdaptorTrampoline() local
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/external/vixl/src/aarch64/ |
D | macro-assembler-aarch64.cc | 1439 void MacroAssembler::Subs(const Register& rd, in Subs() function in vixl::aarch64::MacroAssembler
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/external/libcxxabi/src/demangle/ |
D | ItaniumDemangle.h | 2154 PODSmallVector<Node *, 32> Subs; member
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Demangle/ |
D | ItaniumDemangle.cpp | 1957 PODSmallVector<Node *, 32> Subs; member
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/external/vixl/test/aarch32/ |
D | test-assembler-aarch32.cc | 3304 __ Subs(r0, r0, 0); in TEST() local
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/external/vixl/src/aarch32/ |
D | macro-assembler-aarch32.h | 4636 void Subs(Condition cond, Register rd, Register rn, const Operand& operand) { in Subs() function 4646 void Subs(Register rd, Register rn, const Operand& operand) { in Subs() function
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/external/vixl/test/aarch64/ |
D | test-assembler-aarch64.cc | 379 __ Subs(x7, x0, 0x18001); in TEST() local 380 __ Subs(w8, w0, 0xffffff1); in TEST() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 5228 SmallVector<SDValue, 4> Subs; in SplitOpsAndApply() local
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