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Searched defs:Subs (Results 1 – 23 of 23) sorted by relevance

/external/llvm/lib/MC/
DMCRegisterInfo.cpp32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg() local
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/
DMCRegisterInfo.cpp37 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg() local
48 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex() local
/external/vixl/examples/aarch32/
Dmandelbrot.cc128 __ Subs(r1, r1, 1); in GenerateMandelBrot() local
172 __ Subs(r5, r5, 1); in GenerateMandelBrot() local
185 __ Subs(r4, r4, 1); in GenerateMandelBrot() local
Dpi.cc70 __ Subs(r0, r0, 1); in GenerateApproximatePi() local
/external/eigen/Eigen/src/Core/
DBandMatrix.h30 Subs = internal::traits<Derived>::Subs, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Support/
DCommandLine.cpp1791 SmallVectorImpl<std::pair<const char *, SubCommand *>> &Subs) { in sortSubCommands()
1815 void printSubCommands(StrSubCommandPairVector &Subs, size_t MaxSubLen) { in printSubCommands()
1849 StrSubCommandPairVector Subs; in printHelp() local
2200 auto &Subs = GlobalParser->RegisteredSubCommands; in getRegisteredOptions() local
/external/llvm/lib/Support/
DCommandLine.cpp1710 SmallVectorImpl<std::pair<const char *, SubCommand *>> &Subs) { in sortSubCommands()
1734 void printSubCommands(StrSubCommandPairVector &Subs, size_t MaxSubLen) { in printSubCommands()
1762 StrSubCommandPairVector Subs; in operator =() local
2119 auto &Subs = GlobalParser->RegisteredSubCommands; in getRegisteredOptions() local
/external/swiftshader/third_party/llvm-subzero/lib/Support/
DCommandLine.cpp1735 SmallVectorImpl<std::pair<const char *, SubCommand *>> &Subs) { in sortSubCommands()
1759 void printSubCommands(StrSubCommandPairVector &Subs, size_t MaxSubLen) { in printSubCommands()
1787 StrSubCommandPairVector Subs; in operator =() local
2146 auto &Subs = GlobalParser->RegisteredSubCommands; in getRegisteredOptions() local
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DCommandLine.h269 SmallPtrSet<SubCommand *, 4> Subs; // The subcommands this option belongs to. variable
/external/llvm/include/llvm/Support/
DCommandLine.h254 SmallPtrSet<SubCommand *, 4> Subs; // The subcommands this option belongs to. variable
/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DCommandLine.h260 SmallPtrSet<SubCommand *, 4> Subs; // The subcommands this option belongs to. variable
/external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/
DDebugInfo.cpp931 auto Subs = unwrap(Builder)->getOrCreateArray({unwrap(Subscripts), in LLVMDIBuilderCreateArrayType() local
942 auto Subs = unwrap(Builder)->getOrCreateArray({unwrap(Subscripts), in LLVMDIBuilderCreateVectorType() local
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc1123 __ Subs(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local
1132 __ Subs(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
/external/v8/src/regexp/arm64/
Dregexp-macro-assembler-arm64.cc756 __ Subs(x10, sp, x10); in GetCode() local
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h146 void TurboAssembler::Subs(const Register& rd, const Register& rn, in Subs() function
/external/v8/src/builtins/arm64/
Dbuiltins-arm64.cc2053 __ Subs(len, len, start_index); in Generate_CallOrConstructForwardVarargs() local
2581 __ Subs(scratch1, argc_actual, argc_expected); in Generate_ArgumentsAdaptorTrampoline() local
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.cc1439 void MacroAssembler::Subs(const Register& rd, in Subs() function in vixl::aarch64::MacroAssembler
/external/libcxxabi/src/demangle/
DItaniumDemangle.h2154 PODSmallVector<Node *, 32> Subs; member
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Demangle/
DItaniumDemangle.cpp1957 PODSmallVector<Node *, 32> Subs; member
/external/vixl/test/aarch32/
Dtest-assembler-aarch32.cc3304 __ Subs(r0, r0, 0); in TEST() local
/external/vixl/src/aarch32/
Dmacro-assembler-aarch32.h4636 void Subs(Condition cond, Register rd, Register rn, const Operand& operand) { in Subs() function
4646 void Subs(Register rd, Register rn, const Operand& operand) { in Subs() function
/external/vixl/test/aarch64/
Dtest-assembler-aarch64.cc379 __ Subs(x7, x0, 0x18001); in TEST() local
380 __ Subs(w8, w0, 0xffffff1); in TEST() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp5228 SmallVector<SDValue, 4> Subs; in SplitOpsAndApply() local