| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 510 const TargetRegisterClass *SuperRC in mergeRead2Pair() local
646 const TargetRegisterClass *SuperRC = in mergeSBufferLoadImmPair() local
698 const TargetRegisterClass *SuperRC = in mergeBufferLoadPair() local
792 const TargetRegisterClass *SuperRC = in mergeBufferStorePair() local
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| D | SIInstrInfo.cpp | 3102 const TargetRegisterClass *SuperRC, in buildExtractSubReg()
3135 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm()
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| D | AMDGPUISelDAGToDAG.cpp | 341 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
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| D | SIISelLowering.cpp | 2967 const TargetRegisterClass *SuperRC, in computeIndirectRegAndOffset()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 335 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
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| D | HexagonCopyToCombine.cpp | 590 const TargetRegisterClass *SuperRC = nullptr; in combine() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 229 const TargetRegisterClass *SuperRC in mergeRead2Pair() local
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| D | SILowerControlFlow.cpp | 604 const TargetRegisterClass *SuperRC = TRI->getPhysRegClass(VecReg); in computeIndirectRegAndOffset() local
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| D | SIInstrInfo.cpp | 1904 const TargetRegisterClass *SuperRC, in buildExtractSubReg()
1937 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm()
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| D | AMDGPUISelDAGToDAG.cpp | 208 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 287 const TargetRegisterClass *SuperRC = UseDstRC; in isForwardableRegClassCopy() local
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| D | AggressiveAntiDepBreaker.cpp | 630 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
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| D | RegAllocGreedy.cpp | 2025 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints()
2065 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
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| D | TargetLoweringBase.cpp | 1047 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
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| D | MachineVerifier.cpp | 1295 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1277 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
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| D | AggressiveAntiDepBreaker.cpp | 611 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
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| D | RegAllocGreedy.cpp | 1560 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints()
1599 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
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| D | MachineVerifier.cpp | 1031 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 404 CodeGenRegisterClass *SuperRC) { in addSuperRegClass()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 620 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
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| D | MachineVerifier.cpp | 770 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 365 CodeGenRegisterClass *SuperRC) { in addSuperRegClass()
|