| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 919 __ Sw(val, adr, 0); in VisitMemoryPokeIntNative() local
938 __ Sw(val_lo, adr, 0); in VisitMemoryPokeLongNative() local
939 __ Sw(val_hi, adr, 4); in VisitMemoryPokeLongNative() local
1190 __ Sw(value, TMP, 0); in GenUnsafePut() local
1200 __ Sw(value_lo, TMP, 0); in GenUnsafePut() local
1201 __ Sw(value_hi, TMP, 4); in GenUnsafePut() local
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| D | intrinsics_mips64.cc | 807 __ Sw(val, adr, 00); in VisitMemoryPokeIntNative() local
1038 __ Sw(AT, TMP, 0); in GenUnsafePut() local
1040 __ Sw(value, TMP, 0); in GenUnsafePut() local
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 584 TEST_F(AssemblerMIPSTest, Sw) { in TEST_F() argument
2345 __ Sw(mips::RA, mips::T0, 0); in TEST_F() local
2561 __ Sw(mips::V0, mips::A0, 0x5678); // Possibly patchable instruction, not absorbed. in TEST_F() local
2576 __ Sw(mips::V0, mips::A0, 0x5680); // Immediate isn't 0x5678, absorbed. in TEST_F() local
2749 __ Sw(mips::V0, mips::A0, 0x5678, &patcher_label2); in TEST_F() local
2760 __ Sw(mips::V0, mips::A0, 0x5678, &patcher_label5); in TEST_F() local
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| D | assembler_mips32r6_test.cc | 1560 __ Sw(mips::V0, mips::A0, 0x5678, &patcher_label2); in TEST_F() local
1571 __ Sw(mips::V0, mips::A0, 0x5678, &patcher_label5); in TEST_F() local
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| D | assembler_mips.cc | 809 void MipsAssembler::Sw(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label) { in Sw() function in art::mips::MipsAssembler
816 void MipsAssembler::Sw(Register rt, Register rs, uint16_t imm16) { in Sw() function in art::mips::MipsAssembler
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 1285 TEST_F(AssemblerMIPS64Test, Sw) { in TEST_F() argument
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| D | assembler_mips64.cc | 664 void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sw() function in art::mips64::Mips64Assembler
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