1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <tegra_def.h> 13 #include <utils_def.h> 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stacks */ 20 #ifdef IMAGE_BL31 21 #define PLATFORM_STACK_SIZE U(0x400) 22 #endif 23 24 #define TEGRA_PRIMARY_CPU U(0x0) 25 26 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 27 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 28 PLATFORM_MAX_CPUS_PER_CLUSTER) 29 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 30 PLATFORM_CLUSTER_COUNT + 1) 31 32 /******************************************************************************* 33 * Platform console related constants 34 ******************************************************************************/ 35 #define TEGRA_CONSOLE_BAUDRATE U(115200) 36 #define TEGRA_BOOT_UART_CLK_IN_HZ U(408000000) 37 38 /******************************************************************************* 39 * Platform memory map related constants 40 ******************************************************************************/ 41 /* Size of trusted dram */ 42 #define TZDRAM_SIZE U(0x00400000) 43 #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 44 45 /******************************************************************************* 46 * BL31 specific defines. 47 ******************************************************************************/ 48 #define BL31_SIZE U(0x40000) 49 #define BL31_BASE TZDRAM_BASE 50 #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 51 #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 52 #define BL32_LIMIT TZDRAM_END 53 54 /******************************************************************************* 55 * Platform specific page table and MMU setup constants 56 ******************************************************************************/ 57 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 58 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 59 60 /******************************************************************************* 61 * Some data must be aligned on the biggest cache line size in the platform. 62 * This is known only to the platform as it might have a combination of 63 * integrated and external caches. 64 ******************************************************************************/ 65 #define CACHE_WRITEBACK_SHIFT 6 66 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 67 68 #endif /* __PLATFORM_DEF_H__ */ 69