| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXMachineFunctionInfo.h | 103 void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) { in addVirtualRegister()
142 unsigned getNumRegistersForClass(const TargetRegisterClass *TRC) const { in getNumRegistersForClass()
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| D | PTXMFInfoExtract.cpp | 58 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in runOnMachineFunction() local
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| D | PTXISelLowering.cpp | 239 TargetRegisterClass* TRC = getRegClassFor(RegVT); in LowerFormalArguments() local
300 TargetRegisterClass* TRC = 0; in LowerReturn() local
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| D | PTXAsmPrinter.cpp | 57 const TargetRegisterClass *TRC = MRI.getRegClass(RegNo); in getRegisterTypeName() local
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| /external/u-boot/board/technologic/ts4600/ |
| D | iomux.c | 119 #define TRC 0xd macro
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 134 const TargetRegisterClass *TRC) { in usesRegClass()
272 const TargetRegisterClass *TRC = in optimizeSDPattern() local
437 const TargetRegisterClass *TRC) { in createExtractSubreg()
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| D | ARMLoadStoreOptimizer.cpp | 2277 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 136 const TargetRegisterClass *TRC) { in usesRegClass()
278 const TargetRegisterClass *TRC = in optimizeSDPattern() local
447 const TargetRegisterClass *TRC) { in createExtractSubreg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyAsmPrinter.cpp | 51 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyAsmPrinter.cpp | 97 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 452 const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0)); in EmitSubregNode() local
579 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 494 const TargetRegisterClass *TRC = in EmitSubregNode() local
628 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 517 const TargetRegisterClass *TRC = in EmitSubregNode() local
666 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 430 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
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| D | RegAllocPBQP.cpp | 576 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 497 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
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| D | RegAllocPBQP.cpp | 605 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86AvoidStoreForwardingBlocks.cpp | 561 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2132 TargetRegisterClass *TRC = 0; in Select() local
2161 TargetRegisterClass *TRC = 0; in Select() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 719 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2531 const TargetRegisterClass *TRC; in Select() local
2566 const TargetRegisterClass *TRC; in Select() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5197 TargetRegisterClass *TRC = in EmitAtomicBinary() local
5307 TargetRegisterClass *TRC = in EmitAtomicBinaryMinMax() local
5417 TargetRegisterClass *TRC = in EmitAtomicBinary64() local
5571 const TargetRegisterClass *TRC = in SetupEntryBlockForSjLj() local
5678 const TargetRegisterClass *TRC = in EmitSjLjDispatchBlock() local
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| D | ARMLoadStoreOptimizer.cpp | 1679 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI); in RescheduleOps() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 1595 const TargetRegisterClass *TRC = in SelectInlineAsmMemoryOperand() local
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| /external/clang/lib/Sema/ |
| D | SemaLookup.cpp | 4777 TypoDiagnosticGenerator TDG, TypoRecoveryCallback TRC, CorrectTypoKind Mode, in CorrectTypoDelayed()
5088 TypoRecoveryCallback TRC) { in createDelayedTypo()
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