1 //==-- SystemZISelLowering.h - SystemZ DAG Lowering Interface ----*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H 16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H 17 18 #include "SystemZ.h" 19 #include "SystemZRegisterInfo.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 namespace llvm { 24 namespace SystemZISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 /// Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 /// CALL - These operations represent an abstract call 32 /// instruction, which includes a bunch of information. 33 CALL, 34 35 /// PCRelativeWrapper - PC relative address 36 PCRelativeWrapper, 37 38 /// CMP, UCMP - Compare instruction 39 CMP, 40 UCMP, 41 42 /// BRCOND - Conditional branch. Operand 0 is chain operand, operand 1 is 43 /// the block to branch if condition is true, operand 2 is condition code 44 /// and operand 3 is the flag operand produced by a CMP instruction. 45 BRCOND, 46 47 /// SELECT - Operands 0 and 1 are selection variables, operand 2 is 48 /// condition code and operand 3 is the flag operand. 49 SELECT 50 }; 51 } 52 53 class SystemZSubtarget; 54 class SystemZTargetMachine; 55 56 class SystemZTargetLowering : public TargetLowering { 57 public: 58 explicit SystemZTargetLowering(SystemZTargetMachine &TM); 59 getShiftAmountTy(EVT LHSTy)60 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i64; } 61 62 /// LowerOperation - Provide custom lowering hooks for some operations. 63 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 64 65 /// getTargetNodeName - This method returns the name of a target specific 66 /// DAG node. 67 virtual const char *getTargetNodeName(unsigned Opcode) const; 68 69 std::pair<unsigned, const TargetRegisterClass*> 70 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; 71 TargetLowering::ConstraintType 72 getConstraintType(const std::string &Constraint) const; 73 74 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 75 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 76 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 77 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 78 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 79 80 SDValue EmitCmp(SDValue LHS, SDValue RHS, 81 ISD::CondCode CC, SDValue &SystemZCC, 82 SelectionDAG &DAG) const; 83 84 85 MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI, 86 MachineBasicBlock *BB) const; 87 88 /// isFPImmLegal - Returns true if the target can instruction select the 89 /// specified FP immediate natively. If false, the legalizer will 90 /// materialize the FP immediate as a load from a constant pool. 91 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 92 93 private: 94 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, 95 CallingConv::ID CallConv, bool isVarArg, 96 bool isTailCall, 97 const SmallVectorImpl<ISD::OutputArg> &Outs, 98 const SmallVectorImpl<SDValue> &OutVals, 99 const SmallVectorImpl<ISD::InputArg> &Ins, 100 DebugLoc dl, SelectionDAG &DAG, 101 SmallVectorImpl<SDValue> &InVals) const; 102 103 SDValue LowerCCCArguments(SDValue Chain, 104 CallingConv::ID CallConv, 105 bool isVarArg, 106 const SmallVectorImpl<ISD::InputArg> &Ins, 107 DebugLoc dl, 108 SelectionDAG &DAG, 109 SmallVectorImpl<SDValue> &InVals) const; 110 111 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 112 CallingConv::ID CallConv, bool isVarArg, 113 const SmallVectorImpl<ISD::InputArg> &Ins, 114 DebugLoc dl, SelectionDAG &DAG, 115 SmallVectorImpl<SDValue> &InVals) const; 116 117 virtual SDValue 118 LowerFormalArguments(SDValue Chain, 119 CallingConv::ID CallConv, bool isVarArg, 120 const SmallVectorImpl<ISD::InputArg> &Ins, 121 DebugLoc dl, SelectionDAG &DAG, 122 SmallVectorImpl<SDValue> &InVals) const; 123 virtual SDValue 124 LowerCall(SDValue Chain, SDValue Callee, 125 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 126 const SmallVectorImpl<ISD::OutputArg> &Outs, 127 const SmallVectorImpl<SDValue> &OutVals, 128 const SmallVectorImpl<ISD::InputArg> &Ins, 129 DebugLoc dl, SelectionDAG &DAG, 130 SmallVectorImpl<SDValue> &InVals) const; 131 132 virtual SDValue 133 LowerReturn(SDValue Chain, 134 CallingConv::ID CallConv, bool isVarArg, 135 const SmallVectorImpl<ISD::OutputArg> &Outs, 136 const SmallVectorImpl<SDValue> &OutVals, 137 DebugLoc dl, SelectionDAG &DAG) const; 138 139 const SystemZSubtarget &Subtarget; 140 const SystemZTargetMachine &TM; 141 const SystemZRegisterInfo *RegInfo; 142 }; 143 } // namespace llvm 144 145 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H 146