1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * PXA25x UDC definitions 4 * 5 * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com> 6 */ 7 8 #ifndef __REGS_USB_H__ 9 #define __REGS_USB_H__ 10 11 struct pxa25x_udc_regs { 12 /* UDC Control Register */ 13 uint32_t udccr; /* 0x000 */ 14 uint32_t reserved1; 15 16 /* UDC Control Function Register */ 17 uint32_t udccfr; /* 0x008 */ 18 uint32_t reserved2; 19 20 /* UDC Endpoint Control/Status Registers */ 21 uint32_t udccs[16]; /* 0x010 - 0x04c */ 22 23 /* UDC Interrupt Control/Status Registers */ 24 uint32_t uicr0; /* 0x050 */ 25 uint32_t uicr1; /* 0x054 */ 26 uint32_t usir0; /* 0x058 */ 27 uint32_t usir1; /* 0x05c */ 28 29 /* UDC Frame Number/Byte Count Registers */ 30 uint32_t ufnrh; /* 0x060 */ 31 uint32_t ufnrl; /* 0x064 */ 32 uint32_t ubcr2; /* 0x068 */ 33 uint32_t ubcr4; /* 0x06c */ 34 uint32_t ubcr7; /* 0x070 */ 35 uint32_t ubcr9; /* 0x074 */ 36 uint32_t ubcr12; /* 0x078 */ 37 uint32_t ubcr14; /* 0x07c */ 38 39 /* UDC Endpoint Data Registers */ 40 uint32_t uddr0; /* 0x080 */ 41 uint32_t reserved3[7]; 42 uint32_t uddr5; /* 0x0a0 */ 43 uint32_t reserved4[7]; 44 uint32_t uddr10; /* 0x0c0 */ 45 uint32_t reserved5[7]; 46 uint32_t uddr15; /* 0x0e0 */ 47 uint32_t reserved6[7]; 48 uint32_t uddr1; /* 0x100 */ 49 uint32_t reserved7[31]; 50 uint32_t uddr2; /* 0x180 */ 51 uint32_t reserved8[31]; 52 uint32_t uddr3; /* 0x200 */ 53 uint32_t reserved9[127]; 54 uint32_t uddr4; /* 0x400 */ 55 uint32_t reserved10[127]; 56 uint32_t uddr6; /* 0x600 */ 57 uint32_t reserved11[31]; 58 uint32_t uddr7; /* 0x680 */ 59 uint32_t reserved12[31]; 60 uint32_t uddr8; /* 0x700 */ 61 uint32_t reserved13[127]; 62 uint32_t uddr9; /* 0x900 */ 63 uint32_t reserved14[127]; 64 uint32_t uddr11; /* 0xb00 */ 65 uint32_t reserved15[31]; 66 uint32_t uddr12; /* 0xb80 */ 67 uint32_t reserved16[31]; 68 uint32_t uddr13; /* 0xc00 */ 69 uint32_t reserved17[127]; 70 uint32_t uddr14; /* 0xe00 */ 71 72 }; 73 74 #define PXA25X_UDC_BASE 0x40600000 75 76 #define UDCCR_UDE (1 << 0) 77 #define UDCCR_UDA (1 << 1) 78 #define UDCCR_RSM (1 << 2) 79 #define UDCCR_RESIR (1 << 3) 80 #define UDCCR_SUSIR (1 << 4) 81 #define UDCCR_SRM (1 << 5) 82 #define UDCCR_RSTIR (1 << 6) 83 #define UDCCR_REM (1 << 7) 84 85 /* Bulk IN endpoint 1/6/11 */ 86 #define UDCCS_BI_TSP (1 << 7) 87 #define UDCCS_BI_FST (1 << 5) 88 #define UDCCS_BI_SST (1 << 4) 89 #define UDCCS_BI_TUR (1 << 3) 90 #define UDCCS_BI_FTF (1 << 2) 91 #define UDCCS_BI_TPC (1 << 1) 92 #define UDCCS_BI_TFS (1 << 0) 93 94 /* Bulk OUT endpoint 2/7/12 */ 95 #define UDCCS_BO_RSP (1 << 7) 96 #define UDCCS_BO_RNE (1 << 6) 97 #define UDCCS_BO_FST (1 << 5) 98 #define UDCCS_BO_SST (1 << 4) 99 #define UDCCS_BO_DME (1 << 3) 100 #define UDCCS_BO_RPC (1 << 1) 101 #define UDCCS_BO_RFS (1 << 0) 102 103 /* Isochronous OUT endpoint 4/9/14 */ 104 #define UDCCS_IO_RSP (1 << 7) 105 #define UDCCS_IO_RNE (1 << 6) 106 #define UDCCS_IO_DME (1 << 3) 107 #define UDCCS_IO_ROF (1 << 2) 108 #define UDCCS_IO_RPC (1 << 1) 109 #define UDCCS_IO_RFS (1 << 0) 110 111 /* Control endpoint 0 */ 112 #define UDCCS0_OPR (1 << 0) 113 #define UDCCS0_IPR (1 << 1) 114 #define UDCCS0_FTF (1 << 2) 115 #define UDCCS0_DRWF (1 << 3) 116 #define UDCCS0_SST (1 << 4) 117 #define UDCCS0_FST (1 << 5) 118 #define UDCCS0_RNE (1 << 6) 119 #define UDCCS0_SA (1 << 7) 120 121 #define UICR0_IM0 (1 << 0) 122 123 #define USIR0_IR0 (1 << 0) 124 #define USIR0_IR1 (1 << 1) 125 #define USIR0_IR2 (1 << 2) 126 #define USIR0_IR3 (1 << 3) 127 #define USIR0_IR4 (1 << 4) 128 #define USIR0_IR5 (1 << 5) 129 #define USIR0_IR6 (1 << 6) 130 #define USIR0_IR7 (1 << 7) 131 132 #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ 133 #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ 134 /* 135 * Intel(R) PXA255 Processor Specification, September 2003 (page 31) 136 * define new "must be one" bits in UDCCFR (see Table 12-13.) 137 */ 138 #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) 139 140 #define UFNRH_SIR (1 << 7) /* SOF interrupt request */ 141 #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ 142 #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ 143 #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ 144 #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ 145 146 #endif /* __REGS_USB_H__ */ 147