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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef __DDR3_AXP_CONFIG_H
7 #define __DDR3_AXP_CONFIG_H
8 
9 /*
10  * DDR3_LOG_LEVEL Information
11  *
12  * Level 0: Provides an error code in a case of failure, RL, WL errors
13  *          and other algorithm failure
14  * Level 1: Provides the D-Unit setup (SPD/Static configuration)
15  * Level 2: Provides the windows margin as a results of DQS centeralization
16  * Level 3: Provides the windows margin of each DQ as a results of DQS
17  *          centeralization
18  */
19 #ifdef CONFIG_DDR_LOG_LEVEL
20 #define	DDR3_LOG_LEVEL	CONFIG_DDR_LOG_LEVEL
21 #else
22 #define	DDR3_LOG_LEVEL	0
23 #endif
24 
25 #define DDR3_PBS        1
26 
27 /* This flag allows the execution of SW WL/RL upon HW failure */
28 #define DDR3_RUN_SW_WHEN_HW_FAIL    1
29 
30 /*
31  * General Configurations
32  *
33  * The following parameters are required for proper setup:
34  *
35  * DDR_TARGET_FABRIC   - Set desired fabric configuration
36  *                       (for sample@Reset fabfreq parameter)
37  * DRAM_ECC            - Set ECC support 1/0
38  * BUS_WIDTH           - 64/32 bit
39  * CONFIG_SPD_EEPROM   - Enables auto detection of DIMMs and their timing values
40  * DQS_CLK_ALIGNED     - Set this if CLK and DQS signals are aligned on board
41  * MIXED_DIMM_STATIC   - Mixed DIMM + On board devices support (ODT registers
42  *                       values are taken statically)
43  * DDR3_TRAINING_DEBUG - Debug prints of internal code
44  */
45 #define DDR_TARGET_FABRIC			5
46 /* Only enable ECC if the board selects it */
47 #ifdef CONFIG_BOARD_ECC_SUPPORT
48 #define DRAM_ECC				1
49 #else
50 #define DRAM_ECC				0
51 #endif
52 
53 #ifdef CONFIG_DDR_32BIT
54 #define BUS_WIDTH                               32
55 #else
56 #define BUS_WIDTH				64
57 #endif
58 
59 #undef DQS_CLK_ALIGNED
60 #undef MIXED_DIMM_STATIC
61 #define DDR3_TRAINING_DEBUG			0
62 #define REG_DIMM_SKIP_WL			0
63 
64 /* Marvell boards specific configurations */
65 #if defined(DB_78X60_PCAC)
66 #undef CONFIG_SPD_EEPROM
67 #define STATIC_TRAINING
68 #endif
69 
70 #if defined(DB_78X60_AMC)
71 #undef CONFIG_SPD_EEPROM
72 #undef  DRAM_ECC
73 #define DRAM_ECC				1
74 #endif
75 
76 #ifdef CONFIG_SPD_EEPROM
77 /*
78  * DIMM support parameters:
79  * DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
80  * DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
81  * (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...)
82  */
83 #define DRAM_2T					0x0
84 #define DIMM_CS_BITMAP				0xF
85 #define DUNIT_SPD
86 #endif
87 
88 #ifdef DRAM_ECC
89 /*
90  * ECC support parameters:
91  *
92  * U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
93  * to configure the scrubbing area
94  */
95 #define TRAINING_SIZE				0x20000
96 #define U_BOOT_START_ADDR			0
97 #define U_BOOT_SCRUB_SIZE			0x1000000 /* TRAINING_SIZE */
98 #endif
99 
100 /*
101  * Registered DIMM Support - In case registered DIMM is attached,
102  * please supply the following values:
103  * (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
104  * Driver with Parity and Quad Chip
105  * Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications")
106  * RC0: Global Features Control Word
107  * RC1: Clock Driver Enable Control Word
108  * RC2: Timing Control Word
109  * RC3-RC5 - taken from SPD
110  * RC8: Additional IBT Setting Control Word
111  * RC9: Power Saving Settings Control Word
112  * RC10: Encoding for RDIMM Operating Speed
113  * RC11: Operating Voltage VDD and VREFCA Control Word
114  */
115 #define RDIMM_RC0				0
116 #define RDIMM_RC1				0
117 #define RDIMM_RC2				0
118 #define RDIMM_RC8				0
119 #define RDIMM_RC9				0
120 #define RDIMM_RC10				0x2
121 #define RDIMM_RC11				0x0
122 
123 #if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM)
124 #define DUNIT_STATIC
125 #endif
126 
127 #if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM)
128 /*
129  * This flag allows the user to change the dram refresh cycle in ps,
130  * only in case of SPD or MIX DIMM topology
131  */
132 #define TREFI_USER_EN
133 
134 #ifdef TREFI_USER_EN
135 #define TREFI_USER				3900000
136 #endif
137 #endif
138 
139 #ifdef CONFIG_SPD_EEPROM
140 /*
141  * AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.
142  * Enables I2C auto detection different options
143  */
144 #if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \
145     defined(CONFIG_DB_784MP_GP)
146 #define AUTO_DETECTION_SUPPORT
147 #endif
148 #endif
149 
150 #endif /* __DDR3_AXP_CONFIG_H */
151