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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for SIRegisterInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
17 
18 #include "AMDGPURegisterInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 
21 namespace llvm {
22 
23 class SISubtarget;
24 class MachineRegisterInfo;
25 
26 struct SIRegisterInfo final : public AMDGPURegisterInfo {
27 private:
28   unsigned SGPR32SetID;
29   unsigned VGPR32SetID;
30   BitVector SGPRPressureSets;
31   BitVector VGPRPressureSets;
32 
33   void reserveRegisterTuples(BitVector &, unsigned Reg) const;
34   void classifyPressureSet(unsigned PSetID, unsigned Reg,
35                            BitVector &PressureSets) const;
36 
37 public:
38   SIRegisterInfo();
39 
40   /// Return the end register initially reserved for the scratch buffer in case
41   /// spilling is needed.
42   unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
43 
44   /// Return the end register initially reserved for the scratch wave offset in
45   /// case spilling is needed.
46   unsigned reservedPrivateSegmentWaveByteOffsetReg(
47     const MachineFunction &MF) const;
48 
49   BitVector getReservedRegs(const MachineFunction &MF) const override;
50 
51   unsigned getRegPressureSetLimit(const MachineFunction &MF,
52                                   unsigned Idx) const override;
53 
54 
55   bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
56 
57 
58   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
59   bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
60   bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
61 
62   int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
63                                    int Idx) const override;
64 
65   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
66 
67   void materializeFrameBaseRegister(MachineBasicBlock *MBB,
68                                     unsigned BaseReg, int FrameIdx,
69                                     int64_t Offset) const override;
70 
71   void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
72                          int64_t Offset) const override;
73 
74   bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
75                           int64_t Offset) const override;
76 
77   const TargetRegisterClass *getPointerRegClass(
78     const MachineFunction &MF, unsigned Kind = 0) const override;
79 
80   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
81                            unsigned FIOperandNum,
82                            RegScavenger *RS) const override;
83 
getHWRegIndexfinal84   unsigned getHWRegIndex(unsigned Reg) const {
85     return getEncodingValue(Reg) & 0xff;
86   }
87 
88   /// \brief Return the 'base' register class for this register.
89   /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
90   const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
91 
92   /// \returns true if this class contains only SGPR registers
isSGPRClassfinal93   bool isSGPRClass(const TargetRegisterClass *RC) const {
94     return !hasVGPRs(RC);
95   }
96 
97   /// \returns true if this class ID contains only SGPR registers
isSGPRClassIDfinal98   bool isSGPRClassID(unsigned RCID) const {
99     return isSGPRClass(getRegClass(RCID));
100   }
101 
isSGPRRegfinal102   bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
103     const TargetRegisterClass *RC;
104     if (TargetRegisterInfo::isVirtualRegister(Reg))
105       RC = MRI.getRegClass(Reg);
106     else
107       RC = getPhysRegClass(Reg);
108     return isSGPRClass(RC);
109   }
110 
111   /// \returns true if this class contains VGPR registers.
112   bool hasVGPRs(const TargetRegisterClass *RC) const;
113 
114   /// returns true if this is a pseudoregister class combination of VGPRs and
115   /// SGPRs for operand modeling. FIXME: We should set isAllocatable = 0 on
116   /// them.
isPseudoRegClassfinal117   static bool isPseudoRegClass(const TargetRegisterClass *RC) {
118     return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass;
119   }
120 
121   /// \returns A VGPR reg class with the same width as \p SRC
122   const TargetRegisterClass *getEquivalentVGPRClass(
123                                           const TargetRegisterClass *SRC) const;
124 
125   /// \returns A SGPR reg class with the same width as \p SRC
126   const TargetRegisterClass *getEquivalentSGPRClass(
127                                            const TargetRegisterClass *VRC) const;
128 
129   /// \returns The register class that is used for a sub-register of \p RC for
130   /// the given \p SubIdx.  If \p SubIdx equals NoSubRegister, \p RC will
131   /// be returned.
132   const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
133                                             unsigned SubIdx) const;
134 
135   bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
136                             unsigned DefSubReg,
137                             const TargetRegisterClass *SrcRC,
138                             unsigned SrcSubReg) const override;
139 
140   /// \p Channel This is the register channel (e.g. a value from 0-16), not the
141   ///            SubReg index.
142   /// \returns The sub-register of Reg that is in Channel.
143   unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
144                             unsigned Channel) const;
145 
146   /// \returns True if operands defined with this operand type can accept
147   /// a literal constant (i.e. any 32-bit immediate).
148   bool opCanUseLiteralConstant(unsigned OpType) const;
149 
150   /// \returns True if operands defined with this operand type can accept
151   /// an inline constant. i.e. An integer value in the range (-16, 64) or
152   /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
153   bool opCanUseInlineConstant(unsigned OpType) const;
154 
155   enum PreloadedValue {
156     // SGPRS:
157     PRIVATE_SEGMENT_BUFFER = 0,
158     DISPATCH_PTR        =  1,
159     QUEUE_PTR           =  2,
160     KERNARG_SEGMENT_PTR =  3,
161     DISPATCH_ID         =  4,
162     FLAT_SCRATCH_INIT   =  5,
163     WORKGROUP_ID_X      = 10,
164     WORKGROUP_ID_Y      = 11,
165     WORKGROUP_ID_Z      = 12,
166     PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
167 
168     // VGPRS:
169     FIRST_VGPR_VALUE    = 15,
170     WORKITEM_ID_X       = FIRST_VGPR_VALUE,
171     WORKITEM_ID_Y       = 16,
172     WORKITEM_ID_Z       = 17
173   };
174 
175   /// \brief Returns the physical register that \p Value is stored in.
176   unsigned getPreloadedValue(const MachineFunction &MF,
177                              enum PreloadedValue Value) const;
178 
179   /// \brief Give the maximum number of VGPRs that can be used by \p WaveCount
180   ///        concurrent waves.
181   unsigned getNumVGPRsAllowed(unsigned WaveCount) const;
182 
183   /// \brief Give the maximum number of SGPRs that can be used by \p WaveCount
184   ///        concurrent waves.
185   unsigned getNumSGPRsAllowed(const SISubtarget &ST, unsigned WaveCount) const;
186 
187   unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
188                               const TargetRegisterClass *RC) const;
189 
getSGPR32PressureSetfinal190   unsigned getSGPR32PressureSet() const { return SGPR32SetID; };
getVGPR32PressureSetfinal191   unsigned getVGPR32PressureSet() const { return VGPR32SetID; };
192 
193   bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
194 
195 private:
196   void buildScratchLoadStore(MachineBasicBlock::iterator MI,
197                              unsigned LoadStoreOp, const MachineOperand *SrcDst,
198                              unsigned ScratchRsrcReg, unsigned ScratchOffset,
199                              int64_t Offset,
200                              RegScavenger *RS) const;
201 };
202 
203 } // End namespace llvm
204 
205 #endif
206