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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2015 Freescale Semiconductor
4  */
5 
6 #ifndef __LDPAA_WRIOP_H
7 #define __LDPAA_WRIOP_H
8 
9  #include <phy.h>
10 
11 enum wriop_port {
12 	WRIOP1_DPMAC1 = 1,
13 	WRIOP1_DPMAC2,
14 	WRIOP1_DPMAC3,
15 	WRIOP1_DPMAC4,
16 	WRIOP1_DPMAC5,
17 	WRIOP1_DPMAC6,
18 	WRIOP1_DPMAC7,
19 	WRIOP1_DPMAC8,
20 	WRIOP1_DPMAC9,
21 	WRIOP1_DPMAC10,
22 	WRIOP1_DPMAC11,
23 	WRIOP1_DPMAC12,
24 	WRIOP1_DPMAC13,
25 	WRIOP1_DPMAC14,
26 	WRIOP1_DPMAC15,
27 	WRIOP1_DPMAC16,
28 	WRIOP1_DPMAC17,
29 	WRIOP1_DPMAC18,
30 	WRIOP1_DPMAC19,
31 	WRIOP1_DPMAC20,
32 	WRIOP1_DPMAC21,
33 	WRIOP1_DPMAC22,
34 	WRIOP1_DPMAC23,
35 	WRIOP1_DPMAC24,
36 	NUM_WRIOP_PORTS,
37 };
38 
39 struct wriop_dpmac_info {
40 	u8 enabled;
41 	u8 id;
42 	u8 board_mux;
43 	int phy_addr;
44 	void *phy_regs;
45 	phy_interface_t enet_if;
46 	struct phy_device *phydev;
47 	struct mii_dev *bus;
48 };
49 
50 extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
51 
52 #define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
53 #define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
54 
55 void wriop_init_dpmac(int, int, int);
56 void wriop_disable_dpmac(int);
57 void wriop_enable_dpmac(int);
58 u8 wriop_is_enabled_dpmac(int dpmac_id);
59 void wriop_set_mdio(int, struct mii_dev *);
60 struct mii_dev *wriop_get_mdio(int);
61 void wriop_set_phy_address(int, int);
62 int wriop_get_phy_address(int);
63 void wriop_set_phy_dev(int, struct phy_device *);
64 struct phy_device *wriop_get_phy_dev(int);
65 phy_interface_t wriop_get_enet_if(int);
66 
67 void wriop_dpmac_disable(int);
68 void wriop_dpmac_enable(int);
69 phy_interface_t wriop_dpmac_enet_if(int, int);
70 void wriop_init_dpmac_qsgmii(int, int);
71 void wriop_init_rgmii(void);
72 void wriop_init_dpmac_enet_if(int , phy_interface_t);
73 #endif	/* __LDPAA_WRIOP_H */
74