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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2002
4  * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
5  */
6 
7 #ifndef __ASM_PROCESSOR_H_
8 #define __ASM_PROCESSOR_H_ 1
9 
10 #define X86_GDT_ENTRY_SIZE		8
11 
12 #define X86_GDT_ENTRY_NULL		0
13 #define X86_GDT_ENTRY_UNUSED		1
14 #define X86_GDT_ENTRY_32BIT_CS		2
15 #define X86_GDT_ENTRY_32BIT_DS		3
16 #define X86_GDT_ENTRY_32BIT_FS		4
17 #define X86_GDT_ENTRY_16BIT_CS		5
18 #define X86_GDT_ENTRY_16BIT_DS		6
19 #define X86_GDT_ENTRY_16BIT_FLAT_CS	7
20 #define X86_GDT_ENTRY_16BIT_FLAT_DS	8
21 #define X86_GDT_NUM_ENTRIES		9
22 
23 #define X86_GDT_SIZE		(X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
24 
25 /* Length of the public header on Intel microcode blobs */
26 #define UCODE_HEADER_LEN	0x30
27 
28 #ifndef __ASSEMBLY__
29 
30 /*
31  * This register is documented in (for example) the Intel Atom Processor E3800
32  * Product Family Datasheet in "PCU - Power Management Controller (PMC)".
33  *
34  * RST_CNT: Reset Control Register (RST_CNT) Offset cf9.
35  *
36  * The naming follows Intel's naming.
37  */
38 #define IO_PORT_RESET		0xcf9
39 
40 enum {
41 	SYS_RST		= 1 << 1,	/* 0 for soft reset, 1 for hard reset */
42 	RST_CPU		= 1 << 2,	/* initiate reset */
43 	FULL_RST	= 1 << 3,	/* full power cycle */
44 };
45 
46 /**
47  * x86_full_reset() - reset everything: perform a full power cycle
48  */
49 void x86_full_reset(void);
50 
cpu_hlt(void)51 static inline __attribute__((always_inline)) void cpu_hlt(void)
52 {
53 	asm("hlt");
54 }
55 
cpu_get_sp(void)56 static inline ulong cpu_get_sp(void)
57 {
58 	ulong result;
59 
60 	asm volatile(
61 		"mov %%esp, %%eax"
62 		: "=a" (result));
63 	return result;
64 }
65 
66 #endif /* __ASSEMBLY__ */
67 
68 #endif
69