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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2016 Rockchip Inc.
4  */
5 
6 #ifndef _ASM_ARCH_LVDS_RK3288_H
7 #define _ASM_ARCH_LVDS_RK3288_H
8 
9 #define RK3288_LVDS_CH0_REG0			0x00
10 #define RK3288_LVDS_CH0_REG0_LVDS_EN		BIT(7)
11 #define RK3288_LVDS_CH0_REG0_TTL_EN		BIT(6)
12 #define RK3288_LVDS_CH0_REG0_LANECK_EN		BIT(5)
13 #define RK3288_LVDS_CH0_REG0_LANE4_EN		BIT(4)
14 #define RK3288_LVDS_CH0_REG0_LANE3_EN		BIT(3)
15 #define RK3288_LVDS_CH0_REG0_LANE2_EN		BIT(2)
16 #define RK3288_LVDS_CH0_REG0_LANE1_EN		BIT(1)
17 #define RK3288_LVDS_CH0_REG0_LANE0_EN		BIT(0)
18 
19 #define RK3288_LVDS_CH0_REG1			0x04
20 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS	BIT(5)
21 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS		BIT(4)
22 #define RK3288_LVDS_CH0_REG1_LANE3_BIAS		BIT(3)
23 #define RK3288_LVDS_CH0_REG1_LANE2_BIAS		BIT(2)
24 #define RK3288_LVDS_CH0_REG1_LANE1_BIAS		BIT(1)
25 #define RK3288_LVDS_CH0_REG1_LANE0_BIAS		BIT(0)
26 
27 #define RK3288_LVDS_CH0_REG2			0x08
28 #define RK3288_LVDS_CH0_REG2_RESERVE_ON		BIT(7)
29 #define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE	BIT(6)
30 #define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE	BIT(5)
31 #define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE	BIT(4)
32 #define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE	BIT(3)
33 #define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE	BIT(2)
34 #define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE	BIT(1)
35 #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8		BIT(0)
36 
37 #define RK3288_LVDS_CH0_REG3			0x0c
38 #define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK	0xff
39 
40 #define RK3288_LVDS_CH0_REG4			0x10
41 #define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE	BIT(5)
42 #define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE	BIT(4)
43 #define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE	BIT(3)
44 #define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE	BIT(2)
45 #define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE	BIT(1)
46 #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE	BIT(0)
47 
48 #define RK3288_LVDS_CH0_REG5			0x14
49 #define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA	BIT(5)
50 #define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA	BIT(4)
51 #define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA	BIT(3)
52 #define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA	BIT(2)
53 #define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA	BIT(1)
54 #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA	BIT(0)
55 
56 #define RK3288_LVDS_CFG_REGC			0x30
57 #define RK3288_LVDS_CFG_REGC_PLL_ENABLE		0x00
58 #define RK3288_LVDS_CFG_REGC_PLL_DISABLE	0xff
59 
60 #define RK3288_LVDS_CH0_REGD			0x34
61 #define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK	0x1f
62 
63 #define RK3288_LVDS_CH0_REG20			0x80
64 #define RK3288_LVDS_CH0_REG20_MSB		0x45
65 #define RK3288_LVDS_CH0_REG20_LSB		0x44
66 
67 #define RK3288_LVDS_CFG_REG21			0x84
68 #define RK3288_LVDS_CFG_REG21_TX_ENABLE		0x92
69 #define RK3288_LVDS_CFG_REG21_TX_DISABLE	0x00
70 
71 /* fbdiv value is split over 2 registers, with bit8 in reg2 */
72 #define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
73 		(_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
74 #define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
75 		(_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
76 #define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
77 		(_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
78 
79 #define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT	BIT(3)
80 
81 #define LVDS_FMT_MASK			(7 << 16)
82 #define LVDS_MSB			(1 << 3)
83 #define LVDS_DUAL			(1 << 4)
84 #define LVDS_FMT_1			(1 << 5)
85 #define LVDS_TTL_EN			(1 << 6)
86 #define LVDS_START_PHASE_RST_1		(1 << 7)
87 #define LVDS_DCLK_INV			(1 << 8)
88 #define LVDS_CH0_EN			(1 << 11)
89 #define LVDS_CH1_EN			(1 << 12)
90 #define LVDS_PWRDN			(1 << 15)
91 
92 #define LVDS_24BIT		(0 << 1)
93 #define LVDS_18BIT		(1 << 1)
94 
95 
96 #endif
97