1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdlib.h>
26 #include <string.h>
27
28 #include "ac_nir_to_llvm.h"
29 #include "ac_shader_util.h"
30 #include "sid.h"
31
32 unsigned
ac_get_spi_shader_z_format(bool writes_z,bool writes_stencil,bool writes_samplemask)33 ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
34 bool writes_samplemask)
35 {
36 if (writes_z) {
37 /* Z needs 32 bits. */
38 if (writes_samplemask)
39 return V_028710_SPI_SHADER_32_ABGR;
40 else if (writes_stencil)
41 return V_028710_SPI_SHADER_32_GR;
42 else
43 return V_028710_SPI_SHADER_32_R;
44 } else if (writes_stencil || writes_samplemask) {
45 /* Both stencil and sample mask need only 16 bits. */
46 return V_028710_SPI_SHADER_UINT16_ABGR;
47 } else {
48 return V_028710_SPI_SHADER_ZERO;
49 }
50 }
51
52 unsigned
ac_get_cb_shader_mask(unsigned spi_shader_col_format)53 ac_get_cb_shader_mask(unsigned spi_shader_col_format)
54 {
55 unsigned i, cb_shader_mask = 0;
56
57 for (i = 0; i < 8; i++) {
58 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
59 case V_028714_SPI_SHADER_ZERO:
60 break;
61 case V_028714_SPI_SHADER_32_R:
62 cb_shader_mask |= 0x1 << (i * 4);
63 break;
64 case V_028714_SPI_SHADER_32_GR:
65 cb_shader_mask |= 0x3 << (i * 4);
66 break;
67 case V_028714_SPI_SHADER_32_AR:
68 cb_shader_mask |= 0x9 << (i * 4);
69 break;
70 case V_028714_SPI_SHADER_FP16_ABGR:
71 case V_028714_SPI_SHADER_UNORM16_ABGR:
72 case V_028714_SPI_SHADER_SNORM16_ABGR:
73 case V_028714_SPI_SHADER_UINT16_ABGR:
74 case V_028714_SPI_SHADER_SINT16_ABGR:
75 case V_028714_SPI_SHADER_32_ABGR:
76 cb_shader_mask |= 0xf << (i * 4);
77 break;
78 default:
79 assert(0);
80 }
81 }
82 return cb_shader_mask;
83 }
84
85 /**
86 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
87 * geometry shader.
88 */
89 uint32_t
ac_vgt_gs_mode(unsigned gs_max_vert_out,enum chip_class chip_class)90 ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class)
91 {
92 unsigned cut_mode;
93
94 if (gs_max_vert_out <= 128) {
95 cut_mode = V_028A40_GS_CUT_128;
96 } else if (gs_max_vert_out <= 256) {
97 cut_mode = V_028A40_GS_CUT_256;
98 } else if (gs_max_vert_out <= 512) {
99 cut_mode = V_028A40_GS_CUT_512;
100 } else {
101 assert(gs_max_vert_out <= 1024);
102 cut_mode = V_028A40_GS_CUT_1024;
103 }
104
105 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
106 S_028A40_CUT_MODE(cut_mode)|
107 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
108 S_028A40_GS_WRITE_OPTIMIZE(1) |
109 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
110 }
111
112 void
ac_export_mrt_z(struct ac_llvm_context * ctx,LLVMValueRef depth,LLVMValueRef stencil,LLVMValueRef samplemask,struct ac_export_args * args)113 ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth,
114 LLVMValueRef stencil, LLVMValueRef samplemask,
115 struct ac_export_args *args)
116 {
117 unsigned mask = 0;
118 unsigned format = ac_get_spi_shader_z_format(depth != NULL,
119 stencil != NULL,
120 samplemask != NULL);
121
122 assert(depth || stencil || samplemask);
123
124 memset(args, 0, sizeof(*args));
125
126 args->valid_mask = 1; /* whether the EXEC mask is valid */
127 args->done = 1; /* DONE bit */
128
129 /* Specify the target we are exporting */
130 args->target = V_008DFC_SQ_EXP_MRTZ;
131
132 args->compr = 0; /* COMP flag */
133 args->out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
134 args->out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
135 args->out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
136 args->out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
137
138 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
139 assert(!depth);
140 args->compr = 1; /* COMPR flag */
141
142 if (stencil) {
143 /* Stencil should be in X[23:16]. */
144 stencil = ac_to_integer(ctx, stencil);
145 stencil = LLVMBuildShl(ctx->builder, stencil,
146 LLVMConstInt(ctx->i32, 16, 0), "");
147 args->out[0] = ac_to_float(ctx, stencil);
148 mask |= 0x3;
149 }
150 if (samplemask) {
151 /* SampleMask should be in Y[15:0]. */
152 args->out[1] = samplemask;
153 mask |= 0xc;
154 }
155 } else {
156 if (depth) {
157 args->out[0] = depth;
158 mask |= 0x1;
159 }
160 if (stencil) {
161 args->out[1] = stencil;
162 mask |= 0x2;
163 }
164 if (samplemask) {
165 args->out[2] = samplemask;
166 mask |= 0x4;
167 }
168 }
169
170 /* SI (except OLAND and HAINAN) has a bug that it only looks
171 * at the X writemask component. */
172 if (ctx->chip_class == SI &&
173 ctx->family != CHIP_OLAND &&
174 ctx->family != CHIP_HAINAN)
175 mask |= 0x1;
176
177 /* Specify which components to enable */
178 args->enabled_channels = mask;
179 }
180