1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9
10 #include <common.h>
11 #include <errno.h>
12 #include <malloc.h>
13 #include <mmc.h>
14 #include <sdhci.h>
15
16 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
17 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
18 #else
19 void *aligned_buffer;
20 #endif
21
sdhci_reset(struct sdhci_host * host,u8 mask)22 static void sdhci_reset(struct sdhci_host *host, u8 mask)
23 {
24 unsigned long timeout;
25
26 /* Wait max 100 ms */
27 timeout = 100;
28 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
29 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
30 if (timeout == 0) {
31 printf("%s: Reset 0x%x never completed.\n",
32 __func__, (int)mask);
33 return;
34 }
35 timeout--;
36 udelay(1000);
37 }
38 }
39
sdhci_cmd_done(struct sdhci_host * host,struct mmc_cmd * cmd)40 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
41 {
42 int i;
43 if (cmd->resp_type & MMC_RSP_136) {
44 /* CRC is stripped so we need to do some shifting. */
45 for (i = 0; i < 4; i++) {
46 cmd->response[i] = sdhci_readl(host,
47 SDHCI_RESPONSE + (3-i)*4) << 8;
48 if (i != 3)
49 cmd->response[i] |= sdhci_readb(host,
50 SDHCI_RESPONSE + (3-i)*4-1);
51 }
52 } else {
53 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
54 }
55 }
56
sdhci_transfer_pio(struct sdhci_host * host,struct mmc_data * data)57 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
58 {
59 int i;
60 char *offs;
61 for (i = 0; i < data->blocksize; i += 4) {
62 offs = data->dest + i;
63 if (data->flags == MMC_DATA_READ)
64 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
65 else
66 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
67 }
68 }
69
sdhci_transfer_data(struct sdhci_host * host,struct mmc_data * data,unsigned int start_addr)70 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
71 unsigned int start_addr)
72 {
73 unsigned int stat, rdy, mask, timeout, block = 0;
74 bool transfer_done = false;
75 #ifdef CONFIG_MMC_SDHCI_SDMA
76 unsigned char ctrl;
77 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
78 ctrl &= ~SDHCI_CTRL_DMA_MASK;
79 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
80 #endif
81
82 timeout = 1000000;
83 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
84 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
85 do {
86 stat = sdhci_readl(host, SDHCI_INT_STATUS);
87 if (stat & SDHCI_INT_ERROR) {
88 pr_debug("%s: Error detected in status(0x%X)!\n",
89 __func__, stat);
90 return -EIO;
91 }
92 if (!transfer_done && (stat & rdy)) {
93 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
94 continue;
95 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
96 sdhci_transfer_pio(host, data);
97 data->dest += data->blocksize;
98 if (++block >= data->blocks) {
99 /* Keep looping until the SDHCI_INT_DATA_END is
100 * cleared, even if we finished sending all the
101 * blocks.
102 */
103 transfer_done = true;
104 continue;
105 }
106 }
107 #ifdef CONFIG_MMC_SDHCI_SDMA
108 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
109 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
110 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
111 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
112 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
113 }
114 #endif
115 if (timeout-- > 0)
116 udelay(10);
117 else {
118 printf("%s: Transfer data timeout\n", __func__);
119 return -ETIMEDOUT;
120 }
121 } while (!(stat & SDHCI_INT_DATA_END));
122 return 0;
123 }
124
125 /*
126 * No command will be sent by driver if card is busy, so driver must wait
127 * for card ready state.
128 * Every time when card is busy after timeout then (last) timeout value will be
129 * increased twice but only if it doesn't exceed global defined maximum.
130 * Each function call will use last timeout value.
131 */
132 #define SDHCI_CMD_MAX_TIMEOUT 3200
133 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
134 #define SDHCI_READ_STATUS_TIMEOUT 1000
135
136 #ifdef CONFIG_DM_MMC
sdhci_send_command(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)137 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
138 struct mmc_data *data)
139 {
140 struct mmc *mmc = mmc_get_mmc_dev(dev);
141
142 #else
143 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
144 struct mmc_data *data)
145 {
146 #endif
147 struct sdhci_host *host = mmc->priv;
148 unsigned int stat = 0;
149 int ret = 0;
150 int trans_bytes = 0, is_aligned = 1;
151 u32 mask, flags, mode;
152 unsigned int time = 0, start_addr = 0;
153 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
154 ulong start = get_timer(0);
155
156 /* Timeout unit - ms */
157 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
158
159 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
160
161 /* We shouldn't wait for data inihibit for stop commands, even
162 though they might use busy signaling */
163 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
164 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
165 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
166 mask &= ~SDHCI_DATA_INHIBIT;
167
168 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
169 if (time >= cmd_timeout) {
170 printf("%s: MMC: %d busy ", __func__, mmc_dev);
171 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
172 cmd_timeout += cmd_timeout;
173 printf("timeout increasing to: %u ms.\n",
174 cmd_timeout);
175 } else {
176 puts("timeout.\n");
177 return -ECOMM;
178 }
179 }
180 time++;
181 udelay(1000);
182 }
183
184 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
185
186 mask = SDHCI_INT_RESPONSE;
187 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
188 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
189 mask = SDHCI_INT_DATA_AVAIL;
190
191 if (!(cmd->resp_type & MMC_RSP_PRESENT))
192 flags = SDHCI_CMD_RESP_NONE;
193 else if (cmd->resp_type & MMC_RSP_136)
194 flags = SDHCI_CMD_RESP_LONG;
195 else if (cmd->resp_type & MMC_RSP_BUSY) {
196 flags = SDHCI_CMD_RESP_SHORT_BUSY;
197 if (data)
198 mask |= SDHCI_INT_DATA_END;
199 } else
200 flags = SDHCI_CMD_RESP_SHORT;
201
202 if (cmd->resp_type & MMC_RSP_CRC)
203 flags |= SDHCI_CMD_CRC;
204 if (cmd->resp_type & MMC_RSP_OPCODE)
205 flags |= SDHCI_CMD_INDEX;
206 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
207 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
208 flags |= SDHCI_CMD_DATA;
209
210 /* Set Transfer mode regarding to data flag */
211 if (data) {
212 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
213 mode = SDHCI_TRNS_BLK_CNT_EN;
214 trans_bytes = data->blocks * data->blocksize;
215 if (data->blocks > 1)
216 mode |= SDHCI_TRNS_MULTI;
217
218 if (data->flags == MMC_DATA_READ)
219 mode |= SDHCI_TRNS_READ;
220
221 #ifdef CONFIG_MMC_SDHCI_SDMA
222 if (data->flags == MMC_DATA_READ)
223 start_addr = (unsigned long)data->dest;
224 else
225 start_addr = (unsigned long)data->src;
226 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
227 (start_addr & 0x7) != 0x0) {
228 is_aligned = 0;
229 start_addr = (unsigned long)aligned_buffer;
230 if (data->flags != MMC_DATA_READ)
231 memcpy(aligned_buffer, data->src, trans_bytes);
232 }
233
234 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
235 /*
236 * Always use this bounce-buffer when
237 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
238 */
239 is_aligned = 0;
240 start_addr = (unsigned long)aligned_buffer;
241 if (data->flags != MMC_DATA_READ)
242 memcpy(aligned_buffer, data->src, trans_bytes);
243 #endif
244
245 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
246 mode |= SDHCI_TRNS_DMA;
247 #endif
248 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
249 data->blocksize),
250 SDHCI_BLOCK_SIZE);
251 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
252 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
253 } else if (cmd->resp_type & MMC_RSP_BUSY) {
254 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
255 }
256
257 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
258 #ifdef CONFIG_MMC_SDHCI_SDMA
259 if (data) {
260 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
261 flush_cache(start_addr, trans_bytes);
262 }
263 #endif
264 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
265 start = get_timer(0);
266 do {
267 stat = sdhci_readl(host, SDHCI_INT_STATUS);
268 if (stat & SDHCI_INT_ERROR)
269 break;
270
271 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
272 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
273 return 0;
274 } else {
275 printf("%s: Timeout for status update!\n",
276 __func__);
277 return -ETIMEDOUT;
278 }
279 }
280 } while ((stat & mask) != mask);
281
282 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
283 sdhci_cmd_done(host, cmd);
284 sdhci_writel(host, mask, SDHCI_INT_STATUS);
285 } else
286 ret = -1;
287
288 if (!ret && data)
289 ret = sdhci_transfer_data(host, data, start_addr);
290
291 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
292 udelay(1000);
293
294 stat = sdhci_readl(host, SDHCI_INT_STATUS);
295 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
296 if (!ret) {
297 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
298 !is_aligned && (data->flags == MMC_DATA_READ))
299 memcpy(data->dest, aligned_buffer, trans_bytes);
300 return 0;
301 }
302
303 sdhci_reset(host, SDHCI_RESET_CMD);
304 sdhci_reset(host, SDHCI_RESET_DATA);
305 if (stat & SDHCI_INT_TIMEOUT)
306 return -ETIMEDOUT;
307 else
308 return -ECOMM;
309 }
310
311 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
312 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
313 {
314 int err;
315 struct mmc *mmc = mmc_get_mmc_dev(dev);
316 struct sdhci_host *host = mmc->priv;
317
318 debug("%s\n", __func__);
319
320 if (host->ops && host->ops->platform_execute_tuning) {
321 err = host->ops->platform_execute_tuning(mmc, opcode);
322 if (err)
323 return err;
324 return 0;
325 }
326 return 0;
327 }
328 #endif
329 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
330 {
331 struct sdhci_host *host = mmc->priv;
332 unsigned int div, clk = 0, timeout;
333
334 /* Wait max 20 ms */
335 timeout = 200;
336 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
337 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
338 if (timeout == 0) {
339 printf("%s: Timeout to wait cmd & data inhibit\n",
340 __func__);
341 return -EBUSY;
342 }
343
344 timeout--;
345 udelay(100);
346 }
347
348 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
349
350 if (clock == 0)
351 return 0;
352
353 if (host->ops && host->ops->set_delay)
354 host->ops->set_delay(host);
355
356 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
357 /*
358 * Check if the Host Controller supports Programmable Clock
359 * Mode.
360 */
361 if (host->clk_mul) {
362 for (div = 1; div <= 1024; div++) {
363 if ((host->max_clk / div) <= clock)
364 break;
365 }
366
367 /*
368 * Set Programmable Clock Mode in the Clock
369 * Control register.
370 */
371 clk = SDHCI_PROG_CLOCK_MODE;
372 div--;
373 } else {
374 /* Version 3.00 divisors must be a multiple of 2. */
375 if (host->max_clk <= clock) {
376 div = 1;
377 } else {
378 for (div = 2;
379 div < SDHCI_MAX_DIV_SPEC_300;
380 div += 2) {
381 if ((host->max_clk / div) <= clock)
382 break;
383 }
384 }
385 div >>= 1;
386 }
387 } else {
388 /* Version 2.00 divisors must be a power of 2. */
389 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
390 if ((host->max_clk / div) <= clock)
391 break;
392 }
393 div >>= 1;
394 }
395
396 if (host->ops && host->ops->set_clock)
397 host->ops->set_clock(host, div);
398
399 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
400 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
401 << SDHCI_DIVIDER_HI_SHIFT;
402 clk |= SDHCI_CLOCK_INT_EN;
403 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
404
405 /* Wait max 20 ms */
406 timeout = 20;
407 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
408 & SDHCI_CLOCK_INT_STABLE)) {
409 if (timeout == 0) {
410 printf("%s: Internal clock never stabilised.\n",
411 __func__);
412 return -EBUSY;
413 }
414 timeout--;
415 udelay(1000);
416 }
417
418 clk |= SDHCI_CLOCK_CARD_EN;
419 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
420 return 0;
421 }
422
423 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
424 {
425 u8 pwr = 0;
426
427 if (power != (unsigned short)-1) {
428 switch (1 << power) {
429 case MMC_VDD_165_195:
430 pwr = SDHCI_POWER_180;
431 break;
432 case MMC_VDD_29_30:
433 case MMC_VDD_30_31:
434 pwr = SDHCI_POWER_300;
435 break;
436 case MMC_VDD_32_33:
437 case MMC_VDD_33_34:
438 pwr = SDHCI_POWER_330;
439 break;
440 }
441 }
442
443 if (pwr == 0) {
444 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
445 return;
446 }
447
448 pwr |= SDHCI_POWER_ON;
449
450 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
451 }
452
453 #ifdef CONFIG_DM_MMC
454 static int sdhci_set_ios(struct udevice *dev)
455 {
456 struct mmc *mmc = mmc_get_mmc_dev(dev);
457 #else
458 static int sdhci_set_ios(struct mmc *mmc)
459 {
460 #endif
461 u32 ctrl;
462 struct sdhci_host *host = mmc->priv;
463
464 if (host->ops && host->ops->set_control_reg)
465 host->ops->set_control_reg(host);
466
467 if (mmc->clock != host->clock)
468 sdhci_set_clock(mmc, mmc->clock);
469
470 if (mmc->clk_disable)
471 sdhci_set_clock(mmc, 0);
472
473 /* Set bus width */
474 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
475 if (mmc->bus_width == 8) {
476 ctrl &= ~SDHCI_CTRL_4BITBUS;
477 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
478 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
479 ctrl |= SDHCI_CTRL_8BITBUS;
480 } else {
481 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
482 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
483 ctrl &= ~SDHCI_CTRL_8BITBUS;
484 if (mmc->bus_width == 4)
485 ctrl |= SDHCI_CTRL_4BITBUS;
486 else
487 ctrl &= ~SDHCI_CTRL_4BITBUS;
488 }
489
490 if (mmc->clock > 26000000)
491 ctrl |= SDHCI_CTRL_HISPD;
492 else
493 ctrl &= ~SDHCI_CTRL_HISPD;
494
495 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
496 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
497 ctrl &= ~SDHCI_CTRL_HISPD;
498
499 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
500
501 /* If available, call the driver specific "post" set_ios() function */
502 if (host->ops && host->ops->set_ios_post)
503 host->ops->set_ios_post(host);
504
505 return 0;
506 }
507
508 static int sdhci_init(struct mmc *mmc)
509 {
510 struct sdhci_host *host = mmc->priv;
511
512 sdhci_reset(host, SDHCI_RESET_ALL);
513
514 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
515 aligned_buffer = memalign(8, 512*1024);
516 if (!aligned_buffer) {
517 printf("%s: Aligned buffer alloc failed!!!\n",
518 __func__);
519 return -ENOMEM;
520 }
521 }
522
523 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
524
525 if (host->ops && host->ops->get_cd)
526 host->ops->get_cd(host);
527
528 /* Enable only interrupts served by the SD controller */
529 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
530 SDHCI_INT_ENABLE);
531 /* Mask all sdhci interrupt sources */
532 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
533
534 return 0;
535 }
536
537 #ifdef CONFIG_DM_MMC
538 int sdhci_probe(struct udevice *dev)
539 {
540 struct mmc *mmc = mmc_get_mmc_dev(dev);
541
542 return sdhci_init(mmc);
543 }
544
545 const struct dm_mmc_ops sdhci_ops = {
546 .send_cmd = sdhci_send_command,
547 .set_ios = sdhci_set_ios,
548 #ifdef MMC_SUPPORTS_TUNING
549 .execute_tuning = sdhci_execute_tuning,
550 #endif
551 };
552 #else
553 static const struct mmc_ops sdhci_ops = {
554 .send_cmd = sdhci_send_command,
555 .set_ios = sdhci_set_ios,
556 .init = sdhci_init,
557 };
558 #endif
559
560 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
561 u32 f_max, u32 f_min)
562 {
563 u32 caps, caps_1 = 0;
564
565 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
566
567 #ifdef CONFIG_MMC_SDHCI_SDMA
568 if (!(caps & SDHCI_CAN_DO_SDMA)) {
569 printf("%s: Your controller doesn't support SDMA!!\n",
570 __func__);
571 return -EINVAL;
572 }
573 #endif
574 if (host->quirks & SDHCI_QUIRK_REG32_RW)
575 host->version =
576 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
577 else
578 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
579
580 cfg->name = host->name;
581 #ifndef CONFIG_DM_MMC
582 cfg->ops = &sdhci_ops;
583 #endif
584
585 /* Check whether the clock multiplier is supported or not */
586 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
587 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
588 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
589 SDHCI_CLOCK_MUL_SHIFT;
590 }
591
592 if (host->max_clk == 0) {
593 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
594 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
595 SDHCI_CLOCK_BASE_SHIFT;
596 else
597 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
598 SDHCI_CLOCK_BASE_SHIFT;
599 host->max_clk *= 1000000;
600 if (host->clk_mul)
601 host->max_clk *= host->clk_mul;
602 }
603 if (host->max_clk == 0) {
604 printf("%s: Hardware doesn't specify base clock frequency\n",
605 __func__);
606 return -EINVAL;
607 }
608 if (f_max && (f_max < host->max_clk))
609 cfg->f_max = f_max;
610 else
611 cfg->f_max = host->max_clk;
612 if (f_min)
613 cfg->f_min = f_min;
614 else {
615 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
616 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
617 else
618 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
619 }
620 cfg->voltages = 0;
621 if (caps & SDHCI_CAN_VDD_330)
622 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
623 if (caps & SDHCI_CAN_VDD_300)
624 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
625 if (caps & SDHCI_CAN_VDD_180)
626 cfg->voltages |= MMC_VDD_165_195;
627
628 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
629 cfg->voltages |= host->voltages;
630
631 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
632
633 /* Since Host Controller Version3.0 */
634 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
635 if (!(caps & SDHCI_CAN_DO_8BIT))
636 cfg->host_caps &= ~MMC_MODE_8BIT;
637 }
638
639 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
640 cfg->host_caps &= ~MMC_MODE_HS;
641 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
642 }
643
644 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
645 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
646
647 if (!(cfg->voltages & MMC_VDD_165_195) ||
648 (host->quirks & SDHCI_QUIRK_NO_1_8_V))
649 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
650 SDHCI_SUPPORT_DDR50);
651
652 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
653 SDHCI_SUPPORT_DDR50))
654 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
655
656 if (caps_1 & SDHCI_SUPPORT_SDR104) {
657 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
658 /*
659 * SD3.0: SDR104 is supported so (for eMMC) the caps2
660 * field can be promoted to support HS200.
661 */
662 cfg->host_caps |= MMC_CAP(MMC_HS_200);
663 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
664 cfg->host_caps |= MMC_CAP(UHS_SDR50);
665 }
666
667 if (caps_1 & SDHCI_SUPPORT_DDR50)
668 cfg->host_caps |= MMC_CAP(UHS_DDR50);
669
670 if (host->host_caps)
671 cfg->host_caps |= host->host_caps;
672
673 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
674
675 return 0;
676 }
677
678 #ifdef CONFIG_BLK
679 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
680 {
681 return mmc_bind(dev, mmc, cfg);
682 }
683 #else
684 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
685 {
686 int ret;
687
688 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
689 if (ret)
690 return ret;
691
692 host->mmc = mmc_create(&host->cfg, host);
693 if (host->mmc == NULL) {
694 printf("%s: mmc create fail!\n", __func__);
695 return -ENOMEM;
696 }
697
698 return 0;
699 }
700 #endif
701