1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 /** 25 * \file amdgpu.h 26 * 27 * Declare public libdrm_amdgpu API 28 * 29 * This file define API exposed by libdrm_amdgpu library. 30 * User wanted to use libdrm_amdgpu functionality must include 31 * this file. 32 * 33 */ 34 #ifndef _AMDGPU_H_ 35 #define _AMDGPU_H_ 36 37 #include <stdint.h> 38 #include <stdbool.h> 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 struct drm_amdgpu_info_hw_ip; 45 46 /*--------------------------------------------------------------------------*/ 47 /* --------------------------- Defines ------------------------------------ */ 48 /*--------------------------------------------------------------------------*/ 49 50 /** 51 * Define max. number of Command Buffers (IB) which could be sent to the single 52 * hardware IP to accommodate CE/DE requirements 53 * 54 * \sa amdgpu_cs_ib_info 55 */ 56 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 57 58 /** 59 * Special timeout value meaning that the timeout is infinite. 60 */ 61 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull 62 63 /** 64 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout 65 * is absolute. 66 */ 67 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) 68 69 /*--------------------------------------------------------------------------*/ 70 /* ----------------------------- Enums ------------------------------------ */ 71 /*--------------------------------------------------------------------------*/ 72 73 /** 74 * Enum describing possible handle types 75 * 76 * \sa amdgpu_bo_import, amdgpu_bo_export 77 * 78 */ 79 enum amdgpu_bo_handle_type { 80 /** GEM flink name (needs DRM authentication, used by DRI2) */ 81 amdgpu_bo_handle_type_gem_flink_name = 0, 82 83 /** KMS handle which is used by all driver ioctls */ 84 amdgpu_bo_handle_type_kms = 1, 85 86 /** DMA-buf fd handle */ 87 amdgpu_bo_handle_type_dma_buf_fd = 2 88 }; 89 90 /** Define known types of GPU VM VA ranges */ 91 enum amdgpu_gpu_va_range 92 { 93 /** Allocate from "normal"/general range */ 94 amdgpu_gpu_va_range_general = 0 95 }; 96 97 enum amdgpu_sw_info { 98 amdgpu_sw_info_address32_hi = 0, 99 }; 100 101 /*--------------------------------------------------------------------------*/ 102 /* -------------------------- Datatypes ----------------------------------- */ 103 /*--------------------------------------------------------------------------*/ 104 105 /** 106 * Define opaque pointer to context associated with fd. 107 * This context will be returned as the result of 108 * "initialize" function and should be pass as the first 109 * parameter to any API call 110 */ 111 typedef struct amdgpu_device *amdgpu_device_handle; 112 113 /** 114 * Define GPU Context type as pointer to opaque structure 115 * Example of GPU Context is the "rendering" context associated 116 * with OpenGL context (glCreateContext) 117 */ 118 typedef struct amdgpu_context *amdgpu_context_handle; 119 120 /** 121 * Define handle for amdgpu resources: buffer, GDS, etc. 122 */ 123 typedef struct amdgpu_bo *amdgpu_bo_handle; 124 125 /** 126 * Define handle for list of BOs 127 */ 128 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; 129 130 /** 131 * Define handle to be used to work with VA allocated ranges 132 */ 133 typedef struct amdgpu_va *amdgpu_va_handle; 134 135 /** 136 * Define handle for semaphore 137 */ 138 typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; 139 140 /*--------------------------------------------------------------------------*/ 141 /* -------------------------- Structures ---------------------------------- */ 142 /*--------------------------------------------------------------------------*/ 143 144 /** 145 * Structure describing memory allocation request 146 * 147 * \sa amdgpu_bo_alloc() 148 * 149 */ 150 struct amdgpu_bo_alloc_request { 151 /** Allocation request. It must be aligned correctly. */ 152 uint64_t alloc_size; 153 154 /** 155 * It may be required to have some specific alignment requirements 156 * for physical back-up storage (e.g. for displayable surface). 157 * If 0 there is no special alignment requirement 158 */ 159 uint64_t phys_alignment; 160 161 /** 162 * UMD should specify where to allocate memory and how it 163 * will be accessed by the CPU. 164 */ 165 uint32_t preferred_heap; 166 167 /** Additional flags passed on allocation */ 168 uint64_t flags; 169 }; 170 171 /** 172 * Special UMD specific information associated with buffer. 173 * 174 * It may be need to pass some buffer charactersitic as part 175 * of buffer sharing. Such information are defined UMD and 176 * opaque for libdrm_amdgpu as well for kernel driver. 177 * 178 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info, 179 * amdgpu_bo_import(), amdgpu_bo_export 180 * 181 */ 182 struct amdgpu_bo_metadata { 183 /** Special flag associated with surface */ 184 uint64_t flags; 185 186 /** 187 * ASIC-specific tiling information (also used by DCE). 188 * The encoding is defined by the AMDGPU_TILING_* definitions. 189 */ 190 uint64_t tiling_info; 191 192 /** Size of metadata associated with the buffer, in bytes. */ 193 uint32_t size_metadata; 194 195 /** UMD specific metadata. Opaque for kernel */ 196 uint32_t umd_metadata[64]; 197 }; 198 199 /** 200 * Structure describing allocated buffer. Client may need 201 * to query such information as part of 'sharing' buffers mechanism 202 * 203 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(), 204 * amdgpu_bo_import(), amdgpu_bo_export() 205 */ 206 struct amdgpu_bo_info { 207 /** Allocated memory size */ 208 uint64_t alloc_size; 209 210 /** 211 * It may be required to have some specific alignment requirements 212 * for physical back-up storage. 213 */ 214 uint64_t phys_alignment; 215 216 /** Heap where to allocate memory. */ 217 uint32_t preferred_heap; 218 219 /** Additional allocation flags. */ 220 uint64_t alloc_flags; 221 222 /** Metadata associated with buffer if any. */ 223 struct amdgpu_bo_metadata metadata; 224 }; 225 226 /** 227 * Structure with information about "imported" buffer 228 * 229 * \sa amdgpu_bo_import() 230 * 231 */ 232 struct amdgpu_bo_import_result { 233 /** Handle of memory/buffer to use */ 234 amdgpu_bo_handle buf_handle; 235 236 /** Buffer size */ 237 uint64_t alloc_size; 238 }; 239 240 /** 241 * 242 * Structure to describe GDS partitioning information. 243 * \note OA and GWS resources are asscoiated with GDS partition 244 * 245 * \sa amdgpu_gpu_resource_query_gds_info 246 * 247 */ 248 struct amdgpu_gds_resource_info { 249 uint32_t gds_gfx_partition_size; 250 uint32_t compute_partition_size; 251 uint32_t gds_total_size; 252 uint32_t gws_per_gfx_partition; 253 uint32_t gws_per_compute_partition; 254 uint32_t oa_per_gfx_partition; 255 uint32_t oa_per_compute_partition; 256 }; 257 258 /** 259 * Structure describing CS fence 260 * 261 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit() 262 * 263 */ 264 struct amdgpu_cs_fence { 265 266 /** In which context IB was sent to execution */ 267 amdgpu_context_handle context; 268 269 /** To which HW IP type the fence belongs */ 270 uint32_t ip_type; 271 272 /** IP instance index if there are several IPs of the same type. */ 273 uint32_t ip_instance; 274 275 /** Ring index of the HW IP */ 276 uint32_t ring; 277 278 /** Specify fence for which we need to check submission status.*/ 279 uint64_t fence; 280 }; 281 282 /** 283 * Structure describing IB 284 * 285 * \sa amdgpu_cs_request, amdgpu_cs_submit() 286 * 287 */ 288 struct amdgpu_cs_ib_info { 289 /** Special flags */ 290 uint64_t flags; 291 292 /** Virtual MC address of the command buffer */ 293 uint64_t ib_mc_address; 294 295 /** 296 * Size of Command Buffer to be submitted. 297 * - The size is in units of dwords (4 bytes). 298 * - Could be 0 299 */ 300 uint32_t size; 301 }; 302 303 /** 304 * Structure describing fence information 305 * 306 * \sa amdgpu_cs_request, amdgpu_cs_query_fence, 307 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status() 308 */ 309 struct amdgpu_cs_fence_info { 310 /** buffer object for the fence */ 311 amdgpu_bo_handle handle; 312 313 /** fence offset in the unit of sizeof(uint64_t) */ 314 uint64_t offset; 315 }; 316 317 /** 318 * Structure describing submission request 319 * 320 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx 321 * 322 * \sa amdgpu_cs_submit() 323 */ 324 struct amdgpu_cs_request { 325 /** Specify flags with additional information */ 326 uint64_t flags; 327 328 /** Specify HW IP block type to which to send the IB. */ 329 unsigned ip_type; 330 331 /** IP instance index if there are several IPs of the same type. */ 332 unsigned ip_instance; 333 334 /** 335 * Specify ring index of the IP. We could have several rings 336 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1. 337 */ 338 uint32_t ring; 339 340 /** 341 * List handle with resources used by this request. 342 */ 343 amdgpu_bo_list_handle resources; 344 345 /** 346 * Number of dependencies this Command submission needs to 347 * wait for before starting execution. 348 */ 349 uint32_t number_of_dependencies; 350 351 /** 352 * Array of dependencies which need to be met before 353 * execution can start. 354 */ 355 struct amdgpu_cs_fence *dependencies; 356 357 /** Number of IBs to submit in the field ibs. */ 358 uint32_t number_of_ibs; 359 360 /** 361 * IBs to submit. Those IBs will be submit together as single entity 362 */ 363 struct amdgpu_cs_ib_info *ibs; 364 365 /** 366 * The returned sequence number for the command submission 367 */ 368 uint64_t seq_no; 369 370 /** 371 * The fence information 372 */ 373 struct amdgpu_cs_fence_info fence_info; 374 }; 375 376 /** 377 * Structure which provide information about GPU VM MC Address space 378 * alignments requirements 379 * 380 * \sa amdgpu_query_buffer_size_alignment 381 */ 382 struct amdgpu_buffer_size_alignments { 383 /** Size alignment requirement for allocation in 384 * local memory */ 385 uint64_t size_local; 386 387 /** 388 * Size alignment requirement for allocation in remote memory 389 */ 390 uint64_t size_remote; 391 }; 392 393 /** 394 * Structure which provide information about heap 395 * 396 * \sa amdgpu_query_heap_info() 397 * 398 */ 399 struct amdgpu_heap_info { 400 /** Theoretical max. available memory in the given heap */ 401 uint64_t heap_size; 402 403 /** 404 * Number of bytes allocated in the heap. This includes all processes 405 * and private allocations in the kernel. It changes when new buffers 406 * are allocated, freed, and moved. It cannot be larger than 407 * heap_size. 408 */ 409 uint64_t heap_usage; 410 411 /** 412 * Theoretical possible max. size of buffer which 413 * could be allocated in the given heap 414 */ 415 uint64_t max_allocation; 416 }; 417 418 /** 419 * Describe GPU h/w info needed for UMD correct initialization 420 * 421 * \sa amdgpu_query_gpu_info() 422 */ 423 struct amdgpu_gpu_info { 424 /** Asic id */ 425 uint32_t asic_id; 426 /** Chip revision */ 427 uint32_t chip_rev; 428 /** Chip external revision */ 429 uint32_t chip_external_rev; 430 /** Family ID */ 431 uint32_t family_id; 432 /** Special flags */ 433 uint64_t ids_flags; 434 /** max engine clock*/ 435 uint64_t max_engine_clk; 436 /** max memory clock */ 437 uint64_t max_memory_clk; 438 /** number of shader engines */ 439 uint32_t num_shader_engines; 440 /** number of shader arrays per engine */ 441 uint32_t num_shader_arrays_per_engine; 442 /** Number of available good shader pipes */ 443 uint32_t avail_quad_shader_pipes; 444 /** Max. number of shader pipes.(including good and bad pipes */ 445 uint32_t max_quad_shader_pipes; 446 /** Number of parameter cache entries per shader quad pipe */ 447 uint32_t cache_entries_per_quad_pipe; 448 /** Number of available graphics context */ 449 uint32_t num_hw_gfx_contexts; 450 /** Number of render backend pipes */ 451 uint32_t rb_pipes; 452 /** Enabled render backend pipe mask */ 453 uint32_t enabled_rb_pipes_mask; 454 /** Frequency of GPU Counter */ 455 uint32_t gpu_counter_freq; 456 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */ 457 uint32_t backend_disable[4]; 458 /** Value of MC_ARB_RAMCFG register*/ 459 uint32_t mc_arb_ramcfg; 460 /** Value of GB_ADDR_CONFIG */ 461 uint32_t gb_addr_cfg; 462 /** Values of the GB_TILE_MODE0..31 registers */ 463 uint32_t gb_tile_mode[32]; 464 /** Values of GB_MACROTILE_MODE0..15 registers */ 465 uint32_t gb_macro_tile_mode[16]; 466 /** Value of PA_SC_RASTER_CONFIG register per SE */ 467 uint32_t pa_sc_raster_cfg[4]; 468 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */ 469 uint32_t pa_sc_raster_cfg1[4]; 470 /* CU info */ 471 uint32_t cu_active_number; 472 uint32_t cu_ao_mask; 473 uint32_t cu_bitmap[4][4]; 474 /* video memory type info*/ 475 uint32_t vram_type; 476 /* video memory bit width*/ 477 uint32_t vram_bit_width; 478 /** constant engine ram size*/ 479 uint32_t ce_ram_size; 480 /* vce harvesting instance */ 481 uint32_t vce_harvest_config; 482 /* PCI revision ID */ 483 uint32_t pci_rev_id; 484 }; 485 486 487 /*--------------------------------------------------------------------------*/ 488 /*------------------------- Functions --------------------------------------*/ 489 /*--------------------------------------------------------------------------*/ 490 491 /* 492 * Initialization / Cleanup 493 * 494 */ 495 496 /** 497 * 498 * \param fd - \c [in] File descriptor for AMD GPU device 499 * received previously as the result of 500 * e.g. drmOpen() call. 501 * For legacy fd type, the DRI2/DRI3 502 * authentication should be done before 503 * calling this function. 504 * \param major_version - \c [out] Major version of library. It is assumed 505 * that adding new functionality will cause 506 * increase in major version 507 * \param minor_version - \c [out] Minor version of library 508 * \param device_handle - \c [out] Pointer to opaque context which should 509 * be passed as the first parameter on each 510 * API call 511 * 512 * 513 * \return 0 on success\n 514 * <0 - Negative POSIX Error code 515 * 516 * 517 * \sa amdgpu_device_deinitialize() 518 */ 519 int amdgpu_device_initialize(int fd, 520 uint32_t *major_version, 521 uint32_t *minor_version, 522 amdgpu_device_handle *device_handle); 523 524 /** 525 * 526 * When access to such library does not needed any more the special 527 * function must be call giving opportunity to clean up any 528 * resources if needed. 529 * 530 * \param device_handle - \c [in] Context associated with file 531 * descriptor for AMD GPU device 532 * received previously as the 533 * result e.g. of drmOpen() call. 534 * 535 * \return 0 on success\n 536 * <0 - Negative POSIX Error code 537 * 538 * \sa amdgpu_device_initialize() 539 * 540 */ 541 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); 542 543 /* 544 * Memory Management 545 * 546 */ 547 548 /** 549 * Allocate memory to be used by UMD for GPU related operations 550 * 551 * \param dev - \c [in] Device handle. 552 * See #amdgpu_device_initialize() 553 * \param alloc_buffer - \c [in] Pointer to the structure describing an 554 * allocation request 555 * \param buf_handle - \c [out] Allocated buffer handle 556 * 557 * \return 0 on success\n 558 * <0 - Negative POSIX Error code 559 * 560 * \sa amdgpu_bo_free() 561 */ 562 int amdgpu_bo_alloc(amdgpu_device_handle dev, 563 struct amdgpu_bo_alloc_request *alloc_buffer, 564 amdgpu_bo_handle *buf_handle); 565 566 /** 567 * Associate opaque data with buffer to be queried by another UMD 568 * 569 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 570 * \param buf_handle - \c [in] Buffer handle 571 * \param info - \c [in] Metadata to associated with buffer 572 * 573 * \return 0 on success\n 574 * <0 - Negative POSIX Error code 575 */ 576 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle, 577 struct amdgpu_bo_metadata *info); 578 579 /** 580 * Query buffer information including metadata previusly associated with 581 * buffer. 582 * 583 * \param dev - \c [in] Device handle. 584 * See #amdgpu_device_initialize() 585 * \param buf_handle - \c [in] Buffer handle 586 * \param info - \c [out] Structure describing buffer 587 * 588 * \return 0 on success\n 589 * <0 - Negative POSIX Error code 590 * 591 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 592 */ 593 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle, 594 struct amdgpu_bo_info *info); 595 596 /** 597 * Allow others to get access to buffer 598 * 599 * \param dev - \c [in] Device handle. 600 * See #amdgpu_device_initialize() 601 * \param buf_handle - \c [in] Buffer handle 602 * \param type - \c [in] Type of handle requested 603 * \param shared_handle - \c [out] Special "shared" handle 604 * 605 * \return 0 on success\n 606 * <0 - Negative POSIX Error code 607 * 608 * \sa amdgpu_bo_import() 609 * 610 */ 611 int amdgpu_bo_export(amdgpu_bo_handle buf_handle, 612 enum amdgpu_bo_handle_type type, 613 uint32_t *shared_handle); 614 615 /** 616 * Request access to "shared" buffer 617 * 618 * \param dev - \c [in] Device handle. 619 * See #amdgpu_device_initialize() 620 * \param type - \c [in] Type of handle requested 621 * \param shared_handle - \c [in] Shared handle received as result "import" 622 * operation 623 * \param output - \c [out] Pointer to structure with information 624 * about imported buffer 625 * 626 * \return 0 on success\n 627 * <0 - Negative POSIX Error code 628 * 629 * \note Buffer must be "imported" only using new "fd" (different from 630 * one used by "exporter"). 631 * 632 * \sa amdgpu_bo_export() 633 * 634 */ 635 int amdgpu_bo_import(amdgpu_device_handle dev, 636 enum amdgpu_bo_handle_type type, 637 uint32_t shared_handle, 638 struct amdgpu_bo_import_result *output); 639 640 /** 641 * Request GPU access to user allocated memory e.g. via "malloc" 642 * 643 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 644 * \param cpu - [in] CPU address of user allocated memory which we 645 * want to map to GPU address space (make GPU accessible) 646 * (This address must be correctly aligned). 647 * \param size - [in] Size of allocation (must be correctly aligned) 648 * \param buf_handle - [out] Buffer handle for the userptr memory 649 * resource on submission and be used in other operations. 650 * 651 * 652 * \return 0 on success\n 653 * <0 - Negative POSIX Error code 654 * 655 * \note 656 * This call doesn't guarantee that such memory will be persistently 657 * "locked" / make non-pageable. The purpose of this call is to provide 658 * opportunity for GPU get access to this resource during submission. 659 * 660 * The maximum amount of memory which could be mapped in this call depends 661 * if overcommit is disabled or not. If overcommit is disabled than the max. 662 * amount of memory to be pinned will be limited by left "free" size in total 663 * amount of memory which could be locked simultaneously ("GART" size). 664 * 665 * Supported (theoretical) max. size of mapping is restricted only by 666 * "GART" size. 667 * 668 * It is responsibility of caller to correctly specify access rights 669 * on VA assignment. 670 */ 671 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, 672 void *cpu, uint64_t size, 673 amdgpu_bo_handle *buf_handle); 674 675 /** 676 * Free previosuly allocated memory 677 * 678 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 679 * \param buf_handle - \c [in] Buffer handle to free 680 * 681 * \return 0 on success\n 682 * <0 - Negative POSIX Error code 683 * 684 * \note In the case of memory shared between different applications all 685 * resources will be “physically” freed only all such applications 686 * will be terminated 687 * \note If is UMD responsibility to ‘free’ buffer only when there is no 688 * more GPU access 689 * 690 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 691 * 692 */ 693 int amdgpu_bo_free(amdgpu_bo_handle buf_handle); 694 695 /** 696 * Request CPU access to GPU accessible memory 697 * 698 * \param buf_handle - \c [in] Buffer handle 699 * \param cpu - \c [out] CPU address to be used for access 700 * 701 * \return 0 on success\n 702 * <0 - Negative POSIX Error code 703 * 704 * \sa amdgpu_bo_cpu_unmap() 705 * 706 */ 707 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu); 708 709 /** 710 * Release CPU access to GPU memory 711 * 712 * \param buf_handle - \c [in] Buffer handle 713 * 714 * \return 0 on success\n 715 * <0 - Negative POSIX Error code 716 * 717 * \sa amdgpu_bo_cpu_map() 718 * 719 */ 720 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); 721 722 /** 723 * Wait until a buffer is not used by the device. 724 * 725 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 726 * \param buf_handle - \c [in] Buffer handle. 727 * \param timeout_ns - Timeout in nanoseconds. 728 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed 729 * and no GPU access is scheduled. 730 * 1 GPU access is in fly or scheduled 731 * 732 * \return 0 - on success 733 * <0 - Negative POSIX Error code 734 */ 735 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, 736 uint64_t timeout_ns, 737 bool *buffer_busy); 738 739 /** 740 * Creates a BO list handle for command submission. 741 * 742 * \param dev - \c [in] Device handle. 743 * See #amdgpu_device_initialize() 744 * \param number_of_resources - \c [in] Number of BOs in the list 745 * \param resources - \c [in] List of BO handles 746 * \param resource_prios - \c [in] Optional priority for each handle 747 * \param result - \c [out] Created BO list handle 748 * 749 * \return 0 on success\n 750 * <0 - Negative POSIX Error code 751 * 752 * \sa amdgpu_bo_list_destroy() 753 */ 754 int amdgpu_bo_list_create(amdgpu_device_handle dev, 755 uint32_t number_of_resources, 756 amdgpu_bo_handle *resources, 757 uint8_t *resource_prios, 758 amdgpu_bo_list_handle *result); 759 760 /** 761 * Destroys a BO list handle. 762 * 763 * \param handle - \c [in] BO list handle. 764 * 765 * \return 0 on success\n 766 * <0 - Negative POSIX Error code 767 * 768 * \sa amdgpu_bo_list_create() 769 */ 770 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle); 771 772 /** 773 * Update resources for existing BO list 774 * 775 * \param handle - \c [in] BO list handle 776 * \param number_of_resources - \c [in] Number of BOs in the list 777 * \param resources - \c [in] List of BO handles 778 * \param resource_prios - \c [in] Optional priority for each handle 779 * 780 * \return 0 on success\n 781 * <0 - Negative POSIX Error code 782 * 783 * \sa amdgpu_bo_list_update() 784 */ 785 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, 786 uint32_t number_of_resources, 787 amdgpu_bo_handle *resources, 788 uint8_t *resource_prios); 789 790 /* 791 * GPU Execution context 792 * 793 */ 794 795 /** 796 * Create GPU execution Context 797 * 798 * For the purpose of GPU Scheduler and GPU Robustness extensions it is 799 * necessary to have information/identify rendering/compute contexts. 800 * It also may be needed to associate some specific requirements with such 801 * contexts. Kernel driver will guarantee that submission from the same 802 * context will always be executed in order (first come, first serve). 803 * 804 * 805 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 806 * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_* 807 * \param context - \c [out] GPU Context handle 808 * 809 * \return 0 on success\n 810 * <0 - Negative POSIX Error code 811 * 812 * \sa amdgpu_cs_ctx_free() 813 * 814 */ 815 int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, 816 uint32_t priority, 817 amdgpu_context_handle *context); 818 /** 819 * Create GPU execution Context 820 * 821 * Refer to amdgpu_cs_ctx_create2 for full documentation. This call 822 * is missing the priority parameter. 823 * 824 * \sa amdgpu_cs_ctx_create2() 825 * 826 */ 827 int amdgpu_cs_ctx_create(amdgpu_device_handle dev, 828 amdgpu_context_handle *context); 829 830 /** 831 * 832 * Destroy GPU execution context when not needed any more 833 * 834 * \param context - \c [in] GPU Context handle 835 * 836 * \return 0 on success\n 837 * <0 - Negative POSIX Error code 838 * 839 * \sa amdgpu_cs_ctx_create() 840 * 841 */ 842 int amdgpu_cs_ctx_free(amdgpu_context_handle context); 843 844 /** 845 * Query reset state for the specific GPU Context 846 * 847 * \param context - \c [in] GPU Context handle 848 * \param state - \c [out] One of AMDGPU_CTX_*_RESET 849 * \param hangs - \c [out] Number of hangs caused by the context. 850 * 851 * \return 0 on success\n 852 * <0 - Negative POSIX Error code 853 * 854 * \sa amdgpu_cs_ctx_create() 855 * 856 */ 857 int amdgpu_cs_query_reset_state(amdgpu_context_handle context, 858 uint32_t *state, uint32_t *hangs); 859 860 /* 861 * Command Buffers Management 862 * 863 */ 864 865 /** 866 * Send request to submit command buffers to hardware. 867 * 868 * Kernel driver could use GPU Scheduler to make decision when physically 869 * sent this request to the hardware. Accordingly this request could be put 870 * in queue and sent for execution later. The only guarantee is that request 871 * from the same GPU context to the same ip:ip_instance:ring will be executed in 872 * order. 873 * 874 * The caller can specify the user fence buffer/location with the fence_info in the 875 * cs_request.The sequence number is returned via the 'seq_no' parameter 876 * in ibs_request structure. 877 * 878 * 879 * \param dev - \c [in] Device handle. 880 * See #amdgpu_device_initialize() 881 * \param context - \c [in] GPU Context 882 * \param flags - \c [in] Global submission flags 883 * \param ibs_request - \c [in/out] Pointer to submission requests. 884 * We could submit to the several 885 * engines/rings simulteniously as 886 * 'atomic' operation 887 * \param number_of_requests - \c [in] Number of submission requests 888 * 889 * \return 0 on success\n 890 * <0 - Negative POSIX Error code 891 * 892 * \note It is required to pass correct resource list with buffer handles 893 * which will be accessible by command buffers from submission 894 * This will allow kernel driver to correctly implement "paging". 895 * Failure to do so will have unpredictable results. 896 * 897 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(), 898 * amdgpu_cs_query_fence_status() 899 * 900 */ 901 int amdgpu_cs_submit(amdgpu_context_handle context, 902 uint64_t flags, 903 struct amdgpu_cs_request *ibs_request, 904 uint32_t number_of_requests); 905 906 /** 907 * Query status of Command Buffer Submission 908 * 909 * \param fence - \c [in] Structure describing fence to query 910 * \param timeout_ns - \c [in] Timeout value to wait 911 * \param flags - \c [in] Flags for the query 912 * \param expired - \c [out] If fence expired or not.\n 913 * 0 – if fence is not expired\n 914 * !0 - otherwise 915 * 916 * \return 0 on success\n 917 * <0 - Negative POSIX Error code 918 * 919 * \note If UMD wants only to check operation status and returned immediately 920 * then timeout value as 0 must be passed. In this case success will be 921 * returned in the case if submission was completed or timeout error 922 * code. 923 * 924 * \sa amdgpu_cs_submit() 925 */ 926 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, 927 uint64_t timeout_ns, 928 uint64_t flags, 929 uint32_t *expired); 930 931 /** 932 * Wait for multiple fences 933 * 934 * \param fences - \c [in] The fence array to wait 935 * \param fence_count - \c [in] The fence count 936 * \param wait_all - \c [in] If true, wait all fences to be signaled, 937 * otherwise, wait at least one fence 938 * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds 939 * \param status - \c [out] '1' for signaled, '0' for timeout 940 * \param first - \c [out] the index of the first signaled fence from @fences 941 * 942 * \return 0 on success 943 * <0 - Negative POSIX Error code 944 * 945 * \note Currently it supports only one amdgpu_device. All fences come from 946 * the same amdgpu_device with the same fd. 947 */ 948 int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 949 uint32_t fence_count, 950 bool wait_all, 951 uint64_t timeout_ns, 952 uint32_t *status, uint32_t *first); 953 954 /* 955 * Query / Info API 956 * 957 */ 958 959 /** 960 * Query allocation size alignments 961 * 962 * UMD should query information about GPU VM MC size alignments requirements 963 * to be able correctly choose required allocation size and implement 964 * internal optimization if needed. 965 * 966 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 967 * \param info - \c [out] Pointer to structure to get size alignment 968 * requirements 969 * 970 * \return 0 on success\n 971 * <0 - Negative POSIX Error code 972 * 973 */ 974 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, 975 struct amdgpu_buffer_size_alignments 976 *info); 977 978 /** 979 * Query firmware versions 980 * 981 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 982 * \param fw_type - \c [in] AMDGPU_INFO_FW_* 983 * \param ip_instance - \c [in] Index of the IP block of the same type. 984 * \param index - \c [in] Index of the engine. (for SDMA and MEC) 985 * \param version - \c [out] Pointer to to the "version" return value 986 * \param feature - \c [out] Pointer to to the "feature" return value 987 * 988 * \return 0 on success\n 989 * <0 - Negative POSIX Error code 990 * 991 */ 992 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type, 993 unsigned ip_instance, unsigned index, 994 uint32_t *version, uint32_t *feature); 995 996 /** 997 * Query the number of HW IP instances of a certain type. 998 * 999 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1000 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1001 * \param count - \c [out] Pointer to structure to get information 1002 * 1003 * \return 0 on success\n 1004 * <0 - Negative POSIX Error code 1005 */ 1006 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, 1007 uint32_t *count); 1008 1009 /** 1010 * Query engine information 1011 * 1012 * This query allows UMD to query information different engines and their 1013 * capabilities. 1014 * 1015 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1016 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1017 * \param ip_instance - \c [in] Index of the IP block of the same type. 1018 * \param info - \c [out] Pointer to structure to get information 1019 * 1020 * \return 0 on success\n 1021 * <0 - Negative POSIX Error code 1022 */ 1023 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, 1024 unsigned ip_instance, 1025 struct drm_amdgpu_info_hw_ip *info); 1026 1027 /** 1028 * Query heap information 1029 * 1030 * This query allows UMD to query potentially available memory resources and 1031 * adjust their logic if necessary. 1032 * 1033 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1034 * \param heap - \c [in] Heap type 1035 * \param info - \c [in] Pointer to structure to get needed information 1036 * 1037 * \return 0 on success\n 1038 * <0 - Negative POSIX Error code 1039 * 1040 */ 1041 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, 1042 uint32_t flags, struct amdgpu_heap_info *info); 1043 1044 /** 1045 * Get the CRTC ID from the mode object ID 1046 * 1047 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1048 * \param id - \c [in] Mode object ID 1049 * \param result - \c [in] Pointer to the CRTC ID 1050 * 1051 * \return 0 on success\n 1052 * <0 - Negative POSIX Error code 1053 * 1054 */ 1055 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, 1056 int32_t *result); 1057 1058 /** 1059 * Query GPU H/w Info 1060 * 1061 * Query hardware specific information 1062 * 1063 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1064 * \param heap - \c [in] Heap type 1065 * \param info - \c [in] Pointer to structure to get needed information 1066 * 1067 * \return 0 on success\n 1068 * <0 - Negative POSIX Error code 1069 * 1070 */ 1071 int amdgpu_query_gpu_info(amdgpu_device_handle dev, 1072 struct amdgpu_gpu_info *info); 1073 1074 /** 1075 * Query hardware or driver information. 1076 * 1077 * The return size is query-specific and depends on the "info_id" parameter. 1078 * No more than "size" bytes is returned. 1079 * 1080 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1081 * \param info_id - \c [in] AMDGPU_INFO_* 1082 * \param size - \c [in] Size of the returned value. 1083 * \param value - \c [out] Pointer to the return value. 1084 * 1085 * \return 0 on success\n 1086 * <0 - Negative POSIX error code 1087 * 1088 */ 1089 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 1090 unsigned size, void *value); 1091 1092 /** 1093 * Query hardware or driver information. 1094 * 1095 * The return size is query-specific and depends on the "info_id" parameter. 1096 * No more than "size" bytes is returned. 1097 * 1098 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1099 * \param info - \c [in] amdgpu_sw_info_* 1100 * \param value - \c [out] Pointer to the return value. 1101 * 1102 * \return 0 on success\n 1103 * <0 - Negative POSIX error code 1104 * 1105 */ 1106 int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, 1107 void *value); 1108 1109 /** 1110 * Query information about GDS 1111 * 1112 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1113 * \param gds_info - \c [out] Pointer to structure to get GDS information 1114 * 1115 * \return 0 on success\n 1116 * <0 - Negative POSIX Error code 1117 * 1118 */ 1119 int amdgpu_query_gds_info(amdgpu_device_handle dev, 1120 struct amdgpu_gds_resource_info *gds_info); 1121 1122 /** 1123 * Query information about sensor. 1124 * 1125 * The return size is query-specific and depends on the "sensor_type" 1126 * parameter. No more than "size" bytes is returned. 1127 * 1128 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1129 * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_* 1130 * \param size - \c [in] Size of the returned value. 1131 * \param value - \c [out] Pointer to the return value. 1132 * 1133 * \return 0 on success\n 1134 * <0 - Negative POSIX Error code 1135 * 1136 */ 1137 int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, 1138 unsigned size, void *value); 1139 1140 /** 1141 * Read a set of consecutive memory-mapped registers. 1142 * Not all registers are allowed to be read by userspace. 1143 * 1144 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize( 1145 * \param dword_offset - \c [in] Register offset in dwords 1146 * \param count - \c [in] The number of registers to read starting 1147 * from the offset 1148 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other 1149 * uses. Set it to 0xffffffff if unsure. 1150 * \param flags - \c [in] Flags with additional information. 1151 * \param values - \c [out] The pointer to return values. 1152 * 1153 * \return 0 on success\n 1154 * <0 - Negative POSIX error code 1155 * 1156 */ 1157 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, 1158 unsigned count, uint32_t instance, uint32_t flags, 1159 uint32_t *values); 1160 1161 /** 1162 * Flag to request VA address range in the 32bit address space 1163 */ 1164 #define AMDGPU_VA_RANGE_32_BIT 0x1 1165 #define AMDGPU_VA_RANGE_HIGH 0x2 1166 1167 /** 1168 * Allocate virtual address range 1169 * 1170 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1171 * \param va_range_type - \c [in] Type of MC va range from which to allocate 1172 * \param size - \c [in] Size of range. Size must be correctly* aligned. 1173 * It is client responsibility to correctly aligned size based on the future 1174 * usage of allocated range. 1175 * \param va_base_alignment - \c [in] Overwrite base address alignment 1176 * requirement for GPU VM MC virtual 1177 * address assignment. Must be multiple of size alignments received as 1178 * 'amdgpu_buffer_size_alignments'. 1179 * If 0 use the default one. 1180 * \param va_base_required - \c [in] Specified required va base address. 1181 * If 0 then library choose available one. 1182 * If !0 value will be passed and those value already "in use" then 1183 * corresponding error status will be returned. 1184 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used 1185 * by client. 1186 * \param va_range_handle - \c [out] On return: Handle assigned to allocation 1187 * \param flags - \c [in] flags for special VA range 1188 * 1189 * \return 0 on success\n 1190 * >0 - AMD specific error code\n 1191 * <0 - Negative POSIX Error code 1192 * 1193 * \notes \n 1194 * It is client responsibility to correctly handle VA assignments and usage. 1195 * Neither kernel driver nor libdrm_amdpgu are able to prevent and 1196 * detect wrong va assignemnt. 1197 * 1198 * It is client responsibility to correctly handle multi-GPU cases and to pass 1199 * the corresponding arrays of all devices handles where corresponding VA will 1200 * be used. 1201 * 1202 */ 1203 int amdgpu_va_range_alloc(amdgpu_device_handle dev, 1204 enum amdgpu_gpu_va_range va_range_type, 1205 uint64_t size, 1206 uint64_t va_base_alignment, 1207 uint64_t va_base_required, 1208 uint64_t *va_base_allocated, 1209 amdgpu_va_handle *va_range_handle, 1210 uint64_t flags); 1211 1212 /** 1213 * Free previously allocated virtual address range 1214 * 1215 * 1216 * \param va_range_handle - \c [in] Handle assigned to VA allocation 1217 * 1218 * \return 0 on success\n 1219 * >0 - AMD specific error code\n 1220 * <0 - Negative POSIX Error code 1221 * 1222 */ 1223 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle); 1224 1225 /** 1226 * Query virtual address range 1227 * 1228 * UMD can query GPU VM range supported by each device 1229 * to initialize its own VAM accordingly. 1230 * 1231 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1232 * \param type - \c [in] Type of virtual address range 1233 * \param offset - \c [out] Start offset of virtual address range 1234 * \param size - \c [out] Size of virtual address range 1235 * 1236 * \return 0 on success\n 1237 * <0 - Negative POSIX Error code 1238 * 1239 */ 1240 1241 int amdgpu_va_range_query(amdgpu_device_handle dev, 1242 enum amdgpu_gpu_va_range type, 1243 uint64_t *start, 1244 uint64_t *end); 1245 1246 /** 1247 * VA mapping/unmapping for the buffer object 1248 * 1249 * \param bo - \c [in] BO handle 1250 * \param offset - \c [in] Start offset to map 1251 * \param size - \c [in] Size to map 1252 * \param addr - \c [in] Start virtual address. 1253 * \param flags - \c [in] Supported flags for mapping/unmapping 1254 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1255 * 1256 * \return 0 on success\n 1257 * <0 - Negative POSIX Error code 1258 * 1259 */ 1260 1261 int amdgpu_bo_va_op(amdgpu_bo_handle bo, 1262 uint64_t offset, 1263 uint64_t size, 1264 uint64_t addr, 1265 uint64_t flags, 1266 uint32_t ops); 1267 1268 /** 1269 * VA mapping/unmapping for a buffer object or PRT region. 1270 * 1271 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all 1272 * parameters are treated "raw", i.e. size is not automatically aligned, and 1273 * all flags must be specified explicitly. 1274 * 1275 * \param dev - \c [in] device handle 1276 * \param bo - \c [in] BO handle (may be NULL) 1277 * \param offset - \c [in] Start offset to map 1278 * \param size - \c [in] Size to map 1279 * \param addr - \c [in] Start virtual address. 1280 * \param flags - \c [in] Supported flags for mapping/unmapping 1281 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1282 * 1283 * \return 0 on success\n 1284 * <0 - Negative POSIX Error code 1285 * 1286 */ 1287 1288 int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, 1289 amdgpu_bo_handle bo, 1290 uint64_t offset, 1291 uint64_t size, 1292 uint64_t addr, 1293 uint64_t flags, 1294 uint32_t ops); 1295 1296 /** 1297 * create semaphore 1298 * 1299 * \param sem - \c [out] semaphore handle 1300 * 1301 * \return 0 on success\n 1302 * <0 - Negative POSIX Error code 1303 * 1304 */ 1305 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); 1306 1307 /** 1308 * signal semaphore 1309 * 1310 * \param context - \c [in] GPU Context 1311 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1312 * \param ip_instance - \c [in] Index of the IP block of the same type 1313 * \param ring - \c [in] Specify ring index of the IP 1314 * \param sem - \c [in] semaphore handle 1315 * 1316 * \return 0 on success\n 1317 * <0 - Negative POSIX Error code 1318 * 1319 */ 1320 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, 1321 uint32_t ip_type, 1322 uint32_t ip_instance, 1323 uint32_t ring, 1324 amdgpu_semaphore_handle sem); 1325 1326 /** 1327 * wait semaphore 1328 * 1329 * \param context - \c [in] GPU Context 1330 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1331 * \param ip_instance - \c [in] Index of the IP block of the same type 1332 * \param ring - \c [in] Specify ring index of the IP 1333 * \param sem - \c [in] semaphore handle 1334 * 1335 * \return 0 on success\n 1336 * <0 - Negative POSIX Error code 1337 * 1338 */ 1339 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, 1340 uint32_t ip_type, 1341 uint32_t ip_instance, 1342 uint32_t ring, 1343 amdgpu_semaphore_handle sem); 1344 1345 /** 1346 * destroy semaphore 1347 * 1348 * \param sem - \c [in] semaphore handle 1349 * 1350 * \return 0 on success\n 1351 * <0 - Negative POSIX Error code 1352 * 1353 */ 1354 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); 1355 1356 /** 1357 * Get the ASIC marketing name 1358 * 1359 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1360 * 1361 * \return the constant string of the marketing name 1362 * "NULL" means the ASIC is not found 1363 */ 1364 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); 1365 1366 /** 1367 * Create kernel sync object 1368 * 1369 * \param dev - \c [in] device handle 1370 * \param flags - \c [in] flags that affect creation 1371 * \param syncobj - \c [out] sync object handle 1372 * 1373 * \return 0 on success\n 1374 * <0 - Negative POSIX Error code 1375 * 1376 */ 1377 int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, 1378 uint32_t flags, 1379 uint32_t *syncobj); 1380 1381 /** 1382 * Create kernel sync object 1383 * 1384 * \param dev - \c [in] device handle 1385 * \param syncobj - \c [out] sync object handle 1386 * 1387 * \return 0 on success\n 1388 * <0 - Negative POSIX Error code 1389 * 1390 */ 1391 int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, 1392 uint32_t *syncobj); 1393 /** 1394 * Destroy kernel sync object 1395 * 1396 * \param dev - \c [in] device handle 1397 * \param syncobj - \c [in] sync object handle 1398 * 1399 * \return 0 on success\n 1400 * <0 - Negative POSIX Error code 1401 * 1402 */ 1403 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, 1404 uint32_t syncobj); 1405 1406 /** 1407 * Reset kernel sync objects to unsignalled state. 1408 * 1409 * \param dev - \c [in] device handle 1410 * \param syncobjs - \c [in] array of sync object handles 1411 * \param syncobj_count - \c [in] number of handles in syncobjs 1412 * 1413 * \return 0 on success\n 1414 * <0 - Negative POSIX Error code 1415 * 1416 */ 1417 int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, 1418 const uint32_t *syncobjs, uint32_t syncobj_count); 1419 1420 /** 1421 * Signal kernel sync objects. 1422 * 1423 * \param dev - \c [in] device handle 1424 * \param syncobjs - \c [in] array of sync object handles 1425 * \param syncobj_count - \c [in] number of handles in syncobjs 1426 * 1427 * \return 0 on success\n 1428 * <0 - Negative POSIX Error code 1429 * 1430 */ 1431 int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, 1432 const uint32_t *syncobjs, uint32_t syncobj_count); 1433 1434 /** 1435 * Wait for one or all sync objects to signal. 1436 * 1437 * \param dev - \c [in] self-explanatory 1438 * \param handles - \c [in] array of sync object handles 1439 * \param num_handles - \c [in] self-explanatory 1440 * \param timeout_nsec - \c [in] self-explanatory 1441 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1442 * \param first_signaled - \c [in] self-explanatory 1443 * 1444 * \return 0 on success\n 1445 * -ETIME - Timeout 1446 * <0 - Negative POSIX Error code 1447 * 1448 */ 1449 int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, 1450 uint32_t *handles, unsigned num_handles, 1451 int64_t timeout_nsec, unsigned flags, 1452 uint32_t *first_signaled); 1453 1454 /** 1455 * Export kernel sync object to shareable fd. 1456 * 1457 * \param dev - \c [in] device handle 1458 * \param syncobj - \c [in] sync object handle 1459 * \param shared_fd - \c [out] shared file descriptor. 1460 * 1461 * \return 0 on success\n 1462 * <0 - Negative POSIX Error code 1463 * 1464 */ 1465 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, 1466 uint32_t syncobj, 1467 int *shared_fd); 1468 /** 1469 * Import kernel sync object from shareable fd. 1470 * 1471 * \param dev - \c [in] device handle 1472 * \param shared_fd - \c [in] shared file descriptor. 1473 * \param syncobj - \c [out] sync object handle 1474 * 1475 * \return 0 on success\n 1476 * <0 - Negative POSIX Error code 1477 * 1478 */ 1479 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, 1480 int shared_fd, 1481 uint32_t *syncobj); 1482 1483 /** 1484 * Export kernel sync object to a sync_file. 1485 * 1486 * \param dev - \c [in] device handle 1487 * \param syncobj - \c [in] sync object handle 1488 * \param sync_file_fd - \c [out] sync_file file descriptor. 1489 * 1490 * \return 0 on success\n 1491 * <0 - Negative POSIX Error code 1492 * 1493 */ 1494 int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, 1495 uint32_t syncobj, 1496 int *sync_file_fd); 1497 1498 /** 1499 * Import kernel sync object from a sync_file. 1500 * 1501 * \param dev - \c [in] device handle 1502 * \param syncobj - \c [in] sync object handle 1503 * \param sync_file_fd - \c [in] sync_file file descriptor. 1504 * 1505 * \return 0 on success\n 1506 * <0 - Negative POSIX Error code 1507 * 1508 */ 1509 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, 1510 uint32_t syncobj, 1511 int sync_file_fd); 1512 1513 /** 1514 * Export an amdgpu fence as a handle (syncobj or fd). 1515 * 1516 * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD} 1517 * \param out_handle returned handle 1518 * 1519 * \return 0 on success\n 1520 * <0 - Negative POSIX Error code 1521 */ 1522 int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, 1523 struct amdgpu_cs_fence *fence, 1524 uint32_t what, 1525 uint32_t *out_handle); 1526 1527 /** 1528 * Submit raw command submission to kernel 1529 * 1530 * \param dev - \c [in] device handle 1531 * \param context - \c [in] context handle for context id 1532 * \param bo_list_handle - \c [in] request bo list handle (0 for none) 1533 * \param num_chunks - \c [in] number of CS chunks to submit 1534 * \param chunks - \c [in] array of CS chunks 1535 * \param seq_no - \c [out] output sequence number for submission. 1536 * 1537 * \return 0 on success\n 1538 * <0 - Negative POSIX Error code 1539 * 1540 */ 1541 struct drm_amdgpu_cs_chunk; 1542 struct drm_amdgpu_cs_chunk_dep; 1543 struct drm_amdgpu_cs_chunk_data; 1544 1545 int amdgpu_cs_submit_raw(amdgpu_device_handle dev, 1546 amdgpu_context_handle context, 1547 amdgpu_bo_list_handle bo_list_handle, 1548 int num_chunks, 1549 struct drm_amdgpu_cs_chunk *chunks, 1550 uint64_t *seq_no); 1551 1552 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, 1553 struct drm_amdgpu_cs_chunk_dep *dep); 1554 void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, 1555 struct drm_amdgpu_cs_chunk_data *data); 1556 1557 /** 1558 * Reserve VMID 1559 * \param context - \c [in] GPU Context 1560 * \param flags - \c [in] TBD 1561 * 1562 * \return 0 on success otherwise POSIX Error code 1563 */ 1564 int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags); 1565 1566 /** 1567 * Free reserved VMID 1568 * \param context - \c [in] GPU Context 1569 * \param flags - \c [in] TBD 1570 * 1571 * \return 0 on success otherwise POSIX Error code 1572 */ 1573 int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags); 1574 1575 #ifdef __cplusplus 1576 } 1577 #endif 1578 #endif /* #ifdef _AMDGPU_H_ */ 1579