1/* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#ifndef __ARM_MACROS_S__ 7#define __ARM_MACROS_S__ 8 9#include <gic_common.h> 10#include <gicv2.h> 11#include <gicv3.h> 12#include <platform_def.h> 13 14.section .rodata.gic_reg_name, "aS" 15/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 16gicc_regs: 17 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 18 19/* Applicable only to GICv3 with SRE enabled */ 20icc_regs: 21 .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 22 23/* Registers common to both GICv2 and GICv3 */ 24gicd_pend_reg: 25 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 26 " Offset:\t\t\tvalue\n" 27newline: 28 .asciz "\n" 29spacer: 30 .asciz ":\t\t0x" 31 32 /* --------------------------------------------- 33 * The below utility macro prints out relevant GIC 34 * registers whenever an unhandled exception is 35 * taken in BL31 on ARM standard platforms. 36 * Expects: GICD base in x16, GICC base in x17 37 * Clobbers: x0 - x10, sp 38 * --------------------------------------------- 39 */ 40 .macro arm_print_gic_regs 41 /* Check for GICv3 system register access */ 42 mrs x7, id_aa64pfr0_el1 43 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 44 cmp x7, #1 45 b.ne print_gicv2 46 47 /* Check for SRE enable */ 48 mrs x8, ICC_SRE_EL3 49 tst x8, #ICC_SRE_SRE_BIT 50 b.eq print_gicv2 51 52 /* Load the icc reg list to x6 */ 53 adr x6, icc_regs 54 /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 55 mrs x8, ICC_HPPIR0_EL1 56 mrs x9, ICC_HPPIR1_EL1 57 mrs x10, ICC_CTLR_EL3 58 /* Store to the crash buf and print to console */ 59 bl str_in_crash_buf_print 60 b print_gic_common 61 62print_gicv2: 63 /* Load the gicc reg list to x6 */ 64 adr x6, gicc_regs 65 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 66 ldr w8, [x17, #GICC_HPPIR] 67 ldr w9, [x17, #GICC_AHPPIR] 68 ldr w10, [x17, #GICC_CTLR] 69 /* Store to the crash buf and print to console */ 70 bl str_in_crash_buf_print 71 72print_gic_common: 73 /* Print the GICD_ISPENDR regs */ 74 add x7, x16, #GICD_ISPENDR 75 adr x4, gicd_pend_reg 76 bl asm_print_str 77gicd_ispendr_loop: 78 sub x4, x7, x16 79 cmp x4, #0x280 80 b.eq exit_print_gic_regs 81 bl asm_print_hex 82 83 adr x4, spacer 84 bl asm_print_str 85 86 ldr x4, [x7], #8 87 bl asm_print_hex 88 89 adr x4, newline 90 bl asm_print_str 91 b gicd_ispendr_loop 92exit_print_gic_regs: 93 .endm 94 95#endif /* __ARM_MACROS_S__ */ 96