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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef _DDR_TOPOLOGY_DEF_H
7 #define _DDR_TOPOLOGY_DEF_H
8 
9 #include "ddr3_training_ip_def.h"
10 #include "ddr3_topology_def.h"
11 
12 #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
13 #include "mv_ddr_plat.h"
14 #endif
15 
16 #include "mv_ddr_topology.h"
17 #include "mv_ddr_spd.h"
18 #include "ddr3_logging_def.h"
19 
20 struct bus_params {
21 	/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
22 	u8 cs_bitmask;
23 
24 	/*
25 	 * mirror enable/disable
26 	 * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
27 	 */
28 	int mirror_enable_bitmask;
29 
30 	/* DQS Swap (polarity) - true if enable */
31 	int is_dqs_swap;
32 
33 	/* CK swap (polarity) - true if enable */
34 	int is_ck_swap;
35 };
36 
37 struct if_params {
38 	/* bus configuration */
39 	struct bus_params as_bus_params[MAX_BUS_NUM];
40 
41 	/* Speed Bin Table */
42 	enum hws_speed_bin speed_bin_index;
43 
44 	/* sdram device width */
45 	enum mv_ddr_dev_width bus_width;
46 
47 	/* total sdram capacity per die, megabits */
48 	enum mv_ddr_die_capacity memory_size;
49 
50 	/* The DDR frequency for each interfaces */
51 	enum hws_ddr_freq memory_freq;
52 
53 	/*
54 	 * delay CAS Write Latency
55 	 * - 0 for using default value (jedec suggested)
56 	 */
57 	u8 cas_wl;
58 
59 	/*
60 	 * delay CAS Latency
61 	 * - 0 for using default value (jedec suggested)
62 	 */
63 	u8 cas_l;
64 
65 	/* operation temperature */
66 	enum mv_ddr_temperature interface_temp;
67 
68 	/* 2T vs 1T mode (by default computed from number of CSs) */
69 	enum mv_ddr_timing timing;
70 };
71 
72 struct mv_ddr_topology_map {
73 	/* debug level configuration */
74 	enum mv_ddr_debug_level debug_level;
75 
76 	/* Number of interfaces (default is 12) */
77 	u8 if_act_mask;
78 
79 	/* Controller configuration per interface */
80 	struct if_params interface_params[MAX_INTERFACE_NUM];
81 
82 	/* Bit mask for active buses */
83 	u16 bus_act_mask;
84 
85 	/* source of ddr configuration data */
86 	enum mv_ddr_cfg_src cfg_src;
87 
88 	/* raw spd data */
89 	union mv_ddr_spd_data spd_data;
90 
91 	/* timing parameters */
92 	unsigned int timing_data[MV_DDR_TDATA_LAST];
93 };
94 
95 /* DDR3 training global configuration parameters */
96 struct tune_train_params {
97 	u32 ck_delay;
98 	u32 phy_reg3_val;
99 	u32 g_zpri_data;
100 	u32 g_znri_data;
101 	u32 g_zpri_ctrl;
102 	u32 g_znri_ctrl;
103 	u32 g_zpodt_data;
104 	u32 g_znodt_data;
105 	u32 g_zpodt_ctrl;
106 	u32 g_znodt_ctrl;
107 	u32 g_dic;
108 	u32 g_odt_config;
109 	u32 g_rtt_nom;
110 	u32 g_rtt_wr;
111 	u32 g_rtt_park;
112 };
113 
114 #endif /* _DDR_TOPOLOGY_DEF_H */
115