1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2006 Atmel Corporation
4 *
5 * Modified to support C structur SoC access by
6 * Andreas Bießmann <biessmann@corscience.de>
7 */
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <watchdog.h>
13 #include <serial.h>
14 #include <debug_uart.h>
15 #include <linux/compiler.h>
16
17 #include <asm/io.h>
18 #ifdef CONFIG_DM_SERIAL
19 #include <asm/arch/atmel_serial.h>
20 #endif
21 #include <asm/arch/clk.h>
22 #include <asm/arch/hardware.h>
23
24 #include "atmel_usart.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #ifndef CONFIG_DM_SERIAL
atmel_serial_setbrg_internal(atmel_usart3_t * usart,int id,int baudrate)29 static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
30 int baudrate)
31 {
32 unsigned long divisor;
33 unsigned long usart_hz;
34
35 /*
36 * Master Clock
37 * Baud Rate = --------------
38 * 16 * CD
39 */
40 usart_hz = get_usart_clk_rate(id);
41 divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
42 writel(USART3_BF(CD, divisor), &usart->brgr);
43 }
44
atmel_serial_init_internal(atmel_usart3_t * usart)45 static void atmel_serial_init_internal(atmel_usart3_t *usart)
46 {
47 /*
48 * Just in case: drain transmitter register
49 * 1000us is enough for baudrate >= 9600
50 */
51 if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
52 __udelay(1000);
53
54 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
55 }
56
atmel_serial_activate(atmel_usart3_t * usart)57 static void atmel_serial_activate(atmel_usart3_t *usart)
58 {
59 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
60 | USART3_BF(USCLKS, USART3_USCLKS_MCK)
61 | USART3_BF(CHRL, USART3_CHRL_8)
62 | USART3_BF(PAR, USART3_PAR_NONE)
63 | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
64 &usart->mr);
65 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
66 /* 100us is enough for the new settings to be settled */
67 __udelay(100);
68 }
69
atmel_serial_setbrg(void)70 static void atmel_serial_setbrg(void)
71 {
72 atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
73 CONFIG_USART_ID, gd->baudrate);
74 }
75
atmel_serial_init(void)76 static int atmel_serial_init(void)
77 {
78 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
79
80 atmel_serial_init_internal(usart);
81 serial_setbrg();
82 atmel_serial_activate(usart);
83
84 return 0;
85 }
86
atmel_serial_putc(char c)87 static void atmel_serial_putc(char c)
88 {
89 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
90
91 if (c == '\n')
92 serial_putc('\r');
93
94 while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
95 writel(c, &usart->thr);
96 }
97
atmel_serial_getc(void)98 static int atmel_serial_getc(void)
99 {
100 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
101
102 while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
103 WATCHDOG_RESET();
104 return readl(&usart->rhr);
105 }
106
atmel_serial_tstc(void)107 static int atmel_serial_tstc(void)
108 {
109 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
110 return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
111 }
112
113 static struct serial_device atmel_serial_drv = {
114 .name = "atmel_serial",
115 .start = atmel_serial_init,
116 .stop = NULL,
117 .setbrg = atmel_serial_setbrg,
118 .putc = atmel_serial_putc,
119 .puts = default_serial_puts,
120 .getc = atmel_serial_getc,
121 .tstc = atmel_serial_tstc,
122 };
123
atmel_serial_initialize(void)124 void atmel_serial_initialize(void)
125 {
126 serial_register(&atmel_serial_drv);
127 }
128
default_serial_console(void)129 __weak struct serial_device *default_serial_console(void)
130 {
131 return &atmel_serial_drv;
132 }
133 #endif
134
135 #ifdef CONFIG_DM_SERIAL
136 enum serial_clk_type {
137 CLK_TYPE_NORMAL = 0,
138 CLK_TYPE_DBGU,
139 };
140
141 struct atmel_serial_priv {
142 atmel_usart3_t *usart;
143 ulong usart_clk_rate;
144 };
145
_atmel_serial_set_brg(atmel_usart3_t * usart,ulong usart_clk_rate,int baudrate)146 static void _atmel_serial_set_brg(atmel_usart3_t *usart,
147 ulong usart_clk_rate, int baudrate)
148 {
149 unsigned long divisor;
150
151 divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
152 writel(USART3_BF(CD, divisor), &usart->brgr);
153 }
154
_atmel_serial_init(atmel_usart3_t * usart,ulong usart_clk_rate,int baudrate)155 void _atmel_serial_init(atmel_usart3_t *usart,
156 ulong usart_clk_rate, int baudrate)
157 {
158 writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);
159
160 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
161 USART3_BF(USCLKS, USART3_USCLKS_MCK) |
162 USART3_BF(CHRL, USART3_CHRL_8) |
163 USART3_BF(PAR, USART3_PAR_NONE) |
164 USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
165
166 _atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
167
168 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
169 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
170 }
171
atmel_serial_setbrg(struct udevice * dev,int baudrate)172 int atmel_serial_setbrg(struct udevice *dev, int baudrate)
173 {
174 struct atmel_serial_priv *priv = dev_get_priv(dev);
175
176 _atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);
177
178 return 0;
179 }
180
atmel_serial_getc(struct udevice * dev)181 static int atmel_serial_getc(struct udevice *dev)
182 {
183 struct atmel_serial_priv *priv = dev_get_priv(dev);
184
185 if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
186 return -EAGAIN;
187
188 return readl(&priv->usart->rhr);
189 }
190
atmel_serial_putc(struct udevice * dev,const char ch)191 static int atmel_serial_putc(struct udevice *dev, const char ch)
192 {
193 struct atmel_serial_priv *priv = dev_get_priv(dev);
194
195 if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
196 return -EAGAIN;
197
198 writel(ch, &priv->usart->thr);
199
200 return 0;
201 }
202
atmel_serial_pending(struct udevice * dev,bool input)203 static int atmel_serial_pending(struct udevice *dev, bool input)
204 {
205 struct atmel_serial_priv *priv = dev_get_priv(dev);
206 uint32_t csr = readl(&priv->usart->csr);
207
208 if (input)
209 return csr & USART3_BIT(RXRDY) ? 1 : 0;
210 else
211 return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
212 }
213
214 static const struct dm_serial_ops atmel_serial_ops = {
215 .putc = atmel_serial_putc,
216 .pending = atmel_serial_pending,
217 .getc = atmel_serial_getc,
218 .setbrg = atmel_serial_setbrg,
219 };
220
atmel_serial_enable_clk(struct udevice * dev)221 static int atmel_serial_enable_clk(struct udevice *dev)
222 {
223 struct atmel_serial_priv *priv = dev_get_priv(dev);
224 struct clk clk;
225 ulong clk_rate;
226 int ret;
227
228 ret = clk_get_by_index(dev, 0, &clk);
229 if (ret)
230 return -EINVAL;
231
232 if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
233 ret = clk_enable(&clk);
234 if (ret)
235 return ret;
236 }
237
238 clk_rate = clk_get_rate(&clk);
239 if (!clk_rate)
240 return -EINVAL;
241
242 priv->usart_clk_rate = clk_rate;
243
244 clk_free(&clk);
245
246 return 0;
247 }
248
atmel_serial_probe(struct udevice * dev)249 static int atmel_serial_probe(struct udevice *dev)
250 {
251 struct atmel_serial_platdata *plat = dev->platdata;
252 struct atmel_serial_priv *priv = dev_get_priv(dev);
253 int ret;
254 #if CONFIG_IS_ENABLED(OF_CONTROL)
255 fdt_addr_t addr_base;
256
257 addr_base = devfdt_get_addr(dev);
258 if (addr_base == FDT_ADDR_T_NONE)
259 return -ENODEV;
260
261 plat->base_addr = (uint32_t)addr_base;
262 #endif
263 priv->usart = (atmel_usart3_t *)plat->base_addr;
264
265 ret = atmel_serial_enable_clk(dev);
266 if (ret)
267 return ret;
268
269 _atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);
270
271 return 0;
272 }
273
274 #if CONFIG_IS_ENABLED(OF_CONTROL)
275 static const struct udevice_id atmel_serial_ids[] = {
276 {
277 .compatible = "atmel,at91sam9260-dbgu",
278 .data = CLK_TYPE_DBGU,
279 },
280 {
281 .compatible = "atmel,at91sam9260-usart",
282 .data = CLK_TYPE_NORMAL,
283 },
284 { }
285 };
286 #endif
287
288 U_BOOT_DRIVER(serial_atmel) = {
289 .name = "serial_atmel",
290 .id = UCLASS_SERIAL,
291 #if CONFIG_IS_ENABLED(OF_CONTROL)
292 .of_match = atmel_serial_ids,
293 .platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
294 #endif
295 .probe = atmel_serial_probe,
296 .ops = &atmel_serial_ops,
297 .flags = DM_FLAG_PRE_RELOC,
298 .priv_auto_alloc_size = sizeof(struct atmel_serial_priv),
299 };
300 #endif
301
302 #ifdef CONFIG_DEBUG_UART_ATMEL
_debug_uart_init(void)303 static inline void _debug_uart_init(void)
304 {
305 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
306
307 _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
308 }
309
_debug_uart_putc(int ch)310 static inline void _debug_uart_putc(int ch)
311 {
312 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
313
314 while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
315 ;
316
317 writel(ch, &usart->thr);
318 }
319
320 DEBUG_UART_FUNCS
321 #endif
322