1 /*
2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7 #ifdef DRV_TEGRA
8
9 #include <assert.h>
10 #include <stdio.h>
11 #include <string.h>
12 #include <sys/mman.h>
13 #include <tegra_drm.h>
14 #include <xf86drm.h>
15
16 #include "drv_priv.h"
17 #include "helpers.h"
18 #include "util.h"
19
20 /*
21 * GOB (Group Of Bytes) is the basic unit of the blocklinear layout.
22 * GOBs are arranged to blocks, where the height of the block (measured
23 * in GOBs) is configurable.
24 */
25 #define NV_BLOCKLINEAR_GOB_HEIGHT 8
26 #define NV_BLOCKLINEAR_GOB_WIDTH 64
27 #define NV_DEFAULT_BLOCK_HEIGHT_LOG2 4
28 #define NV_PREFERRED_PAGE_SIZE (128 * 1024)
29
30 // clang-format off
31 enum nv_mem_kind
32 {
33 NV_MEM_KIND_PITCH = 0,
34 NV_MEM_KIND_C32_2CRA = 0xdb,
35 NV_MEM_KIND_GENERIC_16Bx2 = 0xfe,
36 };
37
38 enum tegra_map_type {
39 TEGRA_READ_TILED_BUFFER = 0,
40 TEGRA_WRITE_TILED_BUFFER = 1,
41 };
42 // clang-format on
43
44 struct tegra_private_map_data {
45 void *tiled;
46 void *untiled;
47 };
48
49 static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB8888 };
50
compute_block_height_log2(int height)51 static int compute_block_height_log2(int height)
52 {
53 int block_height_log2 = NV_DEFAULT_BLOCK_HEIGHT_LOG2;
54
55 if (block_height_log2 > 0) {
56 /* Shrink, if a smaller block height could cover the whole
57 * surface height. */
58 int proposed = NV_BLOCKLINEAR_GOB_HEIGHT << (block_height_log2 - 1);
59 while (proposed >= height) {
60 block_height_log2--;
61 if (block_height_log2 == 0)
62 break;
63 proposed /= 2;
64 }
65 }
66 return block_height_log2;
67 }
68
compute_layout_blocklinear(int width,int height,int format,enum nv_mem_kind * kind,uint32_t * block_height_log2,uint32_t * stride,uint32_t * size)69 static void compute_layout_blocklinear(int width, int height, int format, enum nv_mem_kind *kind,
70 uint32_t *block_height_log2, uint32_t *stride,
71 uint32_t *size)
72 {
73 int pitch = drv_stride_from_format(format, width, 0);
74
75 /* Align to blocklinear blocks. */
76 pitch = ALIGN(pitch, NV_BLOCKLINEAR_GOB_WIDTH);
77
78 /* Compute padded height. */
79 *block_height_log2 = compute_block_height_log2(height);
80 int block_height = 1 << *block_height_log2;
81 int padded_height = ALIGN(height, NV_BLOCKLINEAR_GOB_HEIGHT * block_height);
82
83 int bytes = pitch * padded_height;
84
85 /* Pad the allocation to the preferred page size.
86 * This will reduce the required page table size (see discussion in NV
87 * bug 1321091), and also acts as a WAR for NV bug 1325421.
88 */
89 bytes = ALIGN(bytes, NV_PREFERRED_PAGE_SIZE);
90
91 *kind = NV_MEM_KIND_C32_2CRA;
92 *stride = pitch;
93 *size = bytes;
94 }
95
compute_layout_linear(int width,int height,int format,uint32_t * stride,uint32_t * size)96 static void compute_layout_linear(int width, int height, int format, uint32_t *stride,
97 uint32_t *size)
98 {
99 *stride = ALIGN(drv_stride_from_format(format, width, 0), 64);
100 *size = *stride * height;
101 }
102
transfer_tile(struct bo * bo,uint8_t * tiled,uint8_t * untiled,enum tegra_map_type type,uint32_t bytes_per_pixel,uint32_t gob_top,uint32_t gob_left,uint32_t gob_size_pixels,uint8_t * tiled_last)103 static void transfer_tile(struct bo *bo, uint8_t *tiled, uint8_t *untiled, enum tegra_map_type type,
104 uint32_t bytes_per_pixel, uint32_t gob_top, uint32_t gob_left,
105 uint32_t gob_size_pixels, uint8_t *tiled_last)
106 {
107 uint8_t *tmp;
108 uint32_t x, y, k;
109 for (k = 0; k < gob_size_pixels; k++) {
110 /*
111 * Given the kth pixel starting from the tile specified by
112 * gob_top and gob_left, unswizzle to get the standard (x, y)
113 * representation.
114 */
115 x = gob_left + (((k >> 3) & 8) | ((k >> 1) & 4) | (k & 3));
116 y = gob_top + ((k >> 7 << 3) | ((k >> 3) & 6) | ((k >> 2) & 1));
117
118 if (tiled >= tiled_last)
119 return;
120
121 if (x >= bo->width || y >= bo->height) {
122 tiled += bytes_per_pixel;
123 continue;
124 }
125
126 tmp = untiled + y * bo->strides[0] + x * bytes_per_pixel;
127
128 if (type == TEGRA_READ_TILED_BUFFER)
129 memcpy(tmp, tiled, bytes_per_pixel);
130 else if (type == TEGRA_WRITE_TILED_BUFFER)
131 memcpy(tiled, tmp, bytes_per_pixel);
132
133 /* Move on to next pixel. */
134 tiled += bytes_per_pixel;
135 }
136 }
137
transfer_tiled_memory(struct bo * bo,uint8_t * tiled,uint8_t * untiled,enum tegra_map_type type)138 static void transfer_tiled_memory(struct bo *bo, uint8_t *tiled, uint8_t *untiled,
139 enum tegra_map_type type)
140 {
141 uint32_t gob_width, gob_height, gob_size_bytes, gob_size_pixels, gob_count_x, gob_count_y,
142 gob_top, gob_left;
143 uint32_t i, j, offset;
144 uint8_t *tmp, *tiled_last;
145 uint32_t bytes_per_pixel = drv_stride_from_format(bo->format, 1, 0);
146
147 /*
148 * The blocklinear format consists of 8*(2^n) x 64 byte sized tiles,
149 * where 0 <= n <= 4.
150 */
151 gob_width = DIV_ROUND_UP(NV_BLOCKLINEAR_GOB_WIDTH, bytes_per_pixel);
152 gob_height = NV_BLOCKLINEAR_GOB_HEIGHT * (1 << NV_DEFAULT_BLOCK_HEIGHT_LOG2);
153 /* Calculate the height from maximum possible gob height */
154 while (gob_height > NV_BLOCKLINEAR_GOB_HEIGHT && gob_height >= 2 * bo->height)
155 gob_height /= 2;
156
157 gob_size_bytes = gob_height * NV_BLOCKLINEAR_GOB_WIDTH;
158 gob_size_pixels = gob_height * gob_width;
159
160 gob_count_x = DIV_ROUND_UP(bo->strides[0], NV_BLOCKLINEAR_GOB_WIDTH);
161 gob_count_y = DIV_ROUND_UP(bo->height, gob_height);
162
163 tiled_last = tiled + bo->total_size;
164
165 offset = 0;
166 for (j = 0; j < gob_count_y; j++) {
167 gob_top = j * gob_height;
168 for (i = 0; i < gob_count_x; i++) {
169 tmp = tiled + offset;
170 gob_left = i * gob_width;
171
172 transfer_tile(bo, tmp, untiled, type, bytes_per_pixel, gob_top, gob_left,
173 gob_size_pixels, tiled_last);
174
175 offset += gob_size_bytes;
176 }
177 }
178 }
179
tegra_init(struct driver * drv)180 static int tegra_init(struct driver *drv)
181 {
182 struct format_metadata metadata;
183 uint64_t use_flags = BO_USE_RENDER_MASK;
184
185 metadata.tiling = NV_MEM_KIND_PITCH;
186 metadata.priority = 1;
187 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
188
189 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
190 &metadata, use_flags);
191
192 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
193 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
194
195 use_flags &= ~BO_USE_SW_WRITE_OFTEN;
196 use_flags &= ~BO_USE_SW_READ_OFTEN;
197 use_flags &= ~BO_USE_LINEAR;
198
199 metadata.tiling = NV_MEM_KIND_C32_2CRA;
200 metadata.priority = 2;
201
202 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
203 &metadata, use_flags);
204
205 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
206 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
207 return 0;
208 }
209
tegra_bo_create(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)210 static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
211 uint64_t use_flags)
212 {
213 uint32_t size, stride, block_height_log2 = 0;
214 enum nv_mem_kind kind = NV_MEM_KIND_PITCH;
215 struct drm_tegra_gem_create gem_create;
216 int ret;
217
218 if (use_flags &
219 (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
220 compute_layout_linear(width, height, format, &stride, &size);
221 else
222 compute_layout_blocklinear(width, height, format, &kind, &block_height_log2,
223 &stride, &size);
224
225 memset(&gem_create, 0, sizeof(gem_create));
226 gem_create.size = size;
227 gem_create.flags = 0;
228
229 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
230 if (ret) {
231 drv_log("DRM_IOCTL_TEGRA_GEM_CREATE failed (size=%zu)\n", size);
232 return ret;
233 }
234
235 bo->handles[0].u32 = gem_create.handle;
236 bo->offsets[0] = 0;
237 bo->total_size = bo->sizes[0] = size;
238 bo->strides[0] = stride;
239
240 if (kind != NV_MEM_KIND_PITCH) {
241 struct drm_tegra_gem_set_tiling gem_tile;
242
243 memset(&gem_tile, 0, sizeof(gem_tile));
244 gem_tile.handle = bo->handles[0].u32;
245 gem_tile.mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
246 gem_tile.value = block_height_log2;
247
248 ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_SET_TILING, &gem_tile,
249 sizeof(gem_tile));
250 if (ret < 0) {
251 drv_gem_bo_destroy(bo);
252 return ret;
253 }
254
255 /* Encode blocklinear parameters for EGLImage creation. */
256 bo->tiling = (kind & 0xff) | ((block_height_log2 & 0xf) << 8);
257 bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
258 }
259
260 return 0;
261 }
262
tegra_bo_import(struct bo * bo,struct drv_import_fd_data * data)263 static int tegra_bo_import(struct bo *bo, struct drv_import_fd_data *data)
264 {
265 int ret;
266 struct drm_tegra_gem_get_tiling gem_get_tiling;
267
268 ret = drv_prime_bo_import(bo, data);
269 if (ret)
270 return ret;
271
272 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
273 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
274 gem_get_tiling.handle = bo->handles[0].u32;
275
276 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_GET_TILING, &gem_get_tiling);
277 if (ret) {
278 drv_gem_bo_destroy(bo);
279 return ret;
280 }
281
282 /* NOTE(djmk): we only know about one tiled format, so if our drmIoctl call tells us we are
283 tiled, assume it is this format (NV_MEM_KIND_C32_2CRA) otherwise linear (KIND_PITCH). */
284 if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_PITCH) {
285 bo->tiling = NV_MEM_KIND_PITCH;
286 } else if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_BLOCK) {
287 bo->tiling = NV_MEM_KIND_C32_2CRA;
288 } else {
289 drv_log("%s: unknown tile format %d\n", __func__, gem_get_tiling.mode);
290 drv_gem_bo_destroy(bo);
291 assert(0);
292 }
293
294 bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
295 return 0;
296 }
297
tegra_bo_map(struct bo * bo,struct vma * vma,size_t plane,uint32_t map_flags)298 static void *tegra_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
299 {
300 int ret;
301 struct drm_tegra_gem_mmap gem_map;
302 struct tegra_private_map_data *priv;
303
304 memset(&gem_map, 0, sizeof(gem_map));
305 gem_map.handle = bo->handles[0].u32;
306
307 ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_MMAP, &gem_map, sizeof(gem_map));
308 if (ret < 0) {
309 drv_log("DRM_TEGRA_GEM_MMAP failed\n");
310 return MAP_FAILED;
311 }
312
313 void *addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
314 gem_map.offset);
315 vma->length = bo->total_size;
316 if ((bo->tiling & 0xFF) == NV_MEM_KIND_C32_2CRA && addr != MAP_FAILED) {
317 priv = calloc(1, sizeof(*priv));
318 priv->untiled = calloc(1, bo->total_size);
319 priv->tiled = addr;
320 vma->priv = priv;
321 transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_READ_TILED_BUFFER);
322 addr = priv->untiled;
323 }
324
325 return addr;
326 }
327
tegra_bo_unmap(struct bo * bo,struct vma * vma)328 static int tegra_bo_unmap(struct bo *bo, struct vma *vma)
329 {
330 if (vma->priv) {
331 struct tegra_private_map_data *priv = vma->priv;
332 vma->addr = priv->tiled;
333 free(priv->untiled);
334 free(priv);
335 vma->priv = NULL;
336 }
337
338 return munmap(vma->addr, vma->length);
339 }
340
tegra_bo_flush(struct bo * bo,struct mapping * mapping)341 static int tegra_bo_flush(struct bo *bo, struct mapping *mapping)
342 {
343 struct tegra_private_map_data *priv = mapping->vma->priv;
344
345 if (priv && (mapping->vma->map_flags & BO_MAP_WRITE))
346 transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_WRITE_TILED_BUFFER);
347
348 return 0;
349 }
350
351 const struct backend backend_tegra = {
352 .name = "tegra",
353 .init = tegra_init,
354 .bo_create = tegra_bo_create,
355 .bo_destroy = drv_gem_bo_destroy,
356 .bo_import = tegra_bo_import,
357 .bo_map = tegra_bo_map,
358 .bo_unmap = tegra_bo_unmap,
359 .bo_flush = tegra_bo_flush,
360 };
361
362 #endif
363