1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #include "main/macros.h"
34 #include "main/enums.h"
35
36 #include "program/program.h"
37 #include "intel_batchbuffer.h"
38
39 #include "brw_defines.h"
40 #include "brw_context.h"
41 #include "brw_ff_gs.h"
42
43 /**
44 * Allocate registers for GS.
45 *
46 * If sol_program is true, then:
47 *
48 * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
49 * 1 needs to be set aside to hold the streamed vertex buffer indices.
50 *
51 * - The thread will need to use the destination_indices register.
52 */
brw_ff_gs_alloc_regs(struct brw_ff_gs_compile * c,GLuint nr_verts,bool sol_program)53 static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c,
54 GLuint nr_verts,
55 bool sol_program)
56 {
57 GLuint i = 0,j;
58
59 /* Register usage is static, precompute here:
60 */
61 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
62
63 /* Streamed vertex buffer indices */
64 if (sol_program)
65 c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
66
67 /* Payload vertices plus space for more generated vertices:
68 */
69 for (j = 0; j < nr_verts; j++) {
70 c->reg.vertex[j] = brw_vec4_grf(i, 0);
71 i += c->nr_regs;
72 }
73
74 c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
75 c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
76
77 if (sol_program) {
78 c->reg.destination_indices =
79 retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD);
80 }
81
82 c->prog_data.urb_read_length = c->nr_regs;
83 c->prog_data.total_grf = i;
84 }
85
86
87 /**
88 * Set up the initial value of c->reg.header register based on c->reg.R0.
89 *
90 * The following information is passed to the GS thread in R0, and needs to be
91 * included in the first URB_WRITE or FF_SYNC message sent by the GS:
92 *
93 * - DWORD 0 [31:0] handle info (Gen4 only)
94 * - DWORD 5 [7:0] FFTID
95 * - DWORD 6 [31:0] Debug info
96 * - DWORD 7 [31:0] Debug info
97 *
98 * This function sets up the above data by copying by copying the contents of
99 * R0 to the header register.
100 */
brw_ff_gs_initialize_header(struct brw_ff_gs_compile * c)101 static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile *c)
102 {
103 struct brw_codegen *p = &c->func;
104 brw_MOV(p, c->reg.header, c->reg.R0);
105 }
106
107 /**
108 * Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
109 *
110 * In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
111 * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
112 * need to be able to update on a per-vertex basis.
113 */
brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile * c,unsigned dw2)114 static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile *c,
115 unsigned dw2)
116 {
117 struct brw_codegen *p = &c->func;
118 brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
119 }
120
121 /**
122 * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
123 *
124 * When the thread is spawned, GRF 0 contains the primitive type in bits 4:0
125 * of DWORD 2. URB_WRITE messages need the primitive type in bits 6:2 of
126 * DWORD 2. So this function extracts the primitive type field, bitshifts it
127 * appropriately, and stores it in c->reg.header.
128 */
brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile * c)129 static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile *c)
130 {
131 struct brw_codegen *p = &c->func;
132 brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
133 brw_imm_ud(0x1f));
134 brw_SHL(p, get_element_ud(c->reg.header, 2),
135 get_element_ud(c->reg.header, 2), brw_imm_ud(2));
136 }
137
138 /**
139 * Apply an additive offset to DWORD 2 of c->reg.header.
140 *
141 * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
142 * for each vertex.
143 */
brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile * c,int offset)144 static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile *c,
145 int offset)
146 {
147 struct brw_codegen *p = &c->func;
148 brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
149 brw_imm_d(offset));
150 }
151
152
153 /**
154 * Emit a vertex using the URB_WRITE message. Use the contents of
155 * c->reg.header for the message header, and the registers starting at \c vert
156 * for the vertex data.
157 *
158 * If \c last is true, then this is the last vertex, so no further URB space
159 * should be allocated, and this message should end the thread.
160 *
161 * If \c last is false, then a new URB entry will be allocated, and its handle
162 * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
163 * message.
164 */
brw_ff_gs_emit_vue(struct brw_ff_gs_compile * c,struct brw_reg vert,bool last)165 static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c,
166 struct brw_reg vert,
167 bool last)
168 {
169 struct brw_codegen *p = &c->func;
170 int write_offset = 0;
171 bool complete = false;
172
173 do {
174 /* We can't write more than 14 registers at a time to the URB */
175 int write_len = MIN2(c->nr_regs - write_offset, 14);
176 if (write_len == c->nr_regs - write_offset)
177 complete = true;
178
179 /* Copy the vertex from vertn into m1..mN+1:
180 */
181 brw_copy8(p, brw_message_reg(1), offset(vert, write_offset), write_len);
182
183 /* Send the vertex data to the URB. If this is the last write for this
184 * vertex, then we mark it as complete, and either end the thread or
185 * allocate another vertex URB entry (depending whether this is the last
186 * vertex).
187 */
188 enum brw_urb_write_flags flags;
189 if (!complete)
190 flags = BRW_URB_WRITE_NO_FLAGS;
191 else if (last)
192 flags = BRW_URB_WRITE_EOT_COMPLETE;
193 else
194 flags = BRW_URB_WRITE_ALLOCATE_COMPLETE;
195 brw_urb_WRITE(p,
196 (flags & BRW_URB_WRITE_ALLOCATE) ? c->reg.temp
197 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
198 0,
199 c->reg.header,
200 flags,
201 write_len + 1, /* msg length */
202 (flags & BRW_URB_WRITE_ALLOCATE) ? 1
203 : 0, /* response length */
204 write_offset, /* urb offset */
205 BRW_URB_SWIZZLE_NONE);
206 write_offset += write_len;
207 } while (!complete);
208
209 if (!last) {
210 brw_MOV(p, get_element_ud(c->reg.header, 0),
211 get_element_ud(c->reg.temp, 0));
212 }
213 }
214
215 /**
216 * Send an FF_SYNC message to ensure that all previously spawned GS threads
217 * have finished sending primitives down the pipeline, and to allocate a URB
218 * entry for the first output vertex. Only needed on Ironlake+.
219 *
220 * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
221 * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
222 * the allocated URB entry (which will be needed by the URB_WRITE meesage that
223 * follows).
224 */
brw_ff_gs_ff_sync(struct brw_ff_gs_compile * c,int num_prim)225 static void brw_ff_gs_ff_sync(struct brw_ff_gs_compile *c, int num_prim)
226 {
227 struct brw_codegen *p = &c->func;
228
229 brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
230 brw_ff_sync(p,
231 c->reg.temp,
232 0,
233 c->reg.header,
234 1, /* allocate */
235 1, /* response length */
236 0 /* eot */);
237 brw_MOV(p, get_element_ud(c->reg.header, 0),
238 get_element_ud(c->reg.temp, 0));
239 }
240
241
242 void
brw_ff_gs_quads(struct brw_ff_gs_compile * c,struct brw_ff_gs_prog_key * key)243 brw_ff_gs_quads(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key)
244 {
245 brw_ff_gs_alloc_regs(c, 4, false);
246 brw_ff_gs_initialize_header(c);
247 /* Use polygons for correct edgeflag behaviour. Note that vertex 3
248 * is the PV for quads, but vertex 0 for polygons:
249 */
250 if (c->func.devinfo->gen == 5)
251 brw_ff_gs_ff_sync(c, 1);
252 brw_ff_gs_overwrite_header_dw2(
253 c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
254 | URB_WRITE_PRIM_START));
255 if (key->pv_first) {
256 brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
257 brw_ff_gs_overwrite_header_dw2(
258 c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
259 brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
260 brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
261 brw_ff_gs_overwrite_header_dw2(
262 c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
263 | URB_WRITE_PRIM_END));
264 brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
265 }
266 else {
267 brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
268 brw_ff_gs_overwrite_header_dw2(
269 c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
270 brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
271 brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
272 brw_ff_gs_overwrite_header_dw2(
273 c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
274 | URB_WRITE_PRIM_END));
275 brw_ff_gs_emit_vue(c, c->reg.vertex[2], 1);
276 }
277 }
278
279 void
brw_ff_gs_quad_strip(struct brw_ff_gs_compile * c,struct brw_ff_gs_prog_key * key)280 brw_ff_gs_quad_strip(struct brw_ff_gs_compile *c,
281 struct brw_ff_gs_prog_key *key)
282 {
283 brw_ff_gs_alloc_regs(c, 4, false);
284 brw_ff_gs_initialize_header(c);
285
286 if (c->func.devinfo->gen == 5)
287 brw_ff_gs_ff_sync(c, 1);
288 brw_ff_gs_overwrite_header_dw2(
289 c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
290 | URB_WRITE_PRIM_START));
291 if (key->pv_first) {
292 brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
293 brw_ff_gs_overwrite_header_dw2(
294 c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
295 brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
296 brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
297 brw_ff_gs_overwrite_header_dw2(
298 c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
299 | URB_WRITE_PRIM_END));
300 brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
301 }
302 else {
303 brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
304 brw_ff_gs_overwrite_header_dw2(
305 c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
306 brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
307 brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
308 brw_ff_gs_overwrite_header_dw2(
309 c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
310 | URB_WRITE_PRIM_END));
311 brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
312 }
313 }
314
brw_ff_gs_lines(struct brw_ff_gs_compile * c)315 void brw_ff_gs_lines(struct brw_ff_gs_compile *c)
316 {
317 brw_ff_gs_alloc_regs(c, 2, false);
318 brw_ff_gs_initialize_header(c);
319
320 if (c->func.devinfo->gen == 5)
321 brw_ff_gs_ff_sync(c, 1);
322 brw_ff_gs_overwrite_header_dw2(
323 c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
324 | URB_WRITE_PRIM_START));
325 brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
326 brw_ff_gs_overwrite_header_dw2(
327 c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
328 | URB_WRITE_PRIM_END));
329 brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
330 }
331
332 /**
333 * Generate the geometry shader program used on Gen6 to perform stream output
334 * (transform feedback).
335 */
336 void
gen6_sol_program(struct brw_ff_gs_compile * c,struct brw_ff_gs_prog_key * key,unsigned num_verts,bool check_edge_flags)337 gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
338 unsigned num_verts, bool check_edge_flags)
339 {
340 struct brw_codegen *p = &c->func;
341 brw_inst *inst;
342 c->prog_data.svbi_postincrement_value = num_verts;
343
344 brw_ff_gs_alloc_regs(c, num_verts, true);
345 brw_ff_gs_initialize_header(c);
346
347 if (key->num_transform_feedback_bindings > 0) {
348 unsigned vertex, binding;
349 struct brw_reg destination_indices_uw =
350 vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
351
352 /* Note: since we use the binding table to keep track of buffer offsets
353 * and stride, the GS doesn't need to keep track of a separate pointer
354 * into each buffer; it uses a single pointer which increments by 1 for
355 * each vertex. So we use SVBI0 for this pointer, regardless of whether
356 * transform feedback is in interleaved or separate attribs mode.
357 *
358 * Make sure that the buffers have enough room for all the vertices.
359 */
360 brw_ADD(p, get_element_ud(c->reg.temp, 0),
361 get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
362 brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
363 get_element_ud(c->reg.temp, 0),
364 get_element_ud(c->reg.SVBI, 4));
365 brw_IF(p, BRW_EXECUTE_1);
366
367 /* Compute the destination indices to write to. Usually we use SVBI[0]
368 * + (0, 1, 2). However, for odd-numbered triangles in tristrips, the
369 * vertices come down the pipeline in reversed winding order, so we need
370 * to flip the order when writing to the transform feedback buffer. To
371 * ensure that flatshading accuracy is preserved, we need to write them
372 * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
373 * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
374 * the last provoking vertex convention.
375 *
376 * Note: since brw_imm_v can only be used in instructions in
377 * packed-word execution mode, and SVBI is a double-word, we need to
378 * first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1),
379 * or (1, 0, 2)) to the destination_indices register, and then add SVBI
380 * using a separate instruction. Also, since the immediate constant is
381 * expressed as packed words, and we need to load double-words into
382 * destination_indices, we need to intersperse zeros to fill the upper
383 * halves of each double-word.
384 */
385 brw_MOV(p, destination_indices_uw,
386 brw_imm_v(0x00020100)); /* (0, 1, 2) */
387 if (num_verts == 3) {
388 /* Get primitive type into temp register. */
389 brw_AND(p, get_element_ud(c->reg.temp, 0),
390 get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
391
392 /* Test if primitive type is TRISTRIP_REVERSE. We need to do this as
393 * an 8-wide comparison so that the conditional MOV that follows
394 * moves all 8 words correctly.
395 */
396 brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
397 get_element_ud(c->reg.temp, 0),
398 brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
399
400 /* If so, then overwrite destination_indices_uw with the appropriate
401 * reordering.
402 */
403 inst = brw_MOV(p, destination_indices_uw,
404 brw_imm_v(key->pv_first ? 0x00010200 /* (0, 2, 1) */
405 : 0x00020001)); /* (1, 0, 2) */
406 brw_inst_set_pred_control(p->devinfo, inst, BRW_PREDICATE_NORMAL);
407 }
408
409 assert(c->reg.destination_indices.width == BRW_EXECUTE_4);
410 brw_push_insn_state(p);
411 brw_set_default_exec_size(p, BRW_EXECUTE_4);
412 brw_ADD(p, c->reg.destination_indices,
413 c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
414 brw_pop_insn_state(p);
415 /* For each vertex, generate code to output each varying using the
416 * appropriate binding table entry.
417 */
418 for (vertex = 0; vertex < num_verts; ++vertex) {
419 /* Set up the correct destination index for this vertex */
420 brw_MOV(p, get_element_ud(c->reg.header, 5),
421 get_element_ud(c->reg.destination_indices, vertex));
422
423 for (binding = 0; binding < key->num_transform_feedback_bindings;
424 ++binding) {
425 unsigned char varying =
426 key->transform_feedback_bindings[binding];
427 unsigned char slot = c->vue_map.varying_to_slot[varying];
428 /* From the Sandybridge PRM, Volume 2, Part 1, Section 4.5.1:
429 *
430 * "Prior to End of Thread with a URB_WRITE, the kernel must
431 * ensure that all writes are complete by sending the final
432 * write as a committed write."
433 */
434 bool final_write =
435 binding == key->num_transform_feedback_bindings - 1 &&
436 vertex == num_verts - 1;
437 struct brw_reg vertex_slot = c->reg.vertex[vertex];
438 vertex_slot.nr += slot / 2;
439 vertex_slot.subnr = (slot % 2) * 16;
440 /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
441 vertex_slot.swizzle = varying == VARYING_SLOT_PSIZ
442 ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
443 brw_set_default_access_mode(p, BRW_ALIGN_16);
444 brw_push_insn_state(p);
445 brw_set_default_exec_size(p, BRW_EXECUTE_4);
446
447 brw_MOV(p, stride(c->reg.header, 4, 4, 1),
448 retype(vertex_slot, BRW_REGISTER_TYPE_UD));
449 brw_pop_insn_state(p);
450
451 brw_set_default_access_mode(p, BRW_ALIGN_1);
452 brw_svb_write(p,
453 final_write ? c->reg.temp : brw_null_reg(), /* dest */
454 1, /* msg_reg_nr */
455 c->reg.header, /* src0 */
456 BRW_GEN6_SOL_BINDING_START + binding, /* binding_table_index */
457 final_write); /* send_commit_msg */
458 }
459 }
460 brw_ENDIF(p);
461
462 /* Now, reinitialize the header register from R0 to restore the parts of
463 * the register that we overwrote while streaming out transform feedback
464 * data.
465 */
466 brw_ff_gs_initialize_header(c);
467
468 /* Finally, wait for the write commit to occur so that we can proceed to
469 * other things safely.
470 *
471 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
472 *
473 * The write commit does not modify the destination register, but
474 * merely clears the dependency associated with the destination
475 * register. Thus, a simple “mov” instruction using the register as a
476 * source is sufficient to wait for the write commit to occur.
477 */
478 brw_MOV(p, c->reg.temp, c->reg.temp);
479 }
480
481 brw_ff_gs_ff_sync(c, 1);
482
483 brw_ff_gs_overwrite_header_dw2_from_r0(c);
484 switch (num_verts) {
485 case 1:
486 brw_ff_gs_offset_header_dw2(c,
487 URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
488 brw_ff_gs_emit_vue(c, c->reg.vertex[0], true);
489 break;
490 case 2:
491 brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
492 brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
493 brw_ff_gs_offset_header_dw2(c,
494 URB_WRITE_PRIM_END - URB_WRITE_PRIM_START);
495 brw_ff_gs_emit_vue(c, c->reg.vertex[1], true);
496 break;
497 case 3:
498 if (check_edge_flags) {
499 /* Only emit vertices 0 and 1 if this is the first triangle of the
500 * polygon. Otherwise they are redundant.
501 */
502 brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
503 get_element_ud(c->reg.R0, 2),
504 brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
505 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
506 brw_IF(p, BRW_EXECUTE_1);
507 }
508 brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
509 brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
510 brw_ff_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
511 brw_ff_gs_emit_vue(c, c->reg.vertex[1], false);
512 if (check_edge_flags) {
513 brw_ENDIF(p);
514 /* Only emit vertex 2 in PRIM_END mode if this is the last triangle
515 * of the polygon. Otherwise leave the primitive incomplete because
516 * there are more polygon vertices coming.
517 */
518 brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
519 get_element_ud(c->reg.R0, 2),
520 brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
521 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
522 brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
523 }
524 brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
525 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
526 brw_ff_gs_emit_vue(c, c->reg.vertex[2], true);
527 break;
528 }
529 }
530