1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23 #include "main/mtypes.h"
24
25 #include "isl/isl.h"
26
27 #include "brw_context.h"
28 #include "brw_state.h"
29 #include "brw_defines.h"
30
31 enum isl_format
brw_isl_format_for_mesa_format(mesa_format mesa_format)32 brw_isl_format_for_mesa_format(mesa_format mesa_format)
33 {
34 /* This table is ordered according to the enum ordering in formats.h. We do
35 * expect that enum to be extended without our explicit initialization
36 * staying in sync, so we initialize to 0 even though
37 * ISL_FORMAT_R32G32B32A32_FLOAT happens to also be 0.
38 */
39 static const enum isl_format table[MESA_FORMAT_COUNT] = {
40 [0 ... MESA_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED,
41
42 [MESA_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,
43 [MESA_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,
44 [MESA_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,
45 [MESA_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,
46 [MESA_FORMAT_RGB_UNORM8] = ISL_FORMAT_R8G8B8_UNORM,
47 [MESA_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,
48 [MESA_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,
49 [MESA_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,
50 [MESA_FORMAT_L8A8_UNORM] = ISL_FORMAT_L8A8_UNORM,
51 [MESA_FORMAT_L16A16_UNORM] = ISL_FORMAT_L16A16_UNORM,
52 [MESA_FORMAT_A_UNORM8] = ISL_FORMAT_A8_UNORM,
53 [MESA_FORMAT_A_UNORM16] = ISL_FORMAT_A16_UNORM,
54 [MESA_FORMAT_L_UNORM8] = ISL_FORMAT_L8_UNORM,
55 [MESA_FORMAT_L_UNORM16] = ISL_FORMAT_L16_UNORM,
56 [MESA_FORMAT_I_UNORM8] = ISL_FORMAT_I8_UNORM,
57 [MESA_FORMAT_I_UNORM16] = ISL_FORMAT_I16_UNORM,
58 [MESA_FORMAT_YCBCR_REV] = ISL_FORMAT_YCRCB_NORMAL,
59 [MESA_FORMAT_YCBCR] = ISL_FORMAT_YCRCB_SWAPUVY,
60 [MESA_FORMAT_R_UNORM8] = ISL_FORMAT_R8_UNORM,
61 [MESA_FORMAT_R8G8_UNORM] = ISL_FORMAT_R8G8_UNORM,
62 [MESA_FORMAT_R_UNORM16] = ISL_FORMAT_R16_UNORM,
63 [MESA_FORMAT_R16G16_UNORM] = ISL_FORMAT_R16G16_UNORM,
64 [MESA_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,
65 [MESA_FORMAT_S_UINT8] = ISL_FORMAT_R8_UINT,
66
67 [MESA_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
68 [MESA_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
69 [MESA_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
70 [MESA_FORMAT_L_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
71 [MESA_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
72 [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
73 [MESA_FORMAT_SRGBA_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
74 [MESA_FORMAT_SRGBA_DXT3] = ISL_FORMAT_BC2_UNORM_SRGB,
75 [MESA_FORMAT_SRGBA_DXT5] = ISL_FORMAT_BC3_UNORM_SRGB,
76
77 [MESA_FORMAT_RGB_FXT1] = ISL_FORMAT_FXT1,
78 [MESA_FORMAT_RGBA_FXT1] = ISL_FORMAT_FXT1,
79 [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_BC1_UNORM,
80 [MESA_FORMAT_RGBA_DXT1] = ISL_FORMAT_BC1_UNORM,
81 [MESA_FORMAT_RGBA_DXT3] = ISL_FORMAT_BC2_UNORM,
82 [MESA_FORMAT_RGBA_DXT5] = ISL_FORMAT_BC3_UNORM,
83
84 [MESA_FORMAT_RGBA_FLOAT32] = ISL_FORMAT_R32G32B32A32_FLOAT,
85 [MESA_FORMAT_RGBA_FLOAT16] = ISL_FORMAT_R16G16B16A16_FLOAT,
86 [MESA_FORMAT_RGB_FLOAT32] = ISL_FORMAT_R32G32B32_FLOAT,
87 [MESA_FORMAT_A_FLOAT32] = ISL_FORMAT_A32_FLOAT,
88 [MESA_FORMAT_A_FLOAT16] = ISL_FORMAT_A16_FLOAT,
89 [MESA_FORMAT_L_FLOAT32] = ISL_FORMAT_L32_FLOAT,
90 [MESA_FORMAT_L_FLOAT16] = ISL_FORMAT_L16_FLOAT,
91 [MESA_FORMAT_LA_FLOAT32] = ISL_FORMAT_L32A32_FLOAT,
92 [MESA_FORMAT_LA_FLOAT16] = ISL_FORMAT_L16A16_FLOAT,
93 [MESA_FORMAT_I_FLOAT32] = ISL_FORMAT_I32_FLOAT,
94 [MESA_FORMAT_I_FLOAT16] = ISL_FORMAT_I16_FLOAT,
95 [MESA_FORMAT_R_FLOAT32] = ISL_FORMAT_R32_FLOAT,
96 [MESA_FORMAT_R_FLOAT16] = ISL_FORMAT_R16_FLOAT,
97 [MESA_FORMAT_RG_FLOAT32] = ISL_FORMAT_R32G32_FLOAT,
98 [MESA_FORMAT_RG_FLOAT16] = ISL_FORMAT_R16G16_FLOAT,
99
100 [MESA_FORMAT_R_SINT8] = ISL_FORMAT_R8_SINT,
101 [MESA_FORMAT_RG_SINT8] = ISL_FORMAT_R8G8_SINT,
102 [MESA_FORMAT_RGB_SINT8] = ISL_FORMAT_R8G8B8_SINT,
103 [MESA_FORMAT_RGBA_SINT8] = ISL_FORMAT_R8G8B8A8_SINT,
104 [MESA_FORMAT_R_SINT16] = ISL_FORMAT_R16_SINT,
105 [MESA_FORMAT_RG_SINT16] = ISL_FORMAT_R16G16_SINT,
106 [MESA_FORMAT_RGB_SINT16] = ISL_FORMAT_R16G16B16_SINT,
107 [MESA_FORMAT_RGBA_SINT16] = ISL_FORMAT_R16G16B16A16_SINT,
108 [MESA_FORMAT_R_SINT32] = ISL_FORMAT_R32_SINT,
109 [MESA_FORMAT_RG_SINT32] = ISL_FORMAT_R32G32_SINT,
110 [MESA_FORMAT_RGB_SINT32] = ISL_FORMAT_R32G32B32_SINT,
111 [MESA_FORMAT_RGBA_SINT32] = ISL_FORMAT_R32G32B32A32_SINT,
112
113 [MESA_FORMAT_R_UINT8] = ISL_FORMAT_R8_UINT,
114 [MESA_FORMAT_RG_UINT8] = ISL_FORMAT_R8G8_UINT,
115 [MESA_FORMAT_RGB_UINT8] = ISL_FORMAT_R8G8B8_UINT,
116 [MESA_FORMAT_RGBA_UINT8] = ISL_FORMAT_R8G8B8A8_UINT,
117 [MESA_FORMAT_R_UINT16] = ISL_FORMAT_R16_UINT,
118 [MESA_FORMAT_RG_UINT16] = ISL_FORMAT_R16G16_UINT,
119 [MESA_FORMAT_RGB_UINT16] = ISL_FORMAT_R16G16B16_UINT,
120 [MESA_FORMAT_RGBA_UINT16] = ISL_FORMAT_R16G16B16A16_UINT,
121 [MESA_FORMAT_R_UINT32] = ISL_FORMAT_R32_UINT,
122 [MESA_FORMAT_RG_UINT32] = ISL_FORMAT_R32G32_UINT,
123 [MESA_FORMAT_RGB_UINT32] = ISL_FORMAT_R32G32B32_UINT,
124 [MESA_FORMAT_RGBA_UINT32] = ISL_FORMAT_R32G32B32A32_UINT,
125
126 [MESA_FORMAT_R_SNORM8] = ISL_FORMAT_R8_SNORM,
127 [MESA_FORMAT_R8G8_SNORM] = ISL_FORMAT_R8G8_SNORM,
128 [MESA_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,
129 [MESA_FORMAT_R_SNORM16] = ISL_FORMAT_R16_SNORM,
130 [MESA_FORMAT_R16G16_SNORM] = ISL_FORMAT_R16G16_SNORM,
131 [MESA_FORMAT_RGB_SNORM16] = ISL_FORMAT_R16G16B16_SNORM,
132 [MESA_FORMAT_RGBA_SNORM16] = ISL_FORMAT_R16G16B16A16_SNORM,
133 [MESA_FORMAT_RGBA_UNORM16] = ISL_FORMAT_R16G16B16A16_UNORM,
134
135 [MESA_FORMAT_R_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,
136 [MESA_FORMAT_R_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,
137 [MESA_FORMAT_RG_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,
138 [MESA_FORMAT_RG_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,
139
140 [MESA_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,
141 [MESA_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,
142 [MESA_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,
143 [MESA_FORMAT_ETC2_RGBA8_EAC] = ISL_FORMAT_ETC2_EAC_RGBA8,
144 [MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,
145 [MESA_FORMAT_ETC2_R11_EAC] = ISL_FORMAT_EAC_R11,
146 [MESA_FORMAT_ETC2_RG11_EAC] = ISL_FORMAT_EAC_RG11,
147 [MESA_FORMAT_ETC2_SIGNED_R11_EAC] = ISL_FORMAT_EAC_SIGNED_R11,
148 [MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = ISL_FORMAT_EAC_SIGNED_RG11,
149 [MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_RGB8_PTA,
150 [MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_SRGB8_PTA,
151
152 [MESA_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,
153 [MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM] = ISL_FORMAT_BC7_UNORM_SRGB,
154 [MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT] = ISL_FORMAT_BC6H_SF16,
155 [MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT] = ISL_FORMAT_BC6H_UF16,
156
157 [MESA_FORMAT_RGBA_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,
158 [MESA_FORMAT_RGBA_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,
159 [MESA_FORMAT_RGBA_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,
160 [MESA_FORMAT_RGBA_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,
161 [MESA_FORMAT_RGBA_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,
162 [MESA_FORMAT_RGBA_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,
163 [MESA_FORMAT_RGBA_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,
164 [MESA_FORMAT_RGBA_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,
165 [MESA_FORMAT_RGBA_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,
166 [MESA_FORMAT_RGBA_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,
167 [MESA_FORMAT_RGBA_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,
168 [MESA_FORMAT_RGBA_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,
169 [MESA_FORMAT_RGBA_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,
170 [MESA_FORMAT_RGBA_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,
171 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,
172 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,
173 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,
174 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
175 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,
176 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,
177 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,
178 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,
179 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,
180 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,
181 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,
182 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,
183 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,
184 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,
185
186 [MESA_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,
187 [MESA_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,
188
189 [MESA_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,
190 [MESA_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,
191 [MESA_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,
192
193 [MESA_FORMAT_B5G5R5X1_UNORM] = ISL_FORMAT_B5G5R5X1_UNORM,
194 [MESA_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,
195 [MESA_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,
196 [MESA_FORMAT_RGBX_UNORM16] = ISL_FORMAT_R16G16B16X16_UNORM,
197 [MESA_FORMAT_RGBX_FLOAT16] = ISL_FORMAT_R16G16B16X16_FLOAT,
198 [MESA_FORMAT_RGBX_FLOAT32] = ISL_FORMAT_R32G32B32X32_FLOAT,
199 };
200
201 assert(mesa_format < MESA_FORMAT_COUNT);
202 return table[mesa_format];
203 }
204
205 void
intel_screen_init_surface_formats(struct intel_screen * screen)206 intel_screen_init_surface_formats(struct intel_screen *screen)
207 {
208 const struct gen_device_info *devinfo = &screen->devinfo;
209 mesa_format format;
210
211 memset(&screen->mesa_format_supports_texture, 0,
212 sizeof(screen->mesa_format_supports_texture));
213
214 int gen = devinfo->gen * 10;
215 if (devinfo->is_g4x || devinfo->is_haswell)
216 gen += 5;
217
218 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
219 enum isl_format texture, render;
220 bool is_integer = _mesa_is_format_integer_color(format);
221
222 render = texture = brw_isl_format_for_mesa_format(format);
223
224 if (texture == ISL_FORMAT_UNSUPPORTED)
225 continue;
226
227 /* Don't advertise 8 and 16-bit RGB formats to core mesa. This ensures
228 * that they are renderable from an API perspective since core mesa will
229 * fall back to RGBA or RGBX (we can't render to non-power-of-two
230 * formats). For 8-bit, formats, this also keeps us from hitting some
231 * nasty corners in intel_miptree_map_blit if you ever try to map one.
232 */
233 int format_size = _mesa_get_format_bytes(format);
234 if (format_size == 3 || format_size == 6)
235 continue;
236
237 if (isl_format_supports_sampling(devinfo, texture) &&
238 (isl_format_supports_filtering(devinfo, texture) || is_integer))
239 screen->mesa_format_supports_texture[format] = true;
240
241 /* Re-map some render target formats to make them supported when they
242 * wouldn't be using their format for texturing.
243 */
244 switch (render) {
245 /* For these formats, we just need to read/write the first
246 * channel into R, which is to say that we just treat them as
247 * GL_RED.
248 */
249 case ISL_FORMAT_I32_FLOAT:
250 case ISL_FORMAT_L32_FLOAT:
251 render = ISL_FORMAT_R32_FLOAT;
252 break;
253 case ISL_FORMAT_I16_FLOAT:
254 case ISL_FORMAT_L16_FLOAT:
255 render = ISL_FORMAT_R16_FLOAT;
256 break;
257 case ISL_FORMAT_I8_UNORM:
258 case ISL_FORMAT_L8_UNORM:
259 render = ISL_FORMAT_R8_UNORM;
260 break;
261 case ISL_FORMAT_I16_UNORM:
262 case ISL_FORMAT_L16_UNORM:
263 render = ISL_FORMAT_R16_UNORM;
264 break;
265 case ISL_FORMAT_R16G16B16X16_UNORM:
266 render = ISL_FORMAT_R16G16B16A16_UNORM;
267 break;
268 case ISL_FORMAT_R16G16B16X16_FLOAT:
269 render = ISL_FORMAT_R16G16B16A16_FLOAT;
270 break;
271 case ISL_FORMAT_B8G8R8X8_UNORM:
272 /* XRGB is handled as ARGB because the chips in this family
273 * cannot render to XRGB targets. This means that we have to
274 * mask writes to alpha (ala glColorMask) and reconfigure the
275 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
276 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
277 * used. On Gen8+ BGRX is actually allowed (but not RGBX).
278 */
279 if (!isl_format_supports_rendering(devinfo, texture))
280 render = ISL_FORMAT_B8G8R8A8_UNORM;
281 break;
282 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB:
283 if (!isl_format_supports_rendering(devinfo, texture))
284 render = ISL_FORMAT_B8G8R8A8_UNORM_SRGB;
285 break;
286 case ISL_FORMAT_R8G8B8X8_UNORM:
287 render = ISL_FORMAT_R8G8B8A8_UNORM;
288 break;
289 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB:
290 render = ISL_FORMAT_R8G8B8A8_UNORM_SRGB;
291 break;
292 default:
293 break;
294 }
295
296 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
297 * integer, so we don't need hardware support for blending on it. Other
298 * than that, GL in general requires alpha blending for render targets,
299 * even though we don't support it for some formats.
300 */
301 if (isl_format_supports_rendering(devinfo, render) &&
302 (isl_format_supports_alpha_blending(devinfo, render) || is_integer)) {
303 screen->mesa_to_isl_render_format[format] = render;
304 screen->mesa_format_supports_render[format] = true;
305 }
306 }
307
308 /* We will check this table for FBO completeness, but the surface format
309 * table above only covered color rendering.
310 */
311 screen->mesa_format_supports_render[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
312 screen->mesa_format_supports_render[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
313 screen->mesa_format_supports_render[MESA_FORMAT_S_UINT8] = true;
314 screen->mesa_format_supports_render[MESA_FORMAT_Z_FLOAT32] = true;
315 screen->mesa_format_supports_render[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
316 if (gen >= 80)
317 screen->mesa_format_supports_render[MESA_FORMAT_Z_UNORM16] = true;
318
319 /* We remap depth formats to a supported texturing format in
320 * translate_tex_format().
321 */
322 screen->mesa_format_supports_texture[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
323 screen->mesa_format_supports_texture[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
324 screen->mesa_format_supports_texture[MESA_FORMAT_Z_FLOAT32] = true;
325 screen->mesa_format_supports_texture[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
326 screen->mesa_format_supports_texture[MESA_FORMAT_S_UINT8] = true;
327
328 /* Benchmarking shows that Z16 is slower than Z24, so there's no reason to
329 * use it unless you're under memory (not memory bandwidth) pressure.
330 *
331 * Apparently, the GPU's depth scoreboarding works on a 32-bit granularity,
332 * which corresponds to one pixel in the depth buffer for Z24 or Z32 formats.
333 * However, it corresponds to two pixels with Z16, which means both need to
334 * hit the early depth case in order for it to happen.
335 *
336 * Other speculation is that we may be hitting increased fragment shader
337 * execution from GL_LEQUAL/GL_EQUAL depth tests at reduced precision.
338 *
339 * With the PMA stall workaround in place, Z16 is faster than Z24, as it
340 * should be.
341 */
342 if (gen >= 80)
343 screen->mesa_format_supports_texture[MESA_FORMAT_Z_UNORM16] = true;
344
345 /* The RGBX formats are not renderable. Normally these get mapped
346 * internally to RGBA formats when rendering. However on Gen9+ when this
347 * internal override is used fast clears don't work so they are disabled in
348 * brw_meta_fast_clear. To avoid this problem we can just pretend not to
349 * support RGBX formats at all. This will cause the upper layers of Mesa to
350 * pick the RGBA formats instead. This works fine because when it is used
351 * as a texture source the swizzle state is programmed to force the alpha
352 * channel to 1.0 anyway. We could also do this for all gens except that
353 * it's a bit more difficult when the hardware doesn't support texture
354 * swizzling. Gens using the blorp have further problems because that
355 * doesn't implement this swizzle override. We don't need to do this for
356 * BGRX because that actually is supported natively on Gen8+.
357 */
358 if (gen >= 90) {
359 static const mesa_format rgbx_formats[] = {
360 MESA_FORMAT_R8G8B8X8_UNORM,
361 MESA_FORMAT_R8G8B8X8_SRGB,
362 MESA_FORMAT_RGBX_UNORM16,
363 MESA_FORMAT_RGBX_FLOAT16,
364 MESA_FORMAT_RGBX_FLOAT32
365 };
366
367 for (int i = 0; i < ARRAY_SIZE(rgbx_formats); i++) {
368 screen->mesa_format_supports_texture[rgbx_formats[i]] = false;
369 screen->mesa_format_supports_render[rgbx_formats[i]] = false;
370 }
371 }
372
373 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
374 * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
375 */
376 screen->mesa_format_supports_texture[MESA_FORMAT_ETC1_RGB8] = true;
377
378 /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
379 * MESA_FORMAT during glCompressedTexImage2D().
380 * See intel_mipmap_tree::wraps_etc2.
381 */
382 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGB8] = true;
383 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8] = true;
384 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
385 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
386 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_R11_EAC] = true;
387 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RG11_EAC] = true;
388 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
389 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
390 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
391 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
392 }
393
394 void
brw_init_surface_formats(struct brw_context * brw)395 brw_init_surface_formats(struct brw_context *brw)
396 {
397 struct intel_screen *screen = brw->screen;
398 struct gl_context *ctx = &brw->ctx;
399
400 brw->mesa_format_supports_render = screen->mesa_format_supports_render;
401 brw->mesa_to_isl_render_format = screen->mesa_to_isl_render_format;
402
403 STATIC_ASSERT(ARRAY_SIZE(ctx->TextureFormatSupported) ==
404 ARRAY_SIZE(screen->mesa_format_supports_texture));
405
406 for (unsigned i = 0; i < ARRAY_SIZE(ctx->TextureFormatSupported); ++i) {
407 ctx->TextureFormatSupported[i] = screen->mesa_format_supports_texture[i];
408 }
409 }
410
411 bool
brw_render_target_supported(struct brw_context * brw,struct gl_renderbuffer * rb)412 brw_render_target_supported(struct brw_context *brw,
413 struct gl_renderbuffer *rb)
414 {
415 const struct gen_device_info *devinfo = &brw->screen->devinfo;
416 mesa_format format = rb->Format;
417
418 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
419 * we would consider them renderable even though we don't have surface
420 * support for their alpha behavior and don't have the blending unit
421 * available to fake it like we do for XRGB8888. Force them to being
422 * unsupported.
423 */
424 if (_mesa_is_format_integer_color(format) &&
425 rb->_BaseFormat != GL_RGBA &&
426 rb->_BaseFormat != GL_RG &&
427 rb->_BaseFormat != GL_RED)
428 return false;
429
430 /* Under some conditions, MSAA is not supported for formats whose width is
431 * more than 64 bits.
432 */
433 if (devinfo->gen < 8 &&
434 rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
435 /* Gen6: MSAA on >64 bit formats is unsupported. */
436 if (devinfo->gen <= 6)
437 return false;
438
439 /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
440 if (rb->NumSamples >= 8)
441 return false;
442 }
443
444 return brw->mesa_format_supports_render[format];
445 }
446
447 enum isl_format
translate_tex_format(struct brw_context * brw,mesa_format mesa_format,GLenum srgb_decode)448 translate_tex_format(struct brw_context *brw,
449 mesa_format mesa_format,
450 GLenum srgb_decode)
451 {
452 struct gl_context *ctx = &brw->ctx;
453 if (srgb_decode == GL_SKIP_DECODE_EXT)
454 mesa_format = _mesa_get_srgb_format_linear(mesa_format);
455
456 switch( mesa_format ) {
457
458 case MESA_FORMAT_Z_UNORM16:
459 return ISL_FORMAT_R16_UNORM;
460
461 case MESA_FORMAT_Z24_UNORM_S8_UINT:
462 case MESA_FORMAT_Z24_UNORM_X8_UINT:
463 return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
464
465 case MESA_FORMAT_Z_FLOAT32:
466 return ISL_FORMAT_R32_FLOAT;
467
468 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
469 return ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS;
470
471 case MESA_FORMAT_RGBA_FLOAT32:
472 /* The value of this ISL surface format is 0, which tricks the
473 * assertion below.
474 */
475 return ISL_FORMAT_R32G32B32A32_FLOAT;
476
477 case MESA_FORMAT_RGBA_ASTC_4x4:
478 case MESA_FORMAT_RGBA_ASTC_5x4:
479 case MESA_FORMAT_RGBA_ASTC_5x5:
480 case MESA_FORMAT_RGBA_ASTC_6x5:
481 case MESA_FORMAT_RGBA_ASTC_6x6:
482 case MESA_FORMAT_RGBA_ASTC_8x5:
483 case MESA_FORMAT_RGBA_ASTC_8x6:
484 case MESA_FORMAT_RGBA_ASTC_8x8:
485 case MESA_FORMAT_RGBA_ASTC_10x5:
486 case MESA_FORMAT_RGBA_ASTC_10x6:
487 case MESA_FORMAT_RGBA_ASTC_10x8:
488 case MESA_FORMAT_RGBA_ASTC_10x10:
489 case MESA_FORMAT_RGBA_ASTC_12x10:
490 case MESA_FORMAT_RGBA_ASTC_12x12: {
491 enum isl_format isl_fmt =
492 brw_isl_format_for_mesa_format(mesa_format);
493
494 /**
495 * It is possible to process these formats using the LDR Profile
496 * or the Full Profile mode of the hardware. Because, it isn't
497 * possible to determine if an HDR or LDR texture is being rendered, we
498 * can't determine which mode to enable in the hardware. Therefore, to
499 * handle all cases, always default to Full profile unless we are
500 * processing sRGBs, which are incompatible with this mode.
501 */
502 if (ctx->Extensions.KHR_texture_compression_astc_hdr)
503 isl_fmt |= GEN9_SURFACE_ASTC_HDR_FORMAT_BIT;
504
505 return isl_fmt;
506 }
507
508 default:
509 return brw_isl_format_for_mesa_format(mesa_format);
510 }
511 }
512
513 /**
514 * Convert a MESA_FORMAT to the corresponding BRW_DEPTHFORMAT enum.
515 */
516 uint32_t
brw_depth_format(struct brw_context * brw,mesa_format format)517 brw_depth_format(struct brw_context *brw, mesa_format format)
518 {
519 const struct gen_device_info *devinfo = &brw->screen->devinfo;
520
521 switch (format) {
522 case MESA_FORMAT_Z_UNORM16:
523 return BRW_DEPTHFORMAT_D16_UNORM;
524 case MESA_FORMAT_Z_FLOAT32:
525 return BRW_DEPTHFORMAT_D32_FLOAT;
526 case MESA_FORMAT_Z24_UNORM_X8_UINT:
527 if (devinfo->gen >= 6) {
528 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
529 } else {
530 /* Use D24_UNORM_S8, not D24_UNORM_X8.
531 *
532 * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
533 * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
534 * 3DSTATE_DEPTH_BUFFER.Surface_Format).
535 *
536 * However, on Gen5, D24_UNORM_X8 may be used only if separate
537 * stencil is enabled, and we never enable it. From the Ironlake PRM,
538 * same section as above, 3DSTATE_DEPTH_BUFFER's
539 * "Separate Stencil Buffer Enable" bit:
540 *
541 * "If this field is disabled, the Surface Format of the depth
542 * buffer cannot be D24_UNORM_X8_UINT."
543 */
544 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
545 }
546 case MESA_FORMAT_Z24_UNORM_S8_UINT:
547 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
548 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
549 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT;
550 default:
551 unreachable("Unexpected depth format.");
552 }
553 }
554