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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Flex CAN Memory Map
4  *
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8 
9 #ifndef __FLEXCAN_H__
10 #define __FLEXCAN_H__
11 
12 /* FlexCan Message Buffer */
13 typedef struct can_msgbuf_ctrl {
14 #ifdef CONFIG_M5282
15 	u8 tmstamp;		/* 0x00 Timestamp */
16 	u8 ctrl;		/* 0x01 Control */
17 	u16 idh;		/* 0x02 ID High */
18 	u16 idl;		/* 0x04 ID High */
19 	u8 data[8];		/* 0x06 8 Byte Data Field */
20 	u16 res;		/* 0x0E */
21 #else
22 	u16 ctrl;		/* 0x00 Control/Status */
23 	u16 tmstamp;		/* 0x02 Timestamp */
24 	u32 id;			/* 0x04 Identifier */
25 	u8 data[8];		/* 0x08 8 Byte Data Field */
26 #endif
27 } can_msg_t;
28 
29 #ifdef CONFIG_M5282
30 /* MSGBUF CTRL */
31 #define CAN_MSGBUF_CTRL_CODE(x)		(((x) & 0x0F) << 4)
32 #define CAN_MSGBUF_CTRL_CODE_MASK	(0x0F)
33 #define CAN_MSGBUF_CTRL_LEN(x)		((x) & 0x0F)
34 #define CAN_MSGBUF_CTRL_LEN_MASK	(0xF0)
35 
36 /* MSGBUF ID */
37 #define CAN_MSGBUF_IDH_STD(x)		(((x) & 0x07FF) << 5)
38 #define CAN_MSGBUF_IDH_STD_MASK		(0xE003FFFF)
39 #define CAN_MSGBUF_IDH_SRR		(0x0010)
40 #define CAN_MSGBUF_IDH_IDE		(0x0080)
41 #define CAN_MSGBUF_IDH_EXTH(x)		((x) & 0x07)
42 #define CAN_MSGBUF_IDH_EXTH_MASK	(0xFFF8)
43 #define CAN_MSGBUF_IDL_EXTL(x)		(((x) & 0x7FFF) << 1)
44 #define CAN_MSGBUF_IDL_EXTL_MASK		(0xFFFE)
45 #define CAN_MSGBUF_IDL_RTR		(0x0001)
46 #else
47 /* MSGBUF CTRL */
48 #define CAN_MSGBUF_CTRL_CODE(x)		(((x) & 0x000F) << 8)
49 #define CAN_MSGBUF_CTRL_CODE_MASK	(0xF0FF)
50 #define CAN_MSGBUF_CTRL_SRR		(0x0040)
51 #define CAN_MSGBUF_CTRL_IDE		(0x0020)
52 #define CAN_MSGBUF_CTRL_RTR		(0x0010)
53 #define CAN_MSGBUF_CTRL_LEN(x)		((x) & 0x000F)
54 #define CAN_MSGBUF_CTRL_LEN_MASK	(0xFFF0)
55 
56 /* MSGBUF ID */
57 #define CAN_MSGBUF_ID_STD(x)		(((x) & 0x000007FF) << 18)
58 #define CAN_MSGBUF_ID_STD_MASK		(0xE003FFFF)
59 #define CAN_MSGBUF_ID_EXT(x)		((x) & 0x0003FFFF)
60 #define CAN_MSGBUF_ID_EXT_MASK		(0xFFFC0000)
61 #endif
62 
63 /* FlexCan module */
64 typedef struct can_ctrl {
65 	u32 mcr;		/* 0x00 Module Configuration */
66 	u32 ctrl;		/* 0x04 Control */
67 	u32 timer;		/* 0x08 Free Running Timer */
68 	u32 res1;		/* 0x0C */
69 	u32 rxgmsk;		/* 0x10 Rx Global Mask */
70 	u32 rx14msk;		/* 0x14 RxBuffer 14 Mask */
71 	u32 rx15msk;		/* 0x18 RxBuffer 15 Mask */
72 #ifdef CONFIG_M5282
73 	u32 res2;		/* 0x1C */
74 	u16 errstat;		/* 0x20 Error and status */
75 	u16 imsk;		/* 0x22 Interrupt Mask */
76 	u16 iflag;		/* 0x24 Interrupt Flag */
77 	u16 errcnt;		/* 0x26 Error Counter */
78 	u32 res3[3];		/* 0x28 - 0x33 */
79 #else
80 	u16 res2;		/* 0x1C */
81 	u16 errcnt;		/* 0x1E Error Counter */
82 	u16 res3;		/* 0x20 */
83 	u16 errstat;		/* 0x22 Error and status */
84 	u32 res4;		/* 0x24 */
85 	u32 imsk;		/* 0x28 Interrupt Mask */
86 	u32 res5;		/* 0x2C */
87 	u16 iflag;		/* 0x30 Interrupt Flag */
88 #endif
89 	u32 res6[19];		/* 0x34 - 0x7F */
90 	void *msgbuf;		/* 0x80 Message Buffer 0-15 */
91 } can_t;
92 
93 /* MCR */
94 #define CAN_MCR_MDIS			(0x80000000)
95 #define CAN_MCR_FRZ			(0x40000000)
96 #define CAN_MCR_HALT			(0x10000000)
97 #define CAN_MCR_NORDY			(0x08000000)
98 #define CAN_MCF_WAKEMSK			(0x04000000)	/* 5282 */
99 #define CAN_MCR_SOFTRST			(0x02000000)
100 #define CAN_MCR_FRZACK			(0x01000000)
101 #define CAN_MCR_SUPV			(0x00800000)
102 #define CAN_MCR_SELFWAKE		(0x00400000)	/* 5282 */
103 #define CAN_MCR_APS			(0x00200000)	/* 5282 */
104 #define CAN_MCR_LPMACK			(0x00100000)
105 #define CAN_MCF_BCC			(0x00010000)
106 #define CAN_MCR_MAXMB(x)		((x) & 0x0F)
107 #define CAN_MCR_MAXMB_MASK		(0xFFFFFFF0)
108 
109 /* CTRL */
110 #define CAN_CTRL_PRESDIV(x)		(((x) & 0xFF) << 24)
111 #define CAN_CTRL_PRESDIV_MASK		(0x00FFFFFF)
112 #define CAN_CTRL_RJW(x)			(((x) & 0x03) << 22)
113 #define CAN_CTRL_RJW_MASK		(0xFF3FFFFF)
114 #define CAN_CTRL_PSEG1(x)		(((x) & 0x07) << 19)
115 #define CAN_CTRL_PSEG1_MASK		(0xFFC7FFFF)
116 #define CAN_CTRL_PSEG2(x)		(((x) & 0x07) << 16)
117 #define CAN_CTRL_PSEG2_MASK		(0xFFF8FFFF)
118 #define CAN_CTRL_BOFFMSK		(0x00008000)
119 #define CAN_CTRL_ERRMSK			(0x00004000)
120 #define CAN_CTRL_CLKSRC			(0x00002000)
121 #define CAN_CTRL_LPB			(0x00001000)
122 #define CAN_CTRL_RXMODE			(0x00000400)	/* 5282 */
123 #define CAN_CTRL_TXMODE(x)		(((x) & 0x03) << 8)	/* 5282 */
124 #define CAN_CTRL_TXMODE_MASK		(0xFFFFFCFF)	/* 5282 */
125 #define CAN_CTRL_TXMODE_CAN0		(0x00000000)	/* 5282 */
126 #define CAN_CTRL_TXMODE_CAN1		(0x00000100)	/* 5282 */
127 #define CAN_CTRL_TXMODE_OPEN		(0x00000200)	/* 5282 */
128 #define CAN_CTRL_SMP			(0x00000080)
129 #define CAN_CTRL_BOFFREC		(0x00000040)
130 #define CAN_CTRL_TSYNC			(0x00000020)
131 #define CAN_CTRL_LBUF			(0x00000010)
132 #define CAN_CTRL_LOM			(0x00000008)
133 #define CAN_CTRL_PROPSEG(x)		((x) & 0x07)
134 #define CAN_CTRL_PROPSEG_MASK		(0xFFFFFFF8)
135 
136 /* TIMER */
137 /* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
138 #define CAN_TIMER(x)			((x) & 0xFFFF)
139 #define CAN_TIMER_MASK			(0xFFFF0000)
140 
141 /* RXGMASK */
142 #ifdef CONFIG_M5282
143 #define CAN_RXGMSK_MI_STD(x)		(((x) & 0x000007FF) << 21)
144 #define CAN_RXGMSK_MI_STD_MASK		(0x001FFFFF)
145 #define CAN_RXGMSK_MI_EXT(x)		(((x) & 0x0003FFFF) << 1)
146 #define CAN_RXGMSK_MI_EXT_MASK		(0xFFF80001)
147 #else
148 #define CAN_RXGMSK_MI_STD(x)		(((x) & 0x000007FF) << 18)
149 #define CAN_RXGMSK_MI_STD_MASK		(0xE003FFFF)
150 #define CAN_RXGMSK_MI_EXT(x)		((x) & 0x0003FFFF)
151 #define CAN_RXGMSK_MI_EXT_MASK		(0xFFFC0000)
152 #endif
153 
154 /* ERRCNT */
155 #define CAN_ERRCNT_RXECTR(x)		(((x) & 0xFF) << 8)
156 #define CAN_ERRCNT_RXECTR_MASK		(0x00FF)
157 #define CAN_ERRCNT_TXECTR(x)		((x) & 0xFF)
158 #define CAN_ERRCNT_TXECTR_MASK		(0xFF00)
159 
160 /* ERRSTAT */
161 #define CAN_ERRSTAT_BITERR1		(0x8000)
162 #define CAN_ERRSTAT_BITERR0		(0x4000)
163 #define CAN_ERRSTAT_ACKERR		(0x2000)
164 #define CAN_ERRSTAT_CRCERR		(0x1000)
165 #define CAN_ERRSTAT_FRMERR		(0x0800)
166 #define CAN_ERRSTAT_STFERR		(0x0400)
167 #define CAN_ERRSTAT_TXWRN		(0x0200)
168 #define CAN_ERRSTAT_RXWRN		(0x0100)
169 #define CAN_ERRSTAT_IDLE		(0x0080)
170 #define CAN_ERRSTAT_TXRX		(0x0040)
171 #define CAN_ERRSTAT_FLT_MASK		(0xFFCF)
172 #define CAN_ERRSTAT_FLT_BUSOFF		(0x0020)
173 #define CAN_ERRSTAT_FLT_PASSIVE		(0x0010)
174 #define CAN_ERRSTAT_FLT_ACTIVE		(0x0000)
175 #ifdef CONFIG_M5282
176 #define CAN_ERRSTAT_BOFFINT		(0x0004)
177 #define CAN_ERRSTAT_ERRINT		(0x0002)
178 #else
179 #define CAN_ERRSTAT_ERRINT		(0x0004)
180 #define CAN_ERRSTAT_BOFFINT		(0x0002)
181 #define CAN_ERRSTAT_WAKEINT		(0x0001)
182 #endif
183 
184 /* IMASK */
185 #ifdef CONFIG_M5253
186 #define CAN_IMASK_BUFnM(x)		(1 << (x & 0xFFFFFFFF))
187 #define CAN_IMASK_BUFnM_MASKBIT(x)	~CAN_IMASK_BUFnM(x)
188 #else
189 #define CAN_IMASK_BUFnM(x)		(1 << (x & 0xFFFF))
190 #define CAN_IMASK_BUFnM_MASKBIT(x)	~CAN_IMASK_BUFnM(x)
191 #endif
192 
193 /* IFLAG */
194 #ifdef CONFIG_M5253
195 #define CAN_IFLAG_BUFnM(x)		(1 << (x & 0xFFFFFFFF))
196 #define CAN_IFLAG_BUFnM_MASKBIT(x)	~CAN_IFLAG_BUFnM(x)
197 #else
198 #define CAN_IFLAG_BUFnM(x)		(1 << (x & 0xFFFF))
199 #define CAN_IFLAG_BUFnM_MASKBIT(x)	~CAN_IFLAG_BUFnM(x)
200 #endif
201 
202 #endif				/* __FLEXCAN_H__ */
203