1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <cpu.h>
8 #include <dm.h>
9 #include <dm/uclass-internal.h>
10 #include <asm/acpi_s3.h>
11 #include <asm/acpi_table.h>
12 #include <asm/io.h>
13 #include <asm/tables.h>
14 #include <asm/arch/global_nvs.h>
15 #include <asm/arch/iomap.h>
16
acpi_create_fadt(struct acpi_fadt * fadt,struct acpi_facs * facs,void * dsdt)17 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
18 void *dsdt)
19 {
20 struct acpi_table_header *header = &(fadt->header);
21 u16 pmbase = ACPI_BASE_ADDRESS;
22
23 memset((void *)fadt, 0, sizeof(struct acpi_fadt));
24
25 acpi_fill_header(header, "FACP");
26 header->length = sizeof(struct acpi_fadt);
27 header->revision = 4;
28
29 fadt->firmware_ctrl = (u32)facs;
30 fadt->dsdt = (u32)dsdt;
31 fadt->preferred_pm_profile = ACPI_PM_MOBILE;
32 fadt->sci_int = 9;
33 fadt->smi_cmd = 0;
34 fadt->acpi_enable = 0;
35 fadt->acpi_disable = 0;
36 fadt->s4bios_req = 0;
37 fadt->pstate_cnt = 0;
38 fadt->pm1a_evt_blk = pmbase;
39 fadt->pm1b_evt_blk = 0x0;
40 fadt->pm1a_cnt_blk = pmbase + 0x4;
41 fadt->pm1b_cnt_blk = 0x0;
42 fadt->pm2_cnt_blk = pmbase + 0x50;
43 fadt->pm_tmr_blk = pmbase + 0x8;
44 fadt->gpe0_blk = pmbase + 0x20;
45 fadt->gpe1_blk = 0;
46 fadt->pm1_evt_len = 4;
47 fadt->pm1_cnt_len = 2;
48 fadt->pm2_cnt_len = 1;
49 fadt->pm_tmr_len = 4;
50 fadt->gpe0_blk_len = 8;
51 fadt->gpe1_blk_len = 0;
52 fadt->gpe1_base = 0;
53 fadt->cst_cnt = 0;
54 fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
55 fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
56 fadt->flush_size = 0;
57 fadt->flush_stride = 0;
58 fadt->duty_offset = 1;
59 fadt->duty_width = 0;
60 fadt->day_alrm = 0x0d;
61 fadt->mon_alrm = 0x00;
62 fadt->century = 0x00;
63 fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
64 fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
65 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
66 ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
67 ACPI_FADT_PLATFORM_CLOCK;
68
69 fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
70 fadt->reset_reg.bit_width = 8;
71 fadt->reset_reg.bit_offset = 0;
72 fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
73 fadt->reset_reg.addrl = IO_PORT_RESET;
74 fadt->reset_reg.addrh = 0;
75 fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
76
77 fadt->x_firmware_ctl_l = (u32)facs;
78 fadt->x_firmware_ctl_h = 0;
79 fadt->x_dsdt_l = (u32)dsdt;
80 fadt->x_dsdt_h = 0;
81
82 fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
83 fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
84 fadt->x_pm1a_evt_blk.bit_offset = 0;
85 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
86 fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
87 fadt->x_pm1a_evt_blk.addrh = 0x0;
88
89 fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
90 fadt->x_pm1b_evt_blk.bit_width = 0;
91 fadt->x_pm1b_evt_blk.bit_offset = 0;
92 fadt->x_pm1b_evt_blk.access_size = 0;
93 fadt->x_pm1b_evt_blk.addrl = 0x0;
94 fadt->x_pm1b_evt_blk.addrh = 0x0;
95
96 fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
97 fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
98 fadt->x_pm1a_cnt_blk.bit_offset = 0;
99 fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
100 fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
101 fadt->x_pm1a_cnt_blk.addrh = 0x0;
102
103 fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
104 fadt->x_pm1b_cnt_blk.bit_width = 0;
105 fadt->x_pm1b_cnt_blk.bit_offset = 0;
106 fadt->x_pm1b_cnt_blk.access_size = 0;
107 fadt->x_pm1b_cnt_blk.addrl = 0x0;
108 fadt->x_pm1b_cnt_blk.addrh = 0x0;
109
110 fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
111 fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
112 fadt->x_pm2_cnt_blk.bit_offset = 0;
113 fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
114 fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
115 fadt->x_pm2_cnt_blk.addrh = 0x0;
116
117 fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
118 fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
119 fadt->x_pm_tmr_blk.bit_offset = 0;
120 fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
121 fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
122 fadt->x_pm_tmr_blk.addrh = 0x0;
123
124 fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
125 fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
126 fadt->x_gpe0_blk.bit_offset = 0;
127 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
128 fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
129 fadt->x_gpe0_blk.addrh = 0x0;
130
131 fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
132 fadt->x_gpe1_blk.bit_width = 0;
133 fadt->x_gpe1_blk.bit_offset = 0;
134 fadt->x_gpe1_blk.access_size = 0;
135 fadt->x_gpe1_blk.addrl = 0x0;
136 fadt->x_gpe1_blk.addrh = 0x0;
137
138 header->checksum = table_compute_checksum(fadt, header->length);
139 }
140
acpi_create_gnvs(struct acpi_global_nvs * gnvs)141 void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
142 {
143 struct udevice *dev;
144 int ret;
145
146 /* at least we have one processor */
147 gnvs->pcnt = 1;
148 /* override the processor count with actual number */
149 ret = uclass_find_first_device(UCLASS_CPU, &dev);
150 if (ret == 0 && dev != NULL) {
151 ret = cpu_get_count(dev);
152 if (ret > 0)
153 gnvs->pcnt = ret;
154 }
155
156 /* determine whether internal uart is on */
157 if (IS_ENABLED(CONFIG_INTERNAL_UART))
158 gnvs->iuart_en = 1;
159 else
160 gnvs->iuart_en = 0;
161 }
162
163 #ifdef CONFIG_HAVE_ACPI_RESUME
164 /*
165 * The following two routines are called at a very early stage, even before
166 * FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS
167 * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses
168 * of these two blocks are programmed by either U-Boot or FSP.
169 *
170 * It has been verified that 1st phase API (see arch/x86/lib/fsp/fsp_car.S)
171 * on Intel BayTrail SoC already initializes these two base addresses so
172 * we are safe to access these registers here.
173 */
174
chipset_prev_sleep_state(void)175 enum acpi_sleep_state chipset_prev_sleep_state(void)
176 {
177 u32 pm1_sts;
178 u32 pm1_cnt;
179 u32 gen_pmcon1;
180 enum acpi_sleep_state prev_sleep_state = ACPI_S0;
181
182 /* Read Power State */
183 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
184 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
185 gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1);
186
187 debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
188 pm1_sts, pm1_cnt, gen_pmcon1);
189
190 if (pm1_sts & WAK_STS)
191 prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt);
192
193 if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR))
194 prev_sleep_state = ACPI_S5;
195
196 return prev_sleep_state;
197 }
198
chipset_clear_sleep_state(void)199 void chipset_clear_sleep_state(void)
200 {
201 u32 pm1_cnt;
202
203 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
204 outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
205 }
206 #endif
207