1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * sun6i specific clock code
4 *
5 * (C) Copyright 2007-2012
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
10 */
11
12 #include <common.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/prcm.h>
16 #include <asm/arch/sys_proto.h>
17
18 #ifdef CONFIG_SPL_BUILD
clock_init_safe(void)19 void clock_init_safe(void)
20 {
21 struct sunxi_ccm_reg * const ccm =
22 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
23
24 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
25 struct sunxi_prcm_reg * const prcm =
26 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
27
28 /* Set PLL ldo voltage without this PLL6 does not work properly */
29 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
30 PRCM_PLL_CTRL_LDO_KEY);
31 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
32 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
33 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
34 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
35 #endif
36
37 #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
38 /* Set PLL lock enable bits and switch to old lock mode */
39 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
40 #endif
41
42 clock_set_pll1(408000000);
43
44 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
45 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
46 ;
47
48 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
49
50 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
51 if (IS_ENABLED(CONFIG_MACH_SUN6I))
52 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
53
54 #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
55 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
56 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);
57 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
58 setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);
59 #endif
60 }
61 #endif
62
clock_init_sec(void)63 void clock_init_sec(void)
64 {
65 #ifdef CONFIG_MACH_SUNXI_H3_H5
66 struct sunxi_ccm_reg * const ccm =
67 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
68 struct sunxi_prcm_reg * const prcm =
69 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
70
71 setbits_le32(&ccm->ccu_sec_switch,
72 CCM_SEC_SWITCH_MBUS_NONSEC |
73 CCM_SEC_SWITCH_BUS_NONSEC |
74 CCM_SEC_SWITCH_PLL_NONSEC);
75 setbits_le32(&prcm->prcm_sec_switch,
76 PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
77 PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
78 PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
79 #endif
80 }
81
clock_init_uart(void)82 void clock_init_uart(void)
83 {
84 #if CONFIG_CONS_INDEX < 5
85 struct sunxi_ccm_reg *const ccm =
86 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
87
88 /* uart clock source is apb2 */
89 writel(APB2_CLK_SRC_OSC24M|
90 APB2_CLK_RATE_N_1|
91 APB2_CLK_RATE_M(1),
92 &ccm->apb2_div);
93
94 /* open the clock for uart */
95 setbits_le32(&ccm->apb2_gate,
96 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
97 CONFIG_CONS_INDEX - 1));
98
99 /* deassert uart reset */
100 setbits_le32(&ccm->apb2_reset_cfg,
101 1 << (APB2_RESET_UART_SHIFT +
102 CONFIG_CONS_INDEX - 1));
103 #else
104 /* enable R_PIO and R_UART clocks, and de-assert resets */
105 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
106 #endif
107 }
108
109 #ifdef CONFIG_SPL_BUILD
clock_set_pll1(unsigned int clk)110 void clock_set_pll1(unsigned int clk)
111 {
112 struct sunxi_ccm_reg * const ccm =
113 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
114 const int p = 0;
115 int k = 1;
116 int m = 1;
117
118 if (clk > 1152000000) {
119 k = 2;
120 } else if (clk > 768000000) {
121 k = 3;
122 m = 2;
123 }
124
125 /* Switch to 24MHz clock while changing PLL1 */
126 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
127 ATB_DIV_2 << ATB_DIV_SHIFT |
128 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
129 &ccm->cpu_axi_cfg);
130
131 /*
132 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
133 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
134 */
135 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
136 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
137 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
138 sdelay(200);
139
140 /* Switch CPU to PLL1 */
141 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
142 ATB_DIV_2 << ATB_DIV_SHIFT |
143 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
144 &ccm->cpu_axi_cfg);
145 }
146 #endif
147
clock_set_pll3(unsigned int clk)148 void clock_set_pll3(unsigned int clk)
149 {
150 struct sunxi_ccm_reg * const ccm =
151 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
152 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
153
154 if (clk == 0) {
155 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
156 return;
157 }
158
159 /* PLL3 rate = 24000000 * n / m */
160 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
161 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
162 &ccm->pll3_cfg);
163 }
164
165 #ifdef CONFIG_SUNXI_DE2
clock_set_pll3_factors(int m,int n)166 void clock_set_pll3_factors(int m, int n)
167 {
168 struct sunxi_ccm_reg * const ccm =
169 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
170
171 /* PLL3 rate = 24000000 * n / m */
172 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
173 CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
174 &ccm->pll3_cfg);
175
176 while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))
177 ;
178 }
179 #endif
180
clock_set_pll5(unsigned int clk,bool sigma_delta_enable)181 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
182 {
183 struct sunxi_ccm_reg * const ccm =
184 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
185 const int max_n = 32;
186 int k = 1, m = 2;
187
188 #ifdef CONFIG_MACH_SUNXI_H3_H5
189 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
190 CCM_PLL5_TUN_INIT_FREQ_MASK,
191 CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
192 #endif
193
194 if (sigma_delta_enable)
195 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
196
197 /* PLL5 rate = 24000000 * n * k / m */
198 if (clk > 24000000 * k * max_n / m) {
199 m = 1;
200 if (clk > 24000000 * k * max_n / m)
201 k = 2;
202 }
203 writel(CCM_PLL5_CTRL_EN |
204 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
205 CCM_PLL5_CTRL_UPD |
206 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
207 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
208
209 udelay(5500);
210 }
211
212 #ifdef CONFIG_MACH_SUN6I
clock_set_mipi_pll(unsigned int clk)213 void clock_set_mipi_pll(unsigned int clk)
214 {
215 struct sunxi_ccm_reg * const ccm =
216 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
217 unsigned int k, m, n, value, diff;
218 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
219 unsigned int src = clock_get_pll3();
220
221 /* All calculations are in KHz to avoid overflows */
222 clk /= 1000;
223 src /= 1000;
224
225 /* Pick the closest lower clock */
226 for (k = 1; k <= 4; k++) {
227 for (m = 1; m <= 16; m++) {
228 for (n = 1; n <= 16; n++) {
229 value = src * n * k / m;
230 if (value > clk)
231 continue;
232
233 diff = clk - value;
234 if (diff < best_diff) {
235 best_diff = diff;
236 best_k = k;
237 best_m = m;
238 best_n = n;
239 }
240 if (diff == 0)
241 goto done;
242 }
243 }
244 }
245
246 done:
247 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
248 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
249 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
250 }
251 #endif
252
253 #ifdef CONFIG_SUNXI_DE2
clock_set_pll10(unsigned int clk)254 void clock_set_pll10(unsigned int clk)
255 {
256 struct sunxi_ccm_reg * const ccm =
257 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
258 const int m = 2; /* 12 MHz steps */
259
260 if (clk == 0) {
261 clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
262 return;
263 }
264
265 /* PLL10 rate = 24000000 * n / m */
266 writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
267 CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
268 &ccm->pll10_cfg);
269
270 while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))
271 ;
272 }
273 #endif
274
275 #if defined(CONFIG_MACH_SUN8I_A33) || \
276 defined(CONFIG_MACH_SUN8I_R40) || \
277 defined(CONFIG_MACH_SUN50I)
clock_set_pll11(unsigned int clk,bool sigma_delta_enable)278 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
279 {
280 struct sunxi_ccm_reg * const ccm =
281 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
282
283 if (sigma_delta_enable)
284 writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);
285
286 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
287 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
288 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
289
290 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
291 ;
292 }
293 #endif
294
clock_get_pll3(void)295 unsigned int clock_get_pll3(void)
296 {
297 struct sunxi_ccm_reg *const ccm =
298 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
299 uint32_t rval = readl(&ccm->pll3_cfg);
300 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
301 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
302
303 /* Multiply by 1000 after dividing by m to avoid integer overflows */
304 return (24000 * n / m) * 1000;
305 }
306
clock_get_pll6(void)307 unsigned int clock_get_pll6(void)
308 {
309 struct sunxi_ccm_reg *const ccm =
310 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
311 uint32_t rval = readl(&ccm->pll6_cfg);
312 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
313 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
314 return 24000000 * n * k / 2;
315 }
316
clock_get_mipi_pll(void)317 unsigned int clock_get_mipi_pll(void)
318 {
319 struct sunxi_ccm_reg *const ccm =
320 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
321 uint32_t rval = readl(&ccm->mipi_pll_cfg);
322 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
323 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
324 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
325 unsigned int src = clock_get_pll3();
326
327 /* Multiply by 1000 after dividing by m to avoid integer overflows */
328 return ((src / 1000) * n * k / m) * 1000;
329 }
330
clock_set_de_mod_clock(u32 * clk_cfg,unsigned int hz)331 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
332 {
333 int pll = clock_get_pll6() * 2;
334 int div = 1;
335
336 while ((pll / div) > hz)
337 div++;
338
339 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
340 clk_cfg);
341 }
342