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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 /* Tegra cache routines */
7 
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/arch-tegra/ap.h>
11 #include <asm/arch/gp_padctrl.h>
12 
13 #ifndef CONFIG_ARM64
config_cache(void)14 void config_cache(void)
15 {
16 	u32 reg = 0;
17 
18 	/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
19 	asm volatile(
20 		"mrc p15, 0, r0, c1, c0, 1\n"
21 		"orr r0, r0, #0x41\n"
22 		"mcr p15, 0, r0, c1, c0, 1\n");
23 
24 	/* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
25 	if (tegra_get_chip() < CHIPID_TEGRA114)
26 		return;
27 
28 	/*
29 	 * Systems with an architectural L2 cache must not use the PL310.
30 	 * Config L2CTLR here for a data RAM latency of 3 cycles.
31 	 */
32 	asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
33 	reg &= ~7;
34 	reg |= 2;
35 	asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
36 }
37 #endif
38