1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * IN THE SOFTWARE.
27 */
28
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
31
32 #include <stdint.h>
33 #include <stdbool.h>
34 #include <stdlib.h>
35 #include "main/macros.h"
36 #include "amd_family.h"
37
38 struct radeon_info;
39 struct ac_surf_info;
40 struct radeon_surf;
41
42 #define FREE(x) free(x)
43
44 enum radeon_bo_domain { /* bitfield */
45 RADEON_DOMAIN_GTT = 2,
46 RADEON_DOMAIN_VRAM = 4,
47 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
48 };
49
50 enum radeon_bo_flag { /* bitfield */
51 RADEON_FLAG_GTT_WC = (1 << 0),
52 RADEON_FLAG_CPU_ACCESS = (1 << 1),
53 RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
54 RADEON_FLAG_VIRTUAL = (1 << 3),
55 RADEON_FLAG_VA_UNCACHED = (1 << 4),
56 RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
57 RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
58 RADEON_FLAG_READ_ONLY = (1 << 7),
59 };
60
61 enum radeon_bo_usage { /* bitfield */
62 RADEON_USAGE_READ = 2,
63 RADEON_USAGE_WRITE = 4,
64 RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
65 };
66
67 enum ring_type {
68 RING_GFX = 0,
69 RING_COMPUTE,
70 RING_DMA,
71 RING_UVD,
72 RING_VCE,
73 RING_LAST,
74 };
75
76 enum radeon_ctx_priority {
77 RADEON_CTX_PRIORITY_INVALID = -1,
78 RADEON_CTX_PRIORITY_LOW = 0,
79 RADEON_CTX_PRIORITY_MEDIUM,
80 RADEON_CTX_PRIORITY_HIGH,
81 RADEON_CTX_PRIORITY_REALTIME,
82 };
83
84 enum radeon_value_id {
85 RADEON_TIMESTAMP,
86 RADEON_NUM_BYTES_MOVED,
87 RADEON_NUM_EVICTIONS,
88 RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
89 RADEON_VRAM_USAGE,
90 RADEON_VRAM_VIS_USAGE,
91 RADEON_GTT_USAGE,
92 RADEON_GPU_TEMPERATURE,
93 RADEON_CURRENT_SCLK,
94 RADEON_CURRENT_MCLK,
95 };
96
97 struct radeon_winsys_cs {
98 unsigned cdw; /* Number of used dwords. */
99 unsigned max_dw; /* Maximum number of dwords. */
100 uint32_t *buf; /* The base pointer of the chunk. */
101 };
102
103 #define RADEON_SURF_TYPE_MASK 0xFF
104 #define RADEON_SURF_TYPE_SHIFT 0
105 #define RADEON_SURF_TYPE_1D 0
106 #define RADEON_SURF_TYPE_2D 1
107 #define RADEON_SURF_TYPE_3D 2
108 #define RADEON_SURF_TYPE_CUBEMAP 3
109 #define RADEON_SURF_TYPE_1D_ARRAY 4
110 #define RADEON_SURF_TYPE_2D_ARRAY 5
111 #define RADEON_SURF_MODE_MASK 0xFF
112 #define RADEON_SURF_MODE_SHIFT 8
113
114 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
115 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
116 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
117
118 enum radeon_bo_layout {
119 RADEON_LAYOUT_LINEAR = 0,
120 RADEON_LAYOUT_TILED,
121 RADEON_LAYOUT_SQUARETILED,
122
123 RADEON_LAYOUT_UNKNOWN
124 };
125
126 /* Tiling info for display code, DRI sharing, and other data. */
127 struct radeon_bo_metadata {
128 /* Tiling flags describing the texture layout for display code
129 * and DRI sharing.
130 */
131 union {
132 struct {
133 enum radeon_bo_layout microtile;
134 enum radeon_bo_layout macrotile;
135 unsigned pipe_config;
136 unsigned bankw;
137 unsigned bankh;
138 unsigned tile_split;
139 unsigned mtilea;
140 unsigned num_banks;
141 unsigned stride;
142 bool scanout;
143 } legacy;
144
145 struct {
146 /* surface flags */
147 unsigned swizzle_mode:5;
148 } gfx9;
149 } u;
150
151 /* Additional metadata associated with the buffer, in bytes.
152 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
153 * Supported by amdgpu only.
154 */
155 uint32_t size_metadata;
156 uint32_t metadata[64];
157 };
158
159 uint32_t syncobj_handle;
160 struct radeon_winsys_fence;
161
162 struct radeon_winsys_bo {
163 uint64_t va;
164 bool is_local;
165 };
166 struct radv_winsys_sem_counts {
167 uint32_t syncobj_count;
168 uint32_t sem_count;
169 uint32_t *syncobj;
170 struct radeon_winsys_sem **sem;
171 };
172
173 struct radv_winsys_sem_info {
174 bool cs_emit_signal;
175 bool cs_emit_wait;
176 struct radv_winsys_sem_counts wait;
177 struct radv_winsys_sem_counts signal;
178 };
179
180 struct radeon_winsys {
181 void (*destroy)(struct radeon_winsys *ws);
182
183 void (*query_info)(struct radeon_winsys *ws,
184 struct radeon_info *info);
185
186 uint64_t (*query_value)(struct radeon_winsys *ws,
187 enum radeon_value_id value);
188
189 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
190 unsigned num_registers, uint32_t *out);
191
192 const char *(*get_chip_name)(struct radeon_winsys *ws);
193
194 struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
195 uint64_t size,
196 unsigned alignment,
197 enum radeon_bo_domain domain,
198 enum radeon_bo_flag flags);
199
200 void (*buffer_destroy)(struct radeon_winsys_bo *bo);
201 void *(*buffer_map)(struct radeon_winsys_bo *bo);
202
203 struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
204 int fd,
205 unsigned *stride, unsigned *offset);
206
207 bool (*buffer_get_fd)(struct radeon_winsys *ws,
208 struct radeon_winsys_bo *bo,
209 int *fd);
210
211 void (*buffer_unmap)(struct radeon_winsys_bo *bo);
212
213 void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
214 struct radeon_bo_metadata *md);
215
216 void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
217 uint64_t offset, uint64_t size,
218 struct radeon_winsys_bo *bo, uint64_t bo_offset);
219 struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
220 enum radeon_ctx_priority priority);
221 void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
222
223 bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
224 enum ring_type ring_type, int ring_index);
225
226 struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
227 enum ring_type ring_type);
228
229 void (*cs_destroy)(struct radeon_winsys_cs *cs);
230
231 void (*cs_reset)(struct radeon_winsys_cs *cs);
232
233 bool (*cs_finalize)(struct radeon_winsys_cs *cs);
234
235 void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
236
237 int (*cs_submit)(struct radeon_winsys_ctx *ctx,
238 int queue_index,
239 struct radeon_winsys_cs **cs_array,
240 unsigned cs_count,
241 struct radeon_winsys_cs *initial_preamble_cs,
242 struct radeon_winsys_cs *continue_preamble_cs,
243 struct radv_winsys_sem_info *sem_info,
244 bool can_patch,
245 struct radeon_winsys_fence *fence);
246
247 void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
248 struct radeon_winsys_bo *bo,
249 uint8_t priority);
250
251 void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
252 struct radeon_winsys_cs *child);
253
254 void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count);
255
256 int (*surface_init)(struct radeon_winsys *ws,
257 const struct ac_surf_info *surf_info,
258 struct radeon_surf *surf);
259
260 int (*surface_best)(struct radeon_winsys *ws,
261 struct radeon_surf *surf);
262
263 struct radeon_winsys_fence *(*create_fence)();
264 void (*destroy_fence)(struct radeon_winsys_fence *fence);
265 bool (*fence_wait)(struct radeon_winsys *ws,
266 struct radeon_winsys_fence *fence,
267 bool absolute,
268 uint64_t timeout);
269
270 /* old semaphores - non shareable */
271 struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
272 void (*destroy_sem)(struct radeon_winsys_sem *sem);
273
274 /* new shareable sync objects */
275 int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
276 void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
277
278 void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
279 void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
280 bool (*wait_syncobj)(struct radeon_winsys *ws, uint32_t handle, uint64_t timeout);
281
282 int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
283 int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
284
285 int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
286
287 /* Note that this, unlike the normal import, uses an existing syncobj. */
288 int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
289
290 };
291
radeon_emit(struct radeon_winsys_cs * cs,uint32_t value)292 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
293 {
294 cs->buf[cs->cdw++] = value;
295 }
296
radeon_emit_array(struct radeon_winsys_cs * cs,const uint32_t * values,unsigned count)297 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
298 const uint32_t *values, unsigned count)
299 {
300 memcpy(cs->buf + cs->cdw, values, count * 4);
301 cs->cdw += count;
302 }
303
radv_buffer_get_va(struct radeon_winsys_bo * bo)304 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
305 {
306 return bo->va;
307 }
308
radv_cs_add_buffer(struct radeon_winsys * ws,struct radeon_winsys_cs * cs,struct radeon_winsys_bo * bo,uint8_t priority)309 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
310 struct radeon_winsys_cs *cs,
311 struct radeon_winsys_bo *bo,
312 uint8_t priority)
313 {
314 if (bo->is_local)
315 return;
316
317 ws->cs_add_buffer(cs, bo, priority);
318 }
319
320 #endif /* RADV_RADEON_WINSYS_H */
321