1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
4 *
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 *
7 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
8 * follows:
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * dm644x_emac.c
13 *
14 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
15 *
16 * Copyright (C) 2005 Texas Instruments.
17 *
18 * ----------------------------------------------------------------------------
19 *
20 * Modifications:
21 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
22 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
23 */
24 #include <common.h>
25 #include <command.h>
26 #include <net.h>
27 #include <miiphy.h>
28 #include <malloc.h>
29 #include <netdev.h>
30 #include <linux/compiler.h>
31 #include <asm/arch/emac_defs.h>
32 #include <asm/io.h>
33 #include "davinci_emac.h"
34
35 unsigned int emac_dbg = 0;
36 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
37
38 #ifdef EMAC_HW_RAM_ADDR
BD_TO_HW(unsigned long x)39 static inline unsigned long BD_TO_HW(unsigned long x)
40 {
41 if (x == 0)
42 return 0;
43
44 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
45 }
46
HW_TO_BD(unsigned long x)47 static inline unsigned long HW_TO_BD(unsigned long x)
48 {
49 if (x == 0)
50 return 0;
51
52 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
53 }
54 #else
55 #define BD_TO_HW(x) (x)
56 #define HW_TO_BD(x) (x)
57 #endif
58
59 #ifdef DAVINCI_EMAC_GIG_ENABLE
60 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
61 #else
62 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
63 #endif
64
65 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
66 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
67 EMAC_MDIO_CLOCK_FREQ) - 1)
68 #endif
69
70 static void davinci_eth_mdio_enable(void);
71
72 static int gen_init_phy(int phy_addr);
73 static int gen_is_phy_connected(int phy_addr);
74 static int gen_get_link_speed(int phy_addr);
75 static int gen_auto_negotiate(int phy_addr);
76
eth_mdio_enable(void)77 void eth_mdio_enable(void)
78 {
79 davinci_eth_mdio_enable();
80 }
81
82 /* EMAC Addresses */
83 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
84 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
85 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
86
87 /* EMAC descriptors */
88 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
89 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
90 static volatile emac_desc *emac_rx_active_head = 0;
91 static volatile emac_desc *emac_rx_active_tail = 0;
92 static int emac_rx_queue_active = 0;
93
94 /* Receive packet buffers */
95 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
96 __aligned(ARCH_DMA_MINALIGN);
97
98 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
99 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
100 #endif
101
102 /* PHY address for a discovered PHY (0xff - not found) */
103 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
104
105 /* number of PHY found active */
106 static u_int8_t num_phy;
107
108 phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
109
davinci_eth_set_mac_addr(struct eth_device * dev)110 static int davinci_eth_set_mac_addr(struct eth_device *dev)
111 {
112 unsigned long mac_hi;
113 unsigned long mac_lo;
114
115 /*
116 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
117 * receive)
118 * Using channel 0 only - other channels are disabled
119 * */
120 writel(0, &adap_emac->MACINDEX);
121 mac_hi = (dev->enetaddr[3] << 24) |
122 (dev->enetaddr[2] << 16) |
123 (dev->enetaddr[1] << 8) |
124 (dev->enetaddr[0]);
125 mac_lo = (dev->enetaddr[5] << 8) |
126 (dev->enetaddr[4]);
127
128 writel(mac_hi, &adap_emac->MACADDRHI);
129 #if defined(DAVINCI_EMAC_VERSION2)
130 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
131 &adap_emac->MACADDRLO);
132 #else
133 writel(mac_lo, &adap_emac->MACADDRLO);
134 #endif
135
136 writel(0, &adap_emac->MACHASH1);
137 writel(0, &adap_emac->MACHASH2);
138
139 /* Set source MAC address - REQUIRED */
140 writel(mac_hi, &adap_emac->MACSRCADDRHI);
141 writel(mac_lo, &adap_emac->MACSRCADDRLO);
142
143
144 return 0;
145 }
146
davinci_eth_mdio_enable(void)147 static void davinci_eth_mdio_enable(void)
148 {
149 u_int32_t clkdiv;
150
151 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
152
153 writel((clkdiv & 0xff) |
154 MDIO_CONTROL_ENABLE |
155 MDIO_CONTROL_FAULT |
156 MDIO_CONTROL_FAULT_ENABLE,
157 &adap_mdio->CONTROL);
158
159 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
160 ;
161 }
162
163 /*
164 * Tries to find an active connected PHY. Returns 1 if address if found.
165 * If no active PHY (or more than one PHY) found returns 0.
166 * Sets active_phy_addr variable.
167 */
davinci_eth_phy_detect(void)168 static int davinci_eth_phy_detect(void)
169 {
170 u_int32_t phy_act_state;
171 int i;
172 int j;
173 unsigned int count = 0;
174
175 for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
176 active_phy_addr[i] = 0xff;
177
178 udelay(1000);
179 phy_act_state = readl(&adap_mdio->ALIVE);
180
181 if (phy_act_state == 0)
182 return 0; /* No active PHYs */
183
184 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
185
186 for (i = 0, j = 0; i < 32; i++)
187 if (phy_act_state & (1 << i)) {
188 count++;
189 if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
190 active_phy_addr[j++] = i;
191 } else {
192 printf("%s: to many PHYs detected.\n",
193 __func__);
194 count = 0;
195 break;
196 }
197 }
198
199 num_phy = count;
200
201 return count;
202 }
203
204
205 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
davinci_eth_phy_read(u_int8_t phy_addr,u_int8_t reg_num,u_int16_t * data)206 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
207 {
208 int tmp;
209
210 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
211 ;
212
213 writel(MDIO_USERACCESS0_GO |
214 MDIO_USERACCESS0_WRITE_READ |
215 ((reg_num & 0x1f) << 21) |
216 ((phy_addr & 0x1f) << 16),
217 &adap_mdio->USERACCESS0);
218
219 /* Wait for command to complete */
220 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
221 ;
222
223 if (tmp & MDIO_USERACCESS0_ACK) {
224 *data = tmp & 0xffff;
225 return 1;
226 }
227
228 return 0;
229 }
230
231 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
davinci_eth_phy_write(u_int8_t phy_addr,u_int8_t reg_num,u_int16_t data)232 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
233 {
234
235 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
236 ;
237
238 writel(MDIO_USERACCESS0_GO |
239 MDIO_USERACCESS0_WRITE_WRITE |
240 ((reg_num & 0x1f) << 21) |
241 ((phy_addr & 0x1f) << 16) |
242 (data & 0xffff),
243 &adap_mdio->USERACCESS0);
244
245 /* Wait for command to complete */
246 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
247 ;
248
249 return 1;
250 }
251
252 /* PHY functions for a generic PHY */
gen_init_phy(int phy_addr)253 static int gen_init_phy(int phy_addr)
254 {
255 int ret = 1;
256
257 if (gen_get_link_speed(phy_addr)) {
258 /* Try another time */
259 ret = gen_get_link_speed(phy_addr);
260 }
261
262 return(ret);
263 }
264
gen_is_phy_connected(int phy_addr)265 static int gen_is_phy_connected(int phy_addr)
266 {
267 u_int16_t dummy;
268
269 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
270 }
271
get_active_phy(void)272 static int get_active_phy(void)
273 {
274 int i;
275
276 for (i = 0; i < num_phy; i++)
277 if (phy[i].get_link_speed(active_phy_addr[i]))
278 return i;
279
280 return -1; /* Return error if no link */
281 }
282
gen_get_link_speed(int phy_addr)283 static int gen_get_link_speed(int phy_addr)
284 {
285 u_int16_t tmp;
286
287 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
288 (tmp & 0x04)) {
289 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
290 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
291 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
292
293 /* Speed doesn't matter, there is no setting for it in EMAC. */
294 if (tmp & (LPA_100FULL | LPA_10FULL)) {
295 /* set EMAC for Full Duplex */
296 writel(EMAC_MACCONTROL_MIIEN_ENABLE |
297 EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
298 &adap_emac->MACCONTROL);
299 } else {
300 /*set EMAC for Half Duplex */
301 writel(EMAC_MACCONTROL_MIIEN_ENABLE,
302 &adap_emac->MACCONTROL);
303 }
304
305 if (tmp & (LPA_100FULL | LPA_100HALF))
306 writel(readl(&adap_emac->MACCONTROL) |
307 EMAC_MACCONTROL_RMIISPEED_100,
308 &adap_emac->MACCONTROL);
309 else
310 writel(readl(&adap_emac->MACCONTROL) &
311 ~EMAC_MACCONTROL_RMIISPEED_100,
312 &adap_emac->MACCONTROL);
313 #endif
314 return(1);
315 }
316
317 return(0);
318 }
319
gen_auto_negotiate(int phy_addr)320 static int gen_auto_negotiate(int phy_addr)
321 {
322 u_int16_t tmp;
323 u_int16_t val;
324 unsigned long cntr = 0;
325
326 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
327 return 0;
328
329 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
330 BMCR_SPEED100;
331 davinci_eth_phy_write(phy_addr, MII_BMCR, val);
332
333 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
334 return 0;
335
336 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
337 ADVERTISE_10HALF);
338 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
339
340 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
341 return(0);
342
343 #ifdef DAVINCI_EMAC_GIG_ENABLE
344 davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
345 val |= PHY_1000BTCR_1000FD;
346 val &= ~PHY_1000BTCR_1000HD;
347 davinci_eth_phy_write(phy_addr, MII_CTRL1000, val);
348 davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
349 #endif
350
351 /* Restart Auto_negotiation */
352 tmp |= BMCR_ANRESTART;
353 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
354
355 /*check AutoNegotiate complete */
356 do {
357 udelay(40000);
358 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
359 return 0;
360
361 if (tmp & BMSR_ANEGCOMPLETE)
362 break;
363
364 cntr++;
365 } while (cntr < 200);
366
367 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
368 return(0);
369
370 if (!(tmp & BMSR_ANEGCOMPLETE))
371 return(0);
372
373 return(gen_get_link_speed(phy_addr));
374 }
375 /* End of generic PHY functions */
376
377
378 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
davinci_mii_phy_read(struct mii_dev * bus,int addr,int devad,int reg)379 static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
380 int reg)
381 {
382 unsigned short value = 0;
383 int retval = davinci_eth_phy_read(addr, reg, &value);
384
385 return retval ? value : -EIO;
386 }
387
davinci_mii_phy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)388 static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
389 int reg, u16 value)
390 {
391 return davinci_eth_phy_write(addr, reg, value) ? 0 : 1;
392 }
393 #endif
394
davinci_eth_gigabit_enable(int phy_addr)395 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
396 {
397 u_int16_t data;
398
399 if (davinci_eth_phy_read(phy_addr, 0, &data)) {
400 if (data & (1 << 6)) { /* speed selection MSB */
401 /*
402 * Check if link detected is giga-bit
403 * If Gigabit mode detected, enable gigbit in MAC
404 */
405 writel(readl(&adap_emac->MACCONTROL) |
406 EMAC_MACCONTROL_GIGFORCE |
407 EMAC_MACCONTROL_GIGABIT_ENABLE,
408 &adap_emac->MACCONTROL);
409 }
410 }
411 }
412
413 /* Eth device open */
davinci_eth_open(struct eth_device * dev,bd_t * bis)414 static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
415 {
416 dv_reg_p addr;
417 u_int32_t clkdiv, cnt, mac_control;
418 uint16_t __maybe_unused lpa_val;
419 volatile emac_desc *rx_desc;
420 int index;
421
422 debug_emac("+ emac_open\n");
423
424 /* Reset EMAC module and disable interrupts in wrapper */
425 writel(1, &adap_emac->SOFTRESET);
426 while (readl(&adap_emac->SOFTRESET) != 0)
427 ;
428 #if defined(DAVINCI_EMAC_VERSION2)
429 writel(1, &adap_ewrap->softrst);
430 while (readl(&adap_ewrap->softrst) != 0)
431 ;
432 #else
433 writel(0, &adap_ewrap->EWCTL);
434 for (cnt = 0; cnt < 5; cnt++) {
435 clkdiv = readl(&adap_ewrap->EWCTL);
436 }
437 #endif
438
439 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
440 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
441 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
442 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
443 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
444 #endif
445 rx_desc = emac_rx_desc;
446
447 writel(1, &adap_emac->TXCONTROL);
448 writel(1, &adap_emac->RXCONTROL);
449
450 davinci_eth_set_mac_addr(dev);
451
452 /* Set DMA 8 TX / 8 RX Head pointers to 0 */
453 addr = &adap_emac->TX0HDP;
454 for (cnt = 0; cnt < 8; cnt++)
455 writel(0, addr++);
456
457 addr = &adap_emac->RX0HDP;
458 for (cnt = 0; cnt < 8; cnt++)
459 writel(0, addr++);
460
461 /* Clear Statistics (do this before setting MacControl register) */
462 addr = &adap_emac->RXGOODFRAMES;
463 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
464 writel(0, addr++);
465
466 /* No multicast addressing */
467 writel(0, &adap_emac->MACHASH1);
468 writel(0, &adap_emac->MACHASH2);
469
470 /* Create RX queue and set receive process in place */
471 emac_rx_active_head = emac_rx_desc;
472 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
473 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
474 rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
475 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
476 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
477 rx_desc++;
478 }
479
480 /* Finalize the rx desc list */
481 rx_desc--;
482 rx_desc->next = 0;
483 emac_rx_active_tail = rx_desc;
484 emac_rx_queue_active = 1;
485
486 /* Enable TX/RX */
487 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
488 writel(0, &adap_emac->RXBUFFEROFFSET);
489
490 /*
491 * No fancy configs - Use this for promiscous debug
492 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
493 */
494 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
495
496 /* Enable ch 0 only */
497 writel(1, &adap_emac->RXUNICASTSET);
498
499 /* Init MDIO & get link state */
500 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
501 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
502 &adap_mdio->CONTROL);
503
504 /* We need to wait for MDIO to start */
505 udelay(1000);
506
507 index = get_active_phy();
508 if (index == -1)
509 return(0);
510
511 /* Enable MII interface */
512 mac_control = EMAC_MACCONTROL_MIIEN_ENABLE;
513 #ifdef DAVINCI_EMAC_GIG_ENABLE
514 davinci_eth_phy_read(active_phy_addr[index], MII_STAT1000, &lpa_val);
515 if (lpa_val & PHY_1000BTSR_1000FD) {
516 debug_emac("eth_open : gigabit negotiated\n");
517 mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
518 mac_control |= EMAC_MACCONTROL_GIGABIT_ENABLE;
519 }
520 #endif
521
522 davinci_eth_phy_read(active_phy_addr[index], MII_LPA, &lpa_val);
523 if (lpa_val & (LPA_100FULL | LPA_10FULL))
524 /* set EMAC for Full Duplex */
525 mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
526 #if defined(CONFIG_SOC_DA8XX) || \
527 (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
528 mac_control |= EMAC_MACCONTROL_RMIISPEED_100;
529 #endif
530 writel(mac_control, &adap_emac->MACCONTROL);
531 /* Start receive process */
532 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
533
534 debug_emac("- emac_open\n");
535
536 return(1);
537 }
538
539 /* EMAC Channel Teardown */
davinci_eth_ch_teardown(int ch)540 static void davinci_eth_ch_teardown(int ch)
541 {
542 dv_reg dly = 0xff;
543 dv_reg cnt;
544
545 debug_emac("+ emac_ch_teardown\n");
546
547 if (ch == EMAC_CH_TX) {
548 /* Init TX channel teardown */
549 writel(0, &adap_emac->TXTEARDOWN);
550 do {
551 /*
552 * Wait here for Tx teardown completion interrupt to
553 * occur. Note: A task delay can be called here to pend
554 * rather than occupying CPU cycles - anyway it has
555 * been found that teardown takes very few cpu cycles
556 * and does not affect functionality
557 */
558 dly--;
559 udelay(1);
560 if (dly == 0)
561 break;
562 cnt = readl(&adap_emac->TX0CP);
563 } while (cnt != 0xfffffffc);
564 writel(cnt, &adap_emac->TX0CP);
565 writel(0, &adap_emac->TX0HDP);
566 } else {
567 /* Init RX channel teardown */
568 writel(0, &adap_emac->RXTEARDOWN);
569 do {
570 /*
571 * Wait here for Rx teardown completion interrupt to
572 * occur. Note: A task delay can be called here to pend
573 * rather than occupying CPU cycles - anyway it has
574 * been found that teardown takes very few cpu cycles
575 * and does not affect functionality
576 */
577 dly--;
578 udelay(1);
579 if (dly == 0)
580 break;
581 cnt = readl(&adap_emac->RX0CP);
582 } while (cnt != 0xfffffffc);
583 writel(cnt, &adap_emac->RX0CP);
584 writel(0, &adap_emac->RX0HDP);
585 }
586
587 debug_emac("- emac_ch_teardown\n");
588 }
589
590 /* Eth device close */
davinci_eth_close(struct eth_device * dev)591 static void davinci_eth_close(struct eth_device *dev)
592 {
593 debug_emac("+ emac_close\n");
594
595 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
596 if (readl(&adap_emac->RXCONTROL) & 1)
597 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
598
599 /* Reset EMAC module and disable interrupts in wrapper */
600 writel(1, &adap_emac->SOFTRESET);
601 #if defined(DAVINCI_EMAC_VERSION2)
602 writel(1, &adap_ewrap->softrst);
603 #else
604 writel(0, &adap_ewrap->EWCTL);
605 #endif
606
607 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
608 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
609 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
610 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
611 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
612 #endif
613 debug_emac("- emac_close\n");
614 }
615
616 static int tx_send_loop = 0;
617
618 /*
619 * This function sends a single packet on the network and returns
620 * positive number (number of bytes transmitted) or negative for error
621 */
davinci_eth_send_packet(struct eth_device * dev,void * packet,int length)622 static int davinci_eth_send_packet (struct eth_device *dev,
623 void *packet, int length)
624 {
625 int ret_status = -1;
626 int index;
627 tx_send_loop = 0;
628
629 index = get_active_phy();
630 if (index == -1) {
631 printf(" WARN: emac_send_packet: No link\n");
632 return (ret_status);
633 }
634
635 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
636 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
637 length = EMAC_MIN_ETHERNET_PKT_SIZE;
638 }
639
640 /* Populate the TX descriptor */
641 emac_tx_desc->next = 0;
642 emac_tx_desc->buffer = (u_int8_t *) packet;
643 emac_tx_desc->buff_off_len = (length & 0xffff);
644 emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
645 EMAC_CPPI_SOP_BIT |
646 EMAC_CPPI_OWNERSHIP_BIT |
647 EMAC_CPPI_EOP_BIT);
648
649 flush_dcache_range((unsigned long)packet,
650 (unsigned long)packet + ALIGN(length, PKTALIGN));
651
652 /* Send the packet */
653 writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
654
655 /* Wait for packet to complete or link down */
656 while (1) {
657 if (!phy[index].get_link_speed(active_phy_addr[index])) {
658 davinci_eth_ch_teardown (EMAC_CH_TX);
659 return (ret_status);
660 }
661
662 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
663 ret_status = length;
664 break;
665 }
666 tx_send_loop++;
667 }
668
669 return (ret_status);
670 }
671
672 /*
673 * This function handles receipt of a packet from the network
674 */
davinci_eth_rcv_packet(struct eth_device * dev)675 static int davinci_eth_rcv_packet (struct eth_device *dev)
676 {
677 volatile emac_desc *rx_curr_desc;
678 volatile emac_desc *curr_desc;
679 volatile emac_desc *tail_desc;
680 int status, ret = -1;
681
682 rx_curr_desc = emac_rx_active_head;
683 if (!rx_curr_desc)
684 return 0;
685 status = rx_curr_desc->pkt_flag_len;
686 if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
687 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
688 /* Error in packet - discard it and requeue desc */
689 printf ("WARN: emac_rcv_pkt: Error in packet\n");
690 } else {
691 unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
692 unsigned short len =
693 rx_curr_desc->buff_off_len & 0xffff;
694
695 invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
696 net_process_received_packet(rx_curr_desc->buffer, len);
697 ret = len;
698 }
699
700 /* Ack received packet descriptor */
701 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
702 curr_desc = rx_curr_desc;
703 emac_rx_active_head =
704 (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
705
706 if (status & EMAC_CPPI_EOQ_BIT) {
707 if (emac_rx_active_head) {
708 writel(BD_TO_HW((ulong)emac_rx_active_head),
709 &adap_emac->RX0HDP);
710 } else {
711 emac_rx_queue_active = 0;
712 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
713 }
714 }
715
716 /* Recycle RX descriptor */
717 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
718 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
719 rx_curr_desc->next = 0;
720
721 if (emac_rx_active_head == 0) {
722 printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
723 emac_rx_active_head = curr_desc;
724 emac_rx_active_tail = curr_desc;
725 if (emac_rx_queue_active != 0) {
726 writel(BD_TO_HW((ulong)emac_rx_active_head),
727 &adap_emac->RX0HDP);
728 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
729 emac_rx_queue_active = 1;
730 }
731 } else {
732 tail_desc = emac_rx_active_tail;
733 emac_rx_active_tail = curr_desc;
734 tail_desc->next = BD_TO_HW((ulong) curr_desc);
735 status = tail_desc->pkt_flag_len;
736 if (status & EMAC_CPPI_EOQ_BIT) {
737 writel(BD_TO_HW((ulong)curr_desc),
738 &adap_emac->RX0HDP);
739 status &= ~EMAC_CPPI_EOQ_BIT;
740 tail_desc->pkt_flag_len = status;
741 }
742 }
743 return (ret);
744 }
745 return (0);
746 }
747
748 /*
749 * This function initializes the emac hardware. It does NOT initialize
750 * EMAC modules power or pin multiplexors, that is done by board_init()
751 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
752 */
davinci_emac_initialize(void)753 int davinci_emac_initialize(void)
754 {
755 u_int32_t phy_id;
756 u_int16_t tmp;
757 int i;
758 int ret;
759 struct eth_device *dev;
760
761 dev = malloc(sizeof *dev);
762
763 if (dev == NULL)
764 return -1;
765
766 memset(dev, 0, sizeof *dev);
767 strcpy(dev->name, "DaVinci-EMAC");
768
769 dev->iobase = 0;
770 dev->init = davinci_eth_open;
771 dev->halt = davinci_eth_close;
772 dev->send = davinci_eth_send_packet;
773 dev->recv = davinci_eth_rcv_packet;
774 dev->write_hwaddr = davinci_eth_set_mac_addr;
775
776 eth_register(dev);
777
778 davinci_eth_mdio_enable();
779
780 /* let the EMAC detect the PHYs */
781 udelay(5000);
782
783 for (i = 0; i < 256; i++) {
784 if (readl(&adap_mdio->ALIVE))
785 break;
786 udelay(1000);
787 }
788
789 if (i >= 256) {
790 printf("No ETH PHY detected!!!\n");
791 return(0);
792 }
793
794 /* Find if PHY(s) is/are connected */
795 ret = davinci_eth_phy_detect();
796 if (!ret)
797 return(0);
798 else
799 debug_emac(" %d ETH PHY detected\n", ret);
800
801 /* Get PHY ID and initialize phy_ops for a detected PHY */
802 for (i = 0; i < num_phy; i++) {
803 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
804 &tmp)) {
805 active_phy_addr[i] = 0xff;
806 continue;
807 }
808
809 phy_id = (tmp << 16) & 0xffff0000;
810
811 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
812 &tmp)) {
813 active_phy_addr[i] = 0xff;
814 continue;
815 }
816
817 phy_id |= tmp & 0x0000ffff;
818
819 switch (phy_id) {
820 #ifdef PHY_KSZ8873
821 case PHY_KSZ8873:
822 sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
823 active_phy_addr[i]);
824 phy[i].init = ksz8873_init_phy;
825 phy[i].is_phy_connected = ksz8873_is_phy_connected;
826 phy[i].get_link_speed = ksz8873_get_link_speed;
827 phy[i].auto_negotiate = ksz8873_auto_negotiate;
828 break;
829 #endif
830 #ifdef PHY_LXT972
831 case PHY_LXT972:
832 sprintf(phy[i].name, "LXT972 @ 0x%02x",
833 active_phy_addr[i]);
834 phy[i].init = lxt972_init_phy;
835 phy[i].is_phy_connected = lxt972_is_phy_connected;
836 phy[i].get_link_speed = lxt972_get_link_speed;
837 phy[i].auto_negotiate = lxt972_auto_negotiate;
838 break;
839 #endif
840 #ifdef PHY_DP83848
841 case PHY_DP83848:
842 sprintf(phy[i].name, "DP83848 @ 0x%02x",
843 active_phy_addr[i]);
844 phy[i].init = dp83848_init_phy;
845 phy[i].is_phy_connected = dp83848_is_phy_connected;
846 phy[i].get_link_speed = dp83848_get_link_speed;
847 phy[i].auto_negotiate = dp83848_auto_negotiate;
848 break;
849 #endif
850 #ifdef PHY_ET1011C
851 case PHY_ET1011C:
852 sprintf(phy[i].name, "ET1011C @ 0x%02x",
853 active_phy_addr[i]);
854 phy[i].init = gen_init_phy;
855 phy[i].is_phy_connected = gen_is_phy_connected;
856 phy[i].get_link_speed = et1011c_get_link_speed;
857 phy[i].auto_negotiate = gen_auto_negotiate;
858 break;
859 #endif
860 default:
861 sprintf(phy[i].name, "GENERIC @ 0x%02x",
862 active_phy_addr[i]);
863 phy[i].init = gen_init_phy;
864 phy[i].is_phy_connected = gen_is_phy_connected;
865 phy[i].get_link_speed = gen_get_link_speed;
866 phy[i].auto_negotiate = gen_auto_negotiate;
867 }
868
869 debug("Ethernet PHY: %s\n", phy[i].name);
870
871 int retval;
872 struct mii_dev *mdiodev = mdio_alloc();
873 if (!mdiodev)
874 return -ENOMEM;
875 strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
876 mdiodev->read = davinci_mii_phy_read;
877 mdiodev->write = davinci_mii_phy_write;
878
879 retval = mdio_register(mdiodev);
880 if (retval < 0)
881 return retval;
882 #ifdef DAVINCI_EMAC_GIG_ENABLE
883 #define PHY_CONF_REG 22
884 /* Enable PHY to clock out TX_CLK */
885 davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
886 tmp |= PHY_CONF_TXCLKEN;
887 davinci_eth_phy_write(active_phy_addr[i], PHY_CONF_REG, tmp);
888 davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
889 #endif
890 }
891
892 #if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
893 defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
894 !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
895 for (i = 0; i < num_phy; i++) {
896 if (phy[i].is_phy_connected(i))
897 phy[i].auto_negotiate(i);
898 }
899 #endif
900 return(1);
901 }
902