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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2010-2016 Freescale Semiconductor, Inc.
4  * Copyright 2017-2018 NXP Semiconductor
5  */
6 
7 /*
8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9  * Based on code from spd_sdram.c
10  * Author: James Yang [at freescale.com]
11  *         York Sun [at freescale.com]
12  */
13 
14 #include <common.h>
15 #include <cli.h>
16 #include <linux/ctype.h>
17 #include <asm/types.h>
18 #include <asm/io.h>
19 
20 #include <fsl_ddr_sdram.h>
21 #include <fsl_ddr.h>
22 
23 /* Option parameter Structures */
24 struct options_string {
25 	const char *option_name;
26 	size_t offset;
27 	unsigned int size;
28 	const char printhex;
29 };
30 
picos_to_mhz(unsigned int picos)31 static unsigned int picos_to_mhz(unsigned int picos)
32 {
33 	return 1000000 / picos;
34 }
35 
print_option_table(const struct options_string * table,int table_size,const void * base)36 static void print_option_table(const struct options_string *table,
37 			 int table_size,
38 			 const void *base)
39 {
40 	unsigned int i;
41 	unsigned int *ptr;
42 	unsigned long long *ptr_l;
43 
44 	for (i = 0; i < table_size; i++) {
45 		switch (table[i].size) {
46 		case 4:
47 			ptr = (unsigned int *) (base + table[i].offset);
48 			if (table[i].printhex) {
49 				printf("%s = 0x%08X\n",
50 					table[i].option_name, *ptr);
51 			} else {
52 				printf("%s = %u\n",
53 					table[i].option_name, *ptr);
54 			}
55 			break;
56 		case 8:
57 			ptr_l = (unsigned long long *) (base + table[i].offset);
58 			printf("%s = %llu\n",
59 				table[i].option_name, *ptr_l);
60 			break;
61 		default:
62 			printf("Unrecognized size!\n");
63 			break;
64 		}
65 	}
66 }
67 
handle_option_table(const struct options_string * table,int table_size,void * base,const char * opt,const char * val)68 static int handle_option_table(const struct options_string *table,
69 			 int table_size,
70 			 void *base,
71 			 const char *opt,
72 			 const char *val)
73 {
74 	unsigned int i;
75 	unsigned int value, *ptr;
76 	unsigned long long value_l, *ptr_l;
77 
78 	for (i = 0; i < table_size; i++) {
79 		if (strcmp(table[i].option_name, opt) != 0)
80 			continue;
81 		switch (table[i].size) {
82 		case 4:
83 			value = simple_strtoul(val, NULL, 0);
84 			ptr = base + table[i].offset;
85 			*ptr = value;
86 			break;
87 		case 8:
88 			value_l = simple_strtoull(val, NULL, 0);
89 			ptr_l = base + table[i].offset;
90 			*ptr_l = value_l;
91 			break;
92 		default:
93 			printf("Unrecognized size!\n");
94 			break;
95 		}
96 		return 1;
97 	}
98 
99 	return 0;
100 }
101 
fsl_ddr_generic_edit(void * pdata,void * pend,unsigned int element_size,unsigned int element_num,unsigned int value)102 static void fsl_ddr_generic_edit(void *pdata,
103 			   void *pend,
104 			   unsigned int element_size,
105 			   unsigned int element_num,
106 			   unsigned int value)
107 {
108 	char *pcdata = (char *)pdata;		/* BIG ENDIAN ONLY */
109 
110 	pcdata += element_num * element_size;
111 	if ((pcdata + element_size) > (char *) pend) {
112 		printf("trying to write past end of data\n");
113 		return;
114 	}
115 
116 	switch (element_size) {
117 	case 1:
118 		__raw_writeb(value, pcdata);
119 		break;
120 	case 2:
121 		__raw_writew(value, pcdata);
122 		break;
123 	case 4:
124 		__raw_writel(value, pcdata);
125 		break;
126 	default:
127 		printf("unexpected element size %u\n", element_size);
128 		break;
129 	}
130 }
131 
fsl_ddr_spd_edit(fsl_ddr_info_t * pinfo,unsigned int ctrl_num,unsigned int dimm_num,unsigned int element_num,unsigned int value)132 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
133 		       unsigned int ctrl_num,
134 		       unsigned int dimm_num,
135 		       unsigned int element_num,
136 		       unsigned int value)
137 {
138 	generic_spd_eeprom_t *pspd;
139 
140 	pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
141 	fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
142 }
143 
144 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
145 	sizeof((common_timing_params_t *)0)->x, 0}
146 
lowest_common_dimm_parameters_edit(fsl_ddr_info_t * pinfo,unsigned int ctrl_num,const char * optname_str,const char * value_str)147 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
148 					unsigned int ctrl_num,
149 					const char *optname_str,
150 					const char *value_str)
151 {
152 	common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
153 
154 	static const struct options_string options[] = {
155 		COMMON_TIMING(tckmin_x_ps),
156 		COMMON_TIMING(tckmax_ps),
157 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
158 		COMMON_TIMING(taamin_ps),
159 #endif
160 		COMMON_TIMING(trcd_ps),
161 		COMMON_TIMING(trp_ps),
162 		COMMON_TIMING(tras_ps),
163 
164 #ifdef CONFIG_SYS_FSL_DDR4
165 		COMMON_TIMING(trfc1_ps),
166 		COMMON_TIMING(trfc2_ps),
167 		COMMON_TIMING(trfc4_ps),
168 		COMMON_TIMING(trrds_ps),
169 		COMMON_TIMING(trrdl_ps),
170 		COMMON_TIMING(tccdl_ps),
171 		COMMON_TIMING(trfc_slr_ps),
172 #else
173 		COMMON_TIMING(twtr_ps),
174 		COMMON_TIMING(trfc_ps),
175 		COMMON_TIMING(trrd_ps),
176 		COMMON_TIMING(trtp_ps),
177 #endif
178 		COMMON_TIMING(twr_ps),
179 		COMMON_TIMING(trc_ps),
180 		COMMON_TIMING(refresh_rate_ps),
181 		COMMON_TIMING(extended_op_srt),
182 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
183 		COMMON_TIMING(tis_ps),
184 		COMMON_TIMING(tih_ps),
185 		COMMON_TIMING(tds_ps),
186 		COMMON_TIMING(tdh_ps),
187 		COMMON_TIMING(tdqsq_max_ps),
188 		COMMON_TIMING(tqhs_ps),
189 #endif
190 		COMMON_TIMING(ndimms_present),
191 		COMMON_TIMING(lowest_common_spd_caslat),
192 		COMMON_TIMING(highest_common_derated_caslat),
193 		COMMON_TIMING(additive_latency),
194 		COMMON_TIMING(all_dimms_burst_lengths_bitmask),
195 		COMMON_TIMING(all_dimms_registered),
196 		COMMON_TIMING(all_dimms_unbuffered),
197 		COMMON_TIMING(all_dimms_ecc_capable),
198 		COMMON_TIMING(total_mem),
199 		COMMON_TIMING(base_address),
200 	};
201 	static const unsigned int n_opts = ARRAY_SIZE(options);
202 
203 	if (handle_option_table(options, n_opts, p, optname_str, value_str))
204 		return;
205 
206 	printf("Error: couldn't find option string %s\n", optname_str);
207 }
208 
209 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
210 	sizeof((dimm_params_t *)0)->x, 0}
211 #define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
212 	sizeof((dimm_params_t *)0)->x, 1}
213 
fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t * pinfo,unsigned int ctrl_num,unsigned int dimm_num,const char * optname_str,const char * value_str)214 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
215 				   unsigned int ctrl_num,
216 				   unsigned int dimm_num,
217 				   const char *optname_str,
218 				   const char *value_str)
219 {
220 	dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
221 
222 	static const struct options_string options[] = {
223 		DIMM_PARM(n_ranks),
224 		DIMM_PARM(data_width),
225 		DIMM_PARM(primary_sdram_width),
226 		DIMM_PARM(ec_sdram_width),
227 		DIMM_PARM(package_3ds),
228 		DIMM_PARM(registered_dimm),
229 		DIMM_PARM(mirrored_dimm),
230 		DIMM_PARM(device_width),
231 
232 		DIMM_PARM(n_row_addr),
233 		DIMM_PARM(n_col_addr),
234 		DIMM_PARM(edc_config),
235 #ifdef CONFIG_SYS_FSL_DDR4
236 		DIMM_PARM(bank_addr_bits),
237 		DIMM_PARM(bank_group_bits),
238 		DIMM_PARM_HEX(die_density),
239 #else
240 		DIMM_PARM(n_banks_per_sdram_device),
241 #endif
242 		DIMM_PARM(burst_lengths_bitmask),
243 
244 		DIMM_PARM(tckmin_x_ps),
245 		DIMM_PARM(tckmin_x_minus_1_ps),
246 		DIMM_PARM(tckmin_x_minus_2_ps),
247 		DIMM_PARM(tckmax_ps),
248 
249 		DIMM_PARM(caslat_x),
250 		DIMM_PARM(caslat_x_minus_1),
251 		DIMM_PARM(caslat_x_minus_2),
252 
253 		DIMM_PARM(caslat_lowest_derated),
254 
255 		DIMM_PARM(trcd_ps),
256 		DIMM_PARM(trp_ps),
257 		DIMM_PARM(tras_ps),
258 #ifdef CONFIG_SYS_FSL_DDR4
259 		DIMM_PARM(trfc1_ps),
260 		DIMM_PARM(trfc2_ps),
261 		DIMM_PARM(trfc4_ps),
262 		DIMM_PARM(trrds_ps),
263 		DIMM_PARM(trrdl_ps),
264 		DIMM_PARM(tccdl_ps),
265 		DIMM_PARM(trfc_slr_ps),
266 #else
267 		DIMM_PARM(twr_ps),
268 		DIMM_PARM(twtr_ps),
269 		DIMM_PARM(trfc_ps),
270 		DIMM_PARM(trrd_ps),
271 		DIMM_PARM(trtp_ps),
272 #endif
273 		DIMM_PARM(trc_ps),
274 		DIMM_PARM(refresh_rate_ps),
275 		DIMM_PARM(extended_op_srt),
276 
277 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
278 		DIMM_PARM(tis_ps),
279 		DIMM_PARM(tih_ps),
280 		DIMM_PARM(tds_ps),
281 		DIMM_PARM(tdh_ps),
282 		DIMM_PARM(tdqsq_max_ps),
283 		DIMM_PARM(tqhs_ps),
284 #endif
285 #ifdef CONFIG_SYS_FSL_DDR4
286 		DIMM_PARM_HEX(dq_mapping[0]),
287 		DIMM_PARM_HEX(dq_mapping[1]),
288 		DIMM_PARM_HEX(dq_mapping[2]),
289 		DIMM_PARM_HEX(dq_mapping[3]),
290 		DIMM_PARM_HEX(dq_mapping[4]),
291 		DIMM_PARM_HEX(dq_mapping[5]),
292 		DIMM_PARM_HEX(dq_mapping[6]),
293 		DIMM_PARM_HEX(dq_mapping[7]),
294 		DIMM_PARM_HEX(dq_mapping[8]),
295 		DIMM_PARM_HEX(dq_mapping[9]),
296 		DIMM_PARM_HEX(dq_mapping[10]),
297 		DIMM_PARM_HEX(dq_mapping[11]),
298 		DIMM_PARM_HEX(dq_mapping[12]),
299 		DIMM_PARM_HEX(dq_mapping[13]),
300 		DIMM_PARM_HEX(dq_mapping[14]),
301 		DIMM_PARM_HEX(dq_mapping[15]),
302 		DIMM_PARM_HEX(dq_mapping[16]),
303 		DIMM_PARM_HEX(dq_mapping[17]),
304 		DIMM_PARM(dq_mapping_ors),
305 #endif
306 		DIMM_PARM(rank_density),
307 		DIMM_PARM(capacity),
308 		DIMM_PARM(base_address),
309 	};
310 
311 	static const unsigned int n_opts = ARRAY_SIZE(options);
312 
313 	if (handle_option_table(options, n_opts, p, optname_str, value_str))
314 		return;
315 
316 	printf("couldn't find option string %s\n", optname_str);
317 }
318 
print_dimm_parameters(const dimm_params_t * pdimm)319 static void print_dimm_parameters(const dimm_params_t *pdimm)
320 {
321 	static const struct options_string options[] = {
322 		DIMM_PARM(n_ranks),
323 		DIMM_PARM(data_width),
324 		DIMM_PARM(primary_sdram_width),
325 		DIMM_PARM(ec_sdram_width),
326 		DIMM_PARM(package_3ds),
327 		DIMM_PARM(registered_dimm),
328 		DIMM_PARM(mirrored_dimm),
329 		DIMM_PARM(device_width),
330 
331 		DIMM_PARM(n_row_addr),
332 		DIMM_PARM(n_col_addr),
333 		DIMM_PARM(edc_config),
334 #ifdef CONFIG_SYS_FSL_DDR4
335 		DIMM_PARM(bank_addr_bits),
336 		DIMM_PARM(bank_group_bits),
337 		DIMM_PARM_HEX(die_density),
338 #else
339 		DIMM_PARM(n_banks_per_sdram_device),
340 #endif
341 
342 		DIMM_PARM(tckmin_x_ps),
343 		DIMM_PARM(tckmin_x_minus_1_ps),
344 		DIMM_PARM(tckmin_x_minus_2_ps),
345 		DIMM_PARM(tckmax_ps),
346 
347 		DIMM_PARM(caslat_x),
348 		DIMM_PARM_HEX(caslat_x),
349 		DIMM_PARM(taa_ps),
350 		DIMM_PARM(caslat_x_minus_1),
351 		DIMM_PARM(caslat_x_minus_2),
352 		DIMM_PARM(caslat_lowest_derated),
353 
354 		DIMM_PARM(trcd_ps),
355 		DIMM_PARM(trp_ps),
356 		DIMM_PARM(tras_ps),
357 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
358 		DIMM_PARM(tfaw_ps),
359 #endif
360 #ifdef CONFIG_SYS_FSL_DDR4
361 		DIMM_PARM(trfc1_ps),
362 		DIMM_PARM(trfc2_ps),
363 		DIMM_PARM(trfc4_ps),
364 		DIMM_PARM(trrds_ps),
365 		DIMM_PARM(trrdl_ps),
366 		DIMM_PARM(tccdl_ps),
367 		DIMM_PARM(trfc_slr_ps),
368 #else
369 		DIMM_PARM(twr_ps),
370 		DIMM_PARM(twtr_ps),
371 		DIMM_PARM(trfc_ps),
372 		DIMM_PARM(trrd_ps),
373 		DIMM_PARM(trtp_ps),
374 #endif
375 		DIMM_PARM(trc_ps),
376 		DIMM_PARM(refresh_rate_ps),
377 
378 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
379 		DIMM_PARM(tis_ps),
380 		DIMM_PARM(tih_ps),
381 		DIMM_PARM(tds_ps),
382 		DIMM_PARM(tdh_ps),
383 		DIMM_PARM(tdqsq_max_ps),
384 		DIMM_PARM(tqhs_ps),
385 #endif
386 #ifdef CONFIG_SYS_FSL_DDR4
387 		DIMM_PARM_HEX(dq_mapping[0]),
388 		DIMM_PARM_HEX(dq_mapping[1]),
389 		DIMM_PARM_HEX(dq_mapping[2]),
390 		DIMM_PARM_HEX(dq_mapping[3]),
391 		DIMM_PARM_HEX(dq_mapping[4]),
392 		DIMM_PARM_HEX(dq_mapping[5]),
393 		DIMM_PARM_HEX(dq_mapping[6]),
394 		DIMM_PARM_HEX(dq_mapping[7]),
395 		DIMM_PARM_HEX(dq_mapping[8]),
396 		DIMM_PARM_HEX(dq_mapping[9]),
397 		DIMM_PARM_HEX(dq_mapping[10]),
398 		DIMM_PARM_HEX(dq_mapping[11]),
399 		DIMM_PARM_HEX(dq_mapping[12]),
400 		DIMM_PARM_HEX(dq_mapping[13]),
401 		DIMM_PARM_HEX(dq_mapping[14]),
402 		DIMM_PARM_HEX(dq_mapping[15]),
403 		DIMM_PARM_HEX(dq_mapping[16]),
404 		DIMM_PARM_HEX(dq_mapping[17]),
405 		DIMM_PARM(dq_mapping_ors),
406 #endif
407 	};
408 	static const unsigned int n_opts = ARRAY_SIZE(options);
409 
410 	if (pdimm->n_ranks == 0) {
411 		printf("DIMM not present\n");
412 		return;
413 	}
414 	printf("DIMM organization parameters:\n");
415 	printf("module part name = %s\n", pdimm->mpart);
416 	printf("rank_density = %llu bytes (%llu megabytes)\n",
417 	       pdimm->rank_density, pdimm->rank_density / 0x100000);
418 	printf("capacity = %llu bytes (%llu megabytes)\n",
419 	       pdimm->capacity, pdimm->capacity / 0x100000);
420 	printf("burst_lengths_bitmask = %02X\n",
421 	       pdimm->burst_lengths_bitmask);
422 	printf("base_addresss = %llu (%08llX %08llX)\n",
423 	       pdimm->base_address,
424 	       (pdimm->base_address >> 32),
425 	       pdimm->base_address & 0xFFFFFFFF);
426 	print_option_table(options, n_opts, pdimm);
427 }
428 
print_lowest_common_dimm_parameters(const common_timing_params_t * plcd_dimm_params)429 static void print_lowest_common_dimm_parameters(
430 		const common_timing_params_t *plcd_dimm_params)
431 {
432 	static const struct options_string options[] = {
433 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
434 		COMMON_TIMING(taamin_ps),
435 #endif
436 		COMMON_TIMING(trcd_ps),
437 		COMMON_TIMING(trp_ps),
438 		COMMON_TIMING(tras_ps),
439 #ifdef CONFIG_SYS_FSL_DDR4
440 		COMMON_TIMING(trfc1_ps),
441 		COMMON_TIMING(trfc2_ps),
442 		COMMON_TIMING(trfc4_ps),
443 		COMMON_TIMING(trrds_ps),
444 		COMMON_TIMING(trrdl_ps),
445 		COMMON_TIMING(tccdl_ps),
446 		COMMON_TIMING(trfc_slr_ps),
447 #else
448 		COMMON_TIMING(twtr_ps),
449 		COMMON_TIMING(trfc_ps),
450 		COMMON_TIMING(trrd_ps),
451 		COMMON_TIMING(trtp_ps),
452 #endif
453 		COMMON_TIMING(twr_ps),
454 		COMMON_TIMING(trc_ps),
455 		COMMON_TIMING(refresh_rate_ps),
456 		COMMON_TIMING(extended_op_srt),
457 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
458 		COMMON_TIMING(tis_ps),
459 		COMMON_TIMING(tih_ps),
460 		COMMON_TIMING(tds_ps),
461 		COMMON_TIMING(tdh_ps),
462 		COMMON_TIMING(tdqsq_max_ps),
463 		COMMON_TIMING(tqhs_ps),
464 #endif
465 		COMMON_TIMING(lowest_common_spd_caslat),
466 		COMMON_TIMING(highest_common_derated_caslat),
467 		COMMON_TIMING(additive_latency),
468 		COMMON_TIMING(ndimms_present),
469 		COMMON_TIMING(all_dimms_registered),
470 		COMMON_TIMING(all_dimms_unbuffered),
471 		COMMON_TIMING(all_dimms_ecc_capable),
472 	};
473 	static const unsigned int n_opts = ARRAY_SIZE(options);
474 
475 	/* Clock frequencies */
476 	printf("tckmin_x_ps = %u (%u MHz)\n",
477 	       plcd_dimm_params->tckmin_x_ps,
478 	       picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
479 	printf("tckmax_ps = %u (%u MHz)\n",
480 	       plcd_dimm_params->tckmax_ps,
481 	       picos_to_mhz(plcd_dimm_params->tckmax_ps));
482 	printf("all_dimms_burst_lengths_bitmask = %02X\n",
483 	       plcd_dimm_params->all_dimms_burst_lengths_bitmask);
484 
485 	print_option_table(options, n_opts, plcd_dimm_params);
486 
487 	printf("total_mem = %llu (%llu megabytes)\n",
488 	       plcd_dimm_params->total_mem,
489 	       plcd_dimm_params->total_mem / 0x100000);
490 	printf("base_address = %llu (%llu megabytes)\n",
491 	       plcd_dimm_params->base_address,
492 	       plcd_dimm_params->base_address / 0x100000);
493 }
494 
495 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
496 	sizeof((memctl_options_t *)0)->x, 0}
497 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
498 	offsetof(memctl_options_t, cs_local_opts[x].y), \
499 	sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
500 
fsl_ddr_options_edit(fsl_ddr_info_t * pinfo,unsigned int ctl_num,const char * optname_str,const char * value_str)501 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
502 			   unsigned int ctl_num,
503 			   const char *optname_str,
504 			   const char *value_str)
505 {
506 	memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
507 	/*
508 	 * This array all on the stack and *computed* each time this
509 	 * function is rung.
510 	 */
511 	static const struct options_string options[] = {
512 		CTRL_OPTIONS_CS(0, odt_rd_cfg),
513 		CTRL_OPTIONS_CS(0, odt_wr_cfg),
514 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
515 		CTRL_OPTIONS_CS(1, odt_rd_cfg),
516 		CTRL_OPTIONS_CS(1, odt_wr_cfg),
517 #endif
518 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
519 		CTRL_OPTIONS_CS(2, odt_rd_cfg),
520 		CTRL_OPTIONS_CS(2, odt_wr_cfg),
521 #endif
522 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
523 		CTRL_OPTIONS_CS(3, odt_rd_cfg),
524 		CTRL_OPTIONS_CS(3, odt_wr_cfg),
525 #endif
526 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
527 		CTRL_OPTIONS_CS(0, odt_rtt_norm),
528 		CTRL_OPTIONS_CS(0, odt_rtt_wr),
529 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
530 		CTRL_OPTIONS_CS(1, odt_rtt_norm),
531 		CTRL_OPTIONS_CS(1, odt_rtt_wr),
532 #endif
533 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
534 		CTRL_OPTIONS_CS(2, odt_rtt_norm),
535 		CTRL_OPTIONS_CS(2, odt_rtt_wr),
536 #endif
537 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
538 		CTRL_OPTIONS_CS(3, odt_rtt_norm),
539 		CTRL_OPTIONS_CS(3, odt_rtt_wr),
540 #endif
541 #endif
542 		CTRL_OPTIONS(memctl_interleaving),
543 		CTRL_OPTIONS(memctl_interleaving_mode),
544 		CTRL_OPTIONS(ba_intlv_ctl),
545 		CTRL_OPTIONS(ecc_mode),
546 		CTRL_OPTIONS(ecc_init_using_memctl),
547 		CTRL_OPTIONS(dqs_config),
548 		CTRL_OPTIONS(self_refresh_in_sleep),
549 		CTRL_OPTIONS(dynamic_power),
550 		CTRL_OPTIONS(data_bus_width),
551 		CTRL_OPTIONS(burst_length),
552 		CTRL_OPTIONS(cas_latency_override),
553 		CTRL_OPTIONS(cas_latency_override_value),
554 		CTRL_OPTIONS(use_derated_caslat),
555 		CTRL_OPTIONS(additive_latency_override),
556 		CTRL_OPTIONS(additive_latency_override_value),
557 		CTRL_OPTIONS(clk_adjust),
558 		CTRL_OPTIONS(cpo_override),
559 		CTRL_OPTIONS(write_data_delay),
560 		CTRL_OPTIONS(half_strength_driver_enable),
561 
562 		/*
563 		 * These can probably be changed to 2T_EN and 3T_EN
564 		 * (using a leading numerical character) without problem
565 		 */
566 		CTRL_OPTIONS(twot_en),
567 		CTRL_OPTIONS(threet_en),
568 		CTRL_OPTIONS(mirrored_dimm),
569 		CTRL_OPTIONS(ap_en),
570 		CTRL_OPTIONS(x4_en),
571 		CTRL_OPTIONS(package_3ds),
572 		CTRL_OPTIONS(bstopre),
573 		CTRL_OPTIONS(wrlvl_override),
574 		CTRL_OPTIONS(wrlvl_sample),
575 		CTRL_OPTIONS(wrlvl_start),
576 		CTRL_OPTIONS(cswl_override),
577 		CTRL_OPTIONS(rcw_override),
578 		CTRL_OPTIONS(rcw_1),
579 		CTRL_OPTIONS(rcw_2),
580 		CTRL_OPTIONS(rcw_3),
581 		CTRL_OPTIONS(ddr_cdr1),
582 		CTRL_OPTIONS(ddr_cdr2),
583 		CTRL_OPTIONS(tfaw_window_four_activates_ps),
584 		CTRL_OPTIONS(trwt_override),
585 		CTRL_OPTIONS(trwt),
586 		CTRL_OPTIONS(rtt_override),
587 		CTRL_OPTIONS(rtt_override_value),
588 		CTRL_OPTIONS(rtt_wr_override_value),
589 	};
590 
591 	static const unsigned int n_opts = ARRAY_SIZE(options);
592 
593 	if (handle_option_table(options, n_opts, p,
594 					optname_str, value_str))
595 		return;
596 
597 	printf("couldn't find option string %s\n", optname_str);
598 }
599 
600 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
601 	sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
602 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
603 	offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
604 	sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
605 
print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t * ddr)606 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
607 {
608 	unsigned int i;
609 	static const struct options_string options[] = {
610 		CFG_REGS_CS(0, bnds),
611 		CFG_REGS_CS(0, config),
612 		CFG_REGS_CS(0, config_2),
613 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
614 		CFG_REGS_CS(1, bnds),
615 		CFG_REGS_CS(1, config),
616 		CFG_REGS_CS(1, config_2),
617 #endif
618 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
619 		CFG_REGS_CS(2, bnds),
620 		CFG_REGS_CS(2, config),
621 		CFG_REGS_CS(2, config_2),
622 #endif
623 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
624 		CFG_REGS_CS(3, bnds),
625 		CFG_REGS_CS(3, config),
626 		CFG_REGS_CS(3, config_2),
627 #endif
628 		CFG_REGS(timing_cfg_3),
629 		CFG_REGS(timing_cfg_0),
630 		CFG_REGS(timing_cfg_1),
631 		CFG_REGS(timing_cfg_2),
632 		CFG_REGS(ddr_sdram_cfg),
633 		CFG_REGS(ddr_sdram_cfg_2),
634 		CFG_REGS(ddr_sdram_cfg_3),
635 		CFG_REGS(ddr_sdram_mode),
636 		CFG_REGS(ddr_sdram_mode_2),
637 		CFG_REGS(ddr_sdram_mode_3),
638 		CFG_REGS(ddr_sdram_mode_4),
639 		CFG_REGS(ddr_sdram_mode_5),
640 		CFG_REGS(ddr_sdram_mode_6),
641 		CFG_REGS(ddr_sdram_mode_7),
642 		CFG_REGS(ddr_sdram_mode_8),
643 #ifdef CONFIG_SYS_FSL_DDR4
644 		CFG_REGS(ddr_sdram_mode_9),
645 		CFG_REGS(ddr_sdram_mode_10),
646 		CFG_REGS(ddr_sdram_mode_11),
647 		CFG_REGS(ddr_sdram_mode_12),
648 		CFG_REGS(ddr_sdram_mode_13),
649 		CFG_REGS(ddr_sdram_mode_14),
650 		CFG_REGS(ddr_sdram_mode_15),
651 		CFG_REGS(ddr_sdram_mode_16),
652 #endif
653 		CFG_REGS(ddr_sdram_interval),
654 		CFG_REGS(ddr_data_init),
655 		CFG_REGS(ddr_sdram_clk_cntl),
656 		CFG_REGS(ddr_init_addr),
657 		CFG_REGS(ddr_init_ext_addr),
658 		CFG_REGS(timing_cfg_4),
659 		CFG_REGS(timing_cfg_5),
660 #ifdef CONFIG_SYS_FSL_DDR4
661 		CFG_REGS(timing_cfg_6),
662 		CFG_REGS(timing_cfg_7),
663 		CFG_REGS(timing_cfg_8),
664 		CFG_REGS(timing_cfg_9),
665 #endif
666 		CFG_REGS(ddr_zq_cntl),
667 		CFG_REGS(ddr_wrlvl_cntl),
668 		CFG_REGS(ddr_wrlvl_cntl_2),
669 		CFG_REGS(ddr_wrlvl_cntl_3),
670 		CFG_REGS(ddr_sr_cntr),
671 		CFG_REGS(ddr_sdram_rcw_1),
672 		CFG_REGS(ddr_sdram_rcw_2),
673 		CFG_REGS(ddr_sdram_rcw_3),
674 		CFG_REGS(ddr_cdr1),
675 		CFG_REGS(ddr_cdr2),
676 		CFG_REGS(dq_map_0),
677 		CFG_REGS(dq_map_1),
678 		CFG_REGS(dq_map_2),
679 		CFG_REGS(dq_map_3),
680 		CFG_REGS(err_disable),
681 		CFG_REGS(err_int_en),
682 		CFG_REGS(ddr_eor),
683 	};
684 	static const unsigned int n_opts = ARRAY_SIZE(options);
685 
686 	print_option_table(options, n_opts, ddr);
687 
688 	for (i = 0; i < 64; i++)
689 		printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
690 }
691 
fsl_ddr_regs_edit(fsl_ddr_info_t * pinfo,unsigned int ctrl_num,const char * regname,const char * value_str)692 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
693 			unsigned int ctrl_num,
694 			const char *regname,
695 			const char *value_str)
696 {
697 	unsigned int i;
698 	fsl_ddr_cfg_regs_t *ddr;
699 	char buf[20];
700 	static const struct options_string options[] = {
701 		CFG_REGS_CS(0, bnds),
702 		CFG_REGS_CS(0, config),
703 		CFG_REGS_CS(0, config_2),
704 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
705 		CFG_REGS_CS(1, bnds),
706 		CFG_REGS_CS(1, config),
707 		CFG_REGS_CS(1, config_2),
708 #endif
709 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
710 		CFG_REGS_CS(2, bnds),
711 		CFG_REGS_CS(2, config),
712 		CFG_REGS_CS(2, config_2),
713 #endif
714 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
715 		CFG_REGS_CS(3, bnds),
716 		CFG_REGS_CS(3, config),
717 		CFG_REGS_CS(3, config_2),
718 #endif
719 		CFG_REGS(timing_cfg_3),
720 		CFG_REGS(timing_cfg_0),
721 		CFG_REGS(timing_cfg_1),
722 		CFG_REGS(timing_cfg_2),
723 		CFG_REGS(ddr_sdram_cfg),
724 		CFG_REGS(ddr_sdram_cfg_2),
725 		CFG_REGS(ddr_sdram_cfg_3),
726 		CFG_REGS(ddr_sdram_mode),
727 		CFG_REGS(ddr_sdram_mode_2),
728 		CFG_REGS(ddr_sdram_mode_3),
729 		CFG_REGS(ddr_sdram_mode_4),
730 		CFG_REGS(ddr_sdram_mode_5),
731 		CFG_REGS(ddr_sdram_mode_6),
732 		CFG_REGS(ddr_sdram_mode_7),
733 		CFG_REGS(ddr_sdram_mode_8),
734 #ifdef CONFIG_SYS_FSL_DDR4
735 		CFG_REGS(ddr_sdram_mode_9),
736 		CFG_REGS(ddr_sdram_mode_10),
737 		CFG_REGS(ddr_sdram_mode_11),
738 		CFG_REGS(ddr_sdram_mode_12),
739 		CFG_REGS(ddr_sdram_mode_13),
740 		CFG_REGS(ddr_sdram_mode_14),
741 		CFG_REGS(ddr_sdram_mode_15),
742 		CFG_REGS(ddr_sdram_mode_16),
743 #endif
744 		CFG_REGS(ddr_sdram_interval),
745 		CFG_REGS(ddr_data_init),
746 		CFG_REGS(ddr_sdram_clk_cntl),
747 		CFG_REGS(ddr_init_addr),
748 		CFG_REGS(ddr_init_ext_addr),
749 		CFG_REGS(timing_cfg_4),
750 		CFG_REGS(timing_cfg_5),
751 #ifdef CONFIG_SYS_FSL_DDR4
752 		CFG_REGS(timing_cfg_6),
753 		CFG_REGS(timing_cfg_7),
754 		CFG_REGS(timing_cfg_8),
755 		CFG_REGS(timing_cfg_9),
756 #endif
757 		CFG_REGS(ddr_zq_cntl),
758 		CFG_REGS(ddr_wrlvl_cntl),
759 		CFG_REGS(ddr_wrlvl_cntl_2),
760 		CFG_REGS(ddr_wrlvl_cntl_3),
761 		CFG_REGS(ddr_sr_cntr),
762 		CFG_REGS(ddr_sdram_rcw_1),
763 		CFG_REGS(ddr_sdram_rcw_2),
764 		CFG_REGS(ddr_sdram_rcw_3),
765 		CFG_REGS(ddr_cdr1),
766 		CFG_REGS(ddr_cdr2),
767 		CFG_REGS(dq_map_0),
768 		CFG_REGS(dq_map_1),
769 		CFG_REGS(dq_map_2),
770 		CFG_REGS(dq_map_3),
771 		CFG_REGS(err_disable),
772 		CFG_REGS(err_int_en),
773 		CFG_REGS(ddr_sdram_rcw_2),
774 		CFG_REGS(ddr_sdram_rcw_2),
775 		CFG_REGS(ddr_eor),
776 	};
777 	static const unsigned int n_opts = ARRAY_SIZE(options);
778 
779 	debug("fsl_ddr_regs_edit: ctrl_num = %u, "
780 		"regname = %s, value = %s\n",
781 		ctrl_num, regname, value_str);
782 	if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
783 		return;
784 
785 	ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
786 
787 	if (handle_option_table(options, n_opts, ddr, regname, value_str))
788 		return;
789 
790 	for (i = 0; i < 64; i++) {
791 		unsigned int value = simple_strtoul(value_str, NULL, 0);
792 		sprintf(buf, "debug_%u", i + 1);
793 		if (strcmp(buf, regname) == 0) {
794 			ddr->debug[i] = value;
795 			return;
796 		}
797 	}
798 	printf("Error: couldn't find register string %s\n", regname);
799 }
800 
801 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
802 	sizeof((memctl_options_t *)0)->x, 1}
803 
print_memctl_options(const memctl_options_t * popts)804 static void print_memctl_options(const memctl_options_t *popts)
805 {
806 	static const struct options_string options[] = {
807 		CTRL_OPTIONS_CS(0, odt_rd_cfg),
808 		CTRL_OPTIONS_CS(0, odt_wr_cfg),
809 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
810 		CTRL_OPTIONS_CS(1, odt_rd_cfg),
811 		CTRL_OPTIONS_CS(1, odt_wr_cfg),
812 #endif
813 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
814 		CTRL_OPTIONS_CS(2, odt_rd_cfg),
815 		CTRL_OPTIONS_CS(2, odt_wr_cfg),
816 #endif
817 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
818 		CTRL_OPTIONS_CS(3, odt_rd_cfg),
819 		CTRL_OPTIONS_CS(3, odt_wr_cfg),
820 #endif
821 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
822 		CTRL_OPTIONS_CS(0, odt_rtt_norm),
823 		CTRL_OPTIONS_CS(0, odt_rtt_wr),
824 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
825 		CTRL_OPTIONS_CS(1, odt_rtt_norm),
826 		CTRL_OPTIONS_CS(1, odt_rtt_wr),
827 #endif
828 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
829 		CTRL_OPTIONS_CS(2, odt_rtt_norm),
830 		CTRL_OPTIONS_CS(2, odt_rtt_wr),
831 #endif
832 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
833 		CTRL_OPTIONS_CS(3, odt_rtt_norm),
834 		CTRL_OPTIONS_CS(3, odt_rtt_wr),
835 #endif
836 #endif
837 		CTRL_OPTIONS(memctl_interleaving),
838 		CTRL_OPTIONS(memctl_interleaving_mode),
839 		CTRL_OPTIONS_HEX(ba_intlv_ctl),
840 		CTRL_OPTIONS(ecc_mode),
841 		CTRL_OPTIONS(ecc_init_using_memctl),
842 		CTRL_OPTIONS(dqs_config),
843 		CTRL_OPTIONS(self_refresh_in_sleep),
844 		CTRL_OPTIONS(dynamic_power),
845 		CTRL_OPTIONS(data_bus_width),
846 		CTRL_OPTIONS(burst_length),
847 		CTRL_OPTIONS(cas_latency_override),
848 		CTRL_OPTIONS(cas_latency_override_value),
849 		CTRL_OPTIONS(use_derated_caslat),
850 		CTRL_OPTIONS(additive_latency_override),
851 		CTRL_OPTIONS(additive_latency_override_value),
852 		CTRL_OPTIONS(clk_adjust),
853 		CTRL_OPTIONS(cpo_override),
854 		CTRL_OPTIONS(write_data_delay),
855 		CTRL_OPTIONS(half_strength_driver_enable),
856 		/*
857 		 * These can probably be changed to 2T_EN and 3T_EN
858 		 * (using a leading numerical character) without problem
859 		 */
860 		CTRL_OPTIONS(twot_en),
861 		CTRL_OPTIONS(threet_en),
862 		CTRL_OPTIONS(registered_dimm_en),
863 		CTRL_OPTIONS(mirrored_dimm),
864 		CTRL_OPTIONS(ap_en),
865 		CTRL_OPTIONS(x4_en),
866 		CTRL_OPTIONS(package_3ds),
867 		CTRL_OPTIONS(bstopre),
868 		CTRL_OPTIONS(wrlvl_override),
869 		CTRL_OPTIONS(wrlvl_sample),
870 		CTRL_OPTIONS(wrlvl_start),
871 		CTRL_OPTIONS_HEX(cswl_override),
872 		CTRL_OPTIONS(rcw_override),
873 		CTRL_OPTIONS_HEX(rcw_1),
874 		CTRL_OPTIONS_HEX(rcw_2),
875 		CTRL_OPTIONS_HEX(rcw_3),
876 		CTRL_OPTIONS_HEX(ddr_cdr1),
877 		CTRL_OPTIONS_HEX(ddr_cdr2),
878 		CTRL_OPTIONS(tfaw_window_four_activates_ps),
879 		CTRL_OPTIONS(trwt_override),
880 		CTRL_OPTIONS(trwt),
881 		CTRL_OPTIONS(rtt_override),
882 		CTRL_OPTIONS(rtt_override_value),
883 		CTRL_OPTIONS(rtt_wr_override_value),
884 	};
885 	static const unsigned int n_opts = ARRAY_SIZE(options);
886 
887 	print_option_table(options, n_opts, popts);
888 }
889 
890 #ifdef CONFIG_SYS_FSL_DDR1
ddr1_spd_dump(const ddr1_spd_eeprom_t * spd)891 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
892 {
893 	unsigned int i;
894 
895 	printf("%-3d    : %02x %s\n", 0, spd->info_size,
896 	       " spd->info_size,   *  0 # bytes written into serial memory *");
897 	printf("%-3d    : %02x %s\n", 1, spd->chip_size,
898 	       " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
899 	printf("%-3d    : %02x %s\n", 2, spd->mem_type,
900 	       " spd->mem_type,    *  2 Fundamental memory type *");
901 	printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
902 	       " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
903 	printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
904 	       " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
905 	printf("%-3d    : %02x %s\n", 5, spd->nrows,
906 	       " spd->nrows        *  5 # of DIMM Banks *");
907 	printf("%-3d    : %02x %s\n", 6, spd->dataw_lsb,
908 	       " spd->dataw_lsb,   *  6 Data Width lsb of this assembly *");
909 	printf("%-3d    : %02x %s\n", 7, spd->dataw_msb,
910 	       " spd->dataw_msb,   *  7 Data Width msb of this assembly *");
911 	printf("%-3d    : %02x %s\n", 8, spd->voltage,
912 	       " spd->voltage,     *  8 Voltage intf std of this assembly *");
913 	printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
914 	       " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
915 	printf("%-3d    : %02x %s\n", 10, spd->clk_access,
916 	       " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
917 	printf("%-3d    : %02x %s\n", 11, spd->config,
918 	       " spd->config,      * 11 DIMM Configuration type *");
919 	printf("%-3d    : %02x %s\n", 12, spd->refresh,
920 	       " spd->refresh,     * 12 Refresh Rate/Type *");
921 	printf("%-3d    : %02x %s\n", 13, spd->primw,
922 	       " spd->primw,       * 13 Primary SDRAM Width *");
923 	printf("%-3d    : %02x %s\n", 14, spd->ecw,
924 	       " spd->ecw,         * 14 Error Checking SDRAM width *");
925 	printf("%-3d    : %02x %s\n", 15, spd->min_delay,
926 	       " spd->min_delay,   * 15 Back to Back Random Access *");
927 	printf("%-3d    : %02x %s\n", 16, spd->burstl,
928 	       " spd->burstl,      * 16 Burst Lengths Supported *");
929 	printf("%-3d    : %02x %s\n", 17, spd->nbanks,
930 	       " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
931 	printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
932 	       " spd->cas_lat,     * 18 CAS# Latencies Supported *");
933 	printf("%-3d    : %02x %s\n", 19, spd->cs_lat,
934 	       " spd->cs_lat,      * 19 Chip Select Latency *");
935 	printf("%-3d    : %02x %s\n", 20, spd->write_lat,
936 	       " spd->write_lat,   * 20 Write Latency/Recovery *");
937 	printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
938 	       " spd->mod_attr,    * 21 SDRAM Module Attributes *");
939 	printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
940 	       " spd->dev_attr,    * 22 SDRAM Device Attributes *");
941 	printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
942 	       " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
943 	printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
944 	       " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
945 	printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
946 	       " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
947 	printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
948 	       " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
949 	printf("%-3d    : %02x %s\n", 27, spd->trp,
950 	       " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
951 	printf("%-3d    : %02x %s\n", 28, spd->trrd,
952 	       " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
953 	printf("%-3d    : %02x %s\n", 29, spd->trcd,
954 	       " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
955 	printf("%-3d    : %02x %s\n", 30, spd->tras,
956 	       " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
957 	printf("%-3d    : %02x %s\n", 31, spd->bank_dens,
958 	       " spd->bank_dens,   * 31 Density of each bank on module *");
959 	printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
960 	       " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
961 	printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
962 	       " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
963 	printf("%-3d    : %02x %s\n", 34, spd->data_setup,
964 	       " spd->data_setup,  * 34 Data signal input setup time *");
965 	printf("%-3d    : %02x %s\n", 35, spd->data_hold,
966 	       " spd->data_hold,   * 35 Data signal input hold time *");
967 	printf("%-3d    : %02x %s\n", 36, spd->res_36_40[0],
968 	       " spd->res_36_40[0], * 36 Reserved / tWR *");
969 	printf("%-3d    : %02x %s\n", 37, spd->res_36_40[1],
970 	       " spd->res_36_40[1], * 37 Reserved / tWTR *");
971 	printf("%-3d    : %02x %s\n", 38, spd->res_36_40[2],
972 	       " spd->res_36_40[2], * 38 Reserved / tRTP *");
973 	printf("%-3d    : %02x %s\n", 39, spd->res_36_40[3],
974 	       " spd->res_36_40[3], * 39 Reserved / mem_probe *");
975 	printf("%-3d    : %02x %s\n", 40, spd->res_36_40[4],
976 	       " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
977 	printf("%-3d    : %02x %s\n", 41, spd->trc,
978 	       " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
979 	printf("%-3d    : %02x %s\n", 42, spd->trfc,
980 	       " spd->trfc,        * 42 Min Auto to Active period tRFC *");
981 	printf("%-3d    : %02x %s\n", 43, spd->tckmax,
982 	       " spd->tckmax,      * 43 Max device cycle time tCKmax *");
983 	printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
984 	       " spd->tdqsq,       * 44 Max DQS to DQ skew *");
985 	printf("%-3d    : %02x %s\n", 45, spd->tqhs,
986 	       " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
987 	printf("%-3d    : %02x %s\n", 46, spd->res_46,
988 	       " spd->res_46,  * 46 Reserved/ PLL Relock time *");
989 	printf("%-3d    : %02x %s\n", 47, spd->dimm_height,
990 	       " spd->dimm_height  * 47 SDRAM DIMM Height *");
991 
992 	printf("%-3d-%3d: ",  48, 61);
993 
994 	for (i = 0; i < 14; i++)
995 		printf("%02x", spd->res_48_61[i]);
996 
997 	printf(" * 48-61 IDD in SPD and Reserved space *\n");
998 
999 	printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
1000 	       " spd->spd_rev,     * 62 SPD Data Revision Code *");
1001 	printf("%-3d    : %02x %s\n", 63, spd->cksum,
1002 	       " spd->cksum,       * 63 Checksum for bytes 0-62 *");
1003 	printf("%-3d-%3d: ",  64, 71);
1004 
1005 	for (i = 0; i < 8; i++)
1006 		printf("%02x", spd->mid[i]);
1007 
1008 	printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1009 	printf("%-3d    : %02x %s\n", 72, spd->mloc,
1010 	       " spd->mloc,        * 72 Manufacturing Location *");
1011 
1012 	printf("%-3d-%3d: >>",  73, 90);
1013 
1014 	for (i = 0; i < 18; i++)
1015 		printf("%c", spd->mpart[i]);
1016 
1017 	printf("<<* 73 Manufacturer's Part Number *\n");
1018 
1019 	printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1020 	       "* 91 Revision Code *");
1021 	printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1022 	       "* 93 Manufacturing Date *");
1023 	printf("%-3d-%3d: ", 95, 98);
1024 
1025 	for (i = 0; i < 4; i++)
1026 		printf("%02x", spd->sernum[i]);
1027 
1028 	printf("* 95 Assembly Serial Number *\n");
1029 
1030 	printf("%-3d-%3d: ", 99, 127);
1031 
1032 	for (i = 0; i < 27; i++)
1033 		printf("%02x", spd->mspec[i]);
1034 
1035 	printf("* 99 Manufacturer Specific Data *\n");
1036 }
1037 #endif
1038 
1039 #ifdef CONFIG_SYS_FSL_DDR2
ddr2_spd_dump(const ddr2_spd_eeprom_t * spd)1040 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
1041 {
1042 	unsigned int i;
1043 
1044 	printf("%-3d    : %02x %s\n", 0, spd->info_size,
1045 	       " spd->info_size,   *  0 # bytes written into serial memory *");
1046 	printf("%-3d    : %02x %s\n", 1, spd->chip_size,
1047 	       " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
1048 	printf("%-3d    : %02x %s\n", 2, spd->mem_type,
1049 	       " spd->mem_type,    *  2 Fundamental memory type *");
1050 	printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
1051 	       " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
1052 	printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
1053 	       " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
1054 	printf("%-3d    : %02x %s\n", 5, spd->mod_ranks,
1055 	       " spd->mod_ranks    *  5 # of Module Rows on this assembly *");
1056 	printf("%-3d    : %02x %s\n", 6, spd->dataw,
1057 	       " spd->dataw,       *  6 Data Width of this assembly *");
1058 	printf("%-3d    : %02x %s\n", 7, spd->res_7,
1059 	       " spd->res_7,       *  7 Reserved *");
1060 	printf("%-3d    : %02x %s\n", 8, spd->voltage,
1061 	       " spd->voltage,     *  8 Voltage intf std of this assembly *");
1062 	printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
1063 	       " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
1064 	printf("%-3d    : %02x %s\n", 10, spd->clk_access,
1065 	       " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
1066 	printf("%-3d    : %02x %s\n", 11, spd->config,
1067 	       " spd->config,      * 11 DIMM Configuration type *");
1068 	printf("%-3d    : %02x %s\n", 12, spd->refresh,
1069 	       " spd->refresh,     * 12 Refresh Rate/Type *");
1070 	printf("%-3d    : %02x %s\n", 13, spd->primw,
1071 	       " spd->primw,       * 13 Primary SDRAM Width *");
1072 	printf("%-3d    : %02x %s\n", 14, spd->ecw,
1073 	       " spd->ecw,         * 14 Error Checking SDRAM width *");
1074 	printf("%-3d    : %02x %s\n", 15, spd->res_15,
1075 	       " spd->res_15,      * 15 Reserved *");
1076 	printf("%-3d    : %02x %s\n", 16, spd->burstl,
1077 	       " spd->burstl,      * 16 Burst Lengths Supported *");
1078 	printf("%-3d    : %02x %s\n", 17, spd->nbanks,
1079 	       " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
1080 	printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
1081 	       " spd->cas_lat,     * 18 CAS# Latencies Supported *");
1082 	printf("%-3d    : %02x %s\n", 19, spd->mech_char,
1083 	       " spd->mech_char,   * 19 Mechanical Characteristics *");
1084 	printf("%-3d    : %02x %s\n", 20, spd->dimm_type,
1085 	       " spd->dimm_type,   * 20 DIMM type *");
1086 	printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
1087 	       " spd->mod_attr,    * 21 SDRAM Module Attributes *");
1088 	printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
1089 	       " spd->dev_attr,    * 22 SDRAM Device Attributes *");
1090 	printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
1091 	       " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
1092 	printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
1093 	       " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
1094 	printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
1095 	       " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
1096 	printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
1097 	       " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
1098 	printf("%-3d    : %02x %s\n", 27, spd->trp,
1099 	       " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
1100 	printf("%-3d    : %02x %s\n", 28, spd->trrd,
1101 	       " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
1102 	printf("%-3d    : %02x %s\n", 29, spd->trcd,
1103 	       " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
1104 	printf("%-3d    : %02x %s\n", 30, spd->tras,
1105 	       " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
1106 	printf("%-3d    : %02x %s\n", 31, spd->rank_dens,
1107 	       " spd->rank_dens,   * 31 Density of each rank on module *");
1108 	printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
1109 	       " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
1110 	printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
1111 	       " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
1112 	printf("%-3d    : %02x %s\n", 34, spd->data_setup,
1113 	       " spd->data_setup,  * 34 Data signal input setup time *");
1114 	printf("%-3d    : %02x %s\n", 35, spd->data_hold,
1115 	       " spd->data_hold,   * 35 Data signal input hold time *");
1116 	printf("%-3d    : %02x %s\n", 36, spd->twr,
1117 	       " spd->twr,         * 36 Write Recovery time tWR *");
1118 	printf("%-3d    : %02x %s\n", 37, spd->twtr,
1119 	       " spd->twtr,        * 37 Int write to read delay tWTR *");
1120 	printf("%-3d    : %02x %s\n", 38, spd->trtp,
1121 	       " spd->trtp,        * 38 Int read to precharge delay tRTP *");
1122 	printf("%-3d    : %02x %s\n", 39, spd->mem_probe,
1123 	       " spd->mem_probe,   * 39 Mem analysis probe characteristics *");
1124 	printf("%-3d    : %02x %s\n", 40, spd->trctrfc_ext,
1125 	       " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
1126 	printf("%-3d    : %02x %s\n", 41, spd->trc,
1127 	       " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
1128 	printf("%-3d    : %02x %s\n", 42, spd->trfc,
1129 	       " spd->trfc,        * 42 Min Auto to Active period tRFC *");
1130 	printf("%-3d    : %02x %s\n", 43, spd->tckmax,
1131 	       " spd->tckmax,      * 43 Max device cycle time tCKmax *");
1132 	printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
1133 	       " spd->tdqsq,       * 44 Max DQS to DQ skew *");
1134 	printf("%-3d    : %02x %s\n", 45, spd->tqhs,
1135 	       " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
1136 	printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
1137 	       " spd->pll_relock,  * 46 PLL Relock time *");
1138 	printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
1139 	       " spd->t_casemax,    * 47 t_casemax *");
1140 	printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
1141 	       " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
1142 	       "from Top (Case) to Ambient (Psi T-A DRAM) *");
1143 	printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
1144 	       " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
1145 	       "Ambient due to Activate-Precharge/Mode Bits "
1146 	       "(DT0/Mode Bits) *)");
1147 	printf("%-3d    : %02x %s\n", 50, spd->dt2n_dt2q,
1148 	       " spd->dt2n_dt2q,   * 50 DRAM Case Temperature Rise from "
1149 	       "Ambient due to Precharge/Quiet Standby "
1150 	       "(DT2N/DT2Q) *");
1151 	printf("%-3d    : %02x %s\n", 51, spd->dt2p,
1152 	       " spd->dt2p,        * 51 DRAM Case Temperature Rise from "
1153 	       "Ambient due to Precharge Power-Down (DT2P) *");
1154 	printf("%-3d    : %02x %s\n", 52, spd->dt3n,
1155 	       " spd->dt3n,        * 52 DRAM Case Temperature Rise from "
1156 	       "Ambient due to Active Standby (DT3N) *");
1157 	printf("%-3d    : %02x %s\n", 53, spd->dt3pfast,
1158 	       " spd->dt3pfast,    * 53 DRAM Case Temperature Rise from "
1159 	       "Ambient due to Active Power-Down with Fast PDN Exit "
1160 	       "(DT3Pfast) *");
1161 	printf("%-3d    : %02x %s\n", 54, spd->dt3pslow,
1162 	       " spd->dt3pslow,    * 54 DRAM Case Temperature Rise from "
1163 	       "Ambient due to Active Power-Down with Slow PDN Exit "
1164 	       "(DT3Pslow) *");
1165 	printf("%-3d    : %02x %s\n", 55, spd->dt4r_dt4r4w,
1166 	       " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
1167 	       "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
1168 	       "(DT4R/DT4R4W Mode Bit) *");
1169 	printf("%-3d    : %02x %s\n", 56, spd->dt5b,
1170 	       " spd->dt5b,        * 56 DRAM Case Temperature Rise from "
1171 	       "Ambient due to Burst Refresh (DT5B) *");
1172 	printf("%-3d    : %02x %s\n", 57, spd->dt7,
1173 	       " spd->dt7,         * 57 DRAM Case Temperature Rise from "
1174 	       "Ambient due to Bank Interleave Reads with "
1175 	       "Auto-Precharge (DT7) *");
1176 	printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
1177 	       " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
1178 	       " Top (Case) to Ambient (Psi T-A PLL) *");
1179 	printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
1180 	       " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
1181 	       " from Top (Case) to Ambient (Psi T-A Register) *");
1182 	printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
1183 	       " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1184 	       "Ambient due to PLL Active (DT PLL Active) *");
1185 	printf("%-3d    : %02x %s\n", 61, spd->dtregact,
1186 	       " spd->dtregact,    "
1187 	       "* 61 Register Case Temperature Rise from Ambient due to "
1188 	       "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1189 	printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
1190 	       " spd->spd_rev,     * 62 SPD Data Revision Code *");
1191 	printf("%-3d    : %02x %s\n", 63, spd->cksum,
1192 	       " spd->cksum,       * 63 Checksum for bytes 0-62 *");
1193 
1194 	printf("%-3d-%3d: ",  64, 71);
1195 
1196 	for (i = 0; i < 8; i++)
1197 		printf("%02x", spd->mid[i]);
1198 
1199 	printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1200 
1201 	printf("%-3d    : %02x %s\n", 72, spd->mloc,
1202 	       " spd->mloc,        * 72 Manufacturing Location *");
1203 
1204 	printf("%-3d-%3d: >>",  73, 90);
1205 	for (i = 0; i < 18; i++)
1206 		printf("%c", spd->mpart[i]);
1207 
1208 
1209 	printf("<<* 73 Manufacturer's Part Number *\n");
1210 
1211 	printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1212 	       "* 91 Revision Code *");
1213 	printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1214 	       "* 93 Manufacturing Date *");
1215 	printf("%-3d-%3d: ", 95, 98);
1216 
1217 	for (i = 0; i < 4; i++)
1218 		printf("%02x", spd->sernum[i]);
1219 
1220 	printf("* 95 Assembly Serial Number *\n");
1221 
1222 	printf("%-3d-%3d: ", 99, 127);
1223 	for (i = 0; i < 27; i++)
1224 		printf("%02x", spd->mspec[i]);
1225 
1226 
1227 	printf("* 99 Manufacturer Specific Data *\n");
1228 }
1229 #endif
1230 
1231 #ifdef CONFIG_SYS_FSL_DDR3
ddr3_spd_dump(const ddr3_spd_eeprom_t * spd)1232 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1233 {
1234 	unsigned int i;
1235 
1236 	/* General Section: Bytes 0-59 */
1237 
1238 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1239 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1240 	printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1241 
1242 	PRINT_NXS(0, spd->info_size_crc,
1243 		"info_size_crc  bytes written into serial memory, "
1244 		"CRC coverage");
1245 	PRINT_NXS(1, spd->spd_rev,
1246 		"spd_rev        SPD Revision");
1247 	PRINT_NXS(2, spd->mem_type,
1248 		"mem_type       Key Byte / DRAM Device Type");
1249 	PRINT_NXS(3, spd->module_type,
1250 		"module_type    Key Byte / Module Type");
1251 	PRINT_NXS(4, spd->density_banks,
1252 		"density_banks  SDRAM Density and Banks");
1253 	PRINT_NXS(5, spd->addressing,
1254 		"addressing     SDRAM Addressing");
1255 	PRINT_NXS(6, spd->module_vdd,
1256 		"module_vdd     Module Nominal Voltage, VDD");
1257 	PRINT_NXS(7, spd->organization,
1258 		"organization   Module Organization");
1259 	PRINT_NXS(8, spd->bus_width,
1260 		"bus_width      Module Memory Bus Width");
1261 	PRINT_NXS(9, spd->ftb_div,
1262 		"ftb_div        Fine Timebase (FTB) Dividend / Divisor");
1263 	PRINT_NXS(10, spd->mtb_dividend,
1264 		"mtb_dividend   Medium Timebase (MTB) Dividend");
1265 	PRINT_NXS(11, spd->mtb_divisor,
1266 		"mtb_divisor    Medium Timebase (MTB) Divisor");
1267 	PRINT_NXS(12, spd->tck_min,
1268 		  "tck_min        SDRAM Minimum Cycle Time");
1269 	PRINT_NXS(13, spd->res_13,
1270 		"res_13         Reserved");
1271 	PRINT_NXS(14, spd->caslat_lsb,
1272 		"caslat_lsb     CAS Latencies Supported, LSB");
1273 	PRINT_NXS(15, spd->caslat_msb,
1274 		"caslat_msb     CAS Latencies Supported, MSB");
1275 	PRINT_NXS(16, spd->taa_min,
1276 		  "taa_min        Min CAS Latency Time");
1277 	PRINT_NXS(17, spd->twr_min,
1278 		  "twr_min        Min Write REcovery Time");
1279 	PRINT_NXS(18, spd->trcd_min,
1280 		  "trcd_min       Min RAS# to CAS# Delay Time");
1281 	PRINT_NXS(19, spd->trrd_min,
1282 		  "trrd_min       Min Row Active to Row Active Delay Time");
1283 	PRINT_NXS(20, spd->trp_min,
1284 		  "trp_min        Min Row Precharge Delay Time");
1285 	PRINT_NXS(21, spd->tras_trc_ext,
1286 		  "tras_trc_ext   Upper Nibbles for tRAS and tRC");
1287 	PRINT_NXS(22, spd->tras_min_lsb,
1288 		  "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
1289 	PRINT_NXS(23, spd->trc_min_lsb,
1290 		  "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1291 	PRINT_NXS(24, spd->trfc_min_lsb,
1292 		  "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
1293 	PRINT_NXS(25, spd->trfc_min_msb,
1294 		  "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
1295 	PRINT_NXS(26, spd->twtr_min,
1296 		  "twtr_min Min Internal Write to Read Command Delay Time");
1297 	PRINT_NXS(27, spd->trtp_min,
1298 		  "trtp_min "
1299 		  "Min Internal Read to Precharge Command Delay Time");
1300 	PRINT_NXS(28, spd->tfaw_msb,
1301 		  "tfaw_msb       Upper Nibble for tFAW");
1302 	PRINT_NXS(29, spd->tfaw_min,
1303 		  "tfaw_min       Min Four Activate Window Delay Time");
1304 	PRINT_NXS(30, spd->opt_features,
1305 		"opt_features   SDRAM Optional Features");
1306 	PRINT_NXS(31, spd->therm_ref_opt,
1307 		"therm_ref_opt  SDRAM Thermal and Refresh Opts");
1308 	PRINT_NXS(32, spd->therm_sensor,
1309 		"therm_sensor  SDRAM Thermal Sensor");
1310 	PRINT_NXS(33, spd->device_type,
1311 		"device_type  SDRAM Device Type");
1312 	PRINT_NXS(34, spd->fine_tck_min,
1313 		  "fine_tck_min  Fine offset for tCKmin");
1314 	PRINT_NXS(35, spd->fine_taa_min,
1315 		  "fine_taa_min  Fine offset for tAAmin");
1316 	PRINT_NXS(36, spd->fine_trcd_min,
1317 		  "fine_trcd_min Fine offset for tRCDmin");
1318 	PRINT_NXS(37, spd->fine_trp_min,
1319 		  "fine_trp_min  Fine offset for tRPmin");
1320 	PRINT_NXS(38, spd->fine_trc_min,
1321 		  "fine_trc_min  Fine offset for tRCmin");
1322 
1323 	printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
1324 
1325 	for (i = 39; i <= 59; i++)
1326 		printf("%02x ", spd->res_39_59[i - 39]);
1327 
1328 	puts("\n");
1329 
1330 	switch (spd->module_type) {
1331 	case 0x02:  /* UDIMM */
1332 	case 0x03:  /* SO-DIMM */
1333 	case 0x04:  /* Micro-DIMM */
1334 	case 0x06:  /* Mini-UDIMM */
1335 		PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1336 			"mod_height    (Unbuffered) Module Nominal Height");
1337 		PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1338 			"mod_thickness (Unbuffered) Module Maximum Thickness");
1339 		PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1340 			"ref_raw_card  (Unbuffered) Reference Raw Card Used");
1341 		PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1342 			"addr_mapping  (Unbuffered) Address mapping from "
1343 			"Edge Connector to DRAM");
1344 		break;
1345 	case 0x01:  /* RDIMM */
1346 	case 0x05:  /* Mini-RDIMM */
1347 		PRINT_NXS(60, spd->mod_section.registered.mod_height,
1348 			"mod_height    (Registered) Module Nominal Height");
1349 		PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1350 			"mod_thickness (Registered) Module Maximum Thickness");
1351 		PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1352 			"ref_raw_card  (Registered) Reference Raw Card Used");
1353 		PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1354 			"modu_attr     (Registered) DIMM Module Attributes");
1355 		PRINT_NXS(64, spd->mod_section.registered.thermal,
1356 			"thermal       (Registered) Thermal Heat "
1357 			"Spreader Solution");
1358 		PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1359 			"reg_id_lo     (Registered) Register Manufacturer ID "
1360 			"Code, LSB");
1361 		PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1362 			"reg_id_hi     (Registered) Register Manufacturer ID "
1363 			"Code, MSB");
1364 		PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1365 			"reg_rev       (Registered) Register "
1366 			"Revision Number");
1367 		PRINT_NXS(68, spd->mod_section.registered.reg_type,
1368 			"reg_type      (Registered) Register Type");
1369 		for (i = 69; i <= 76; i++) {
1370 			printf("%-3d    : %02x rcw[%d]\n", i,
1371 				spd->mod_section.registered.rcw[i-69], i-69);
1372 		}
1373 		break;
1374 	default:
1375 		/* Module-specific Section, Unsupported Module Type */
1376 		printf("%-3d-%3d: ", 60, 116);
1377 
1378 		for (i = 60; i <= 116; i++)
1379 			printf("%02x", spd->mod_section.uc[i - 60]);
1380 
1381 		break;
1382 	}
1383 
1384 	/* Unique Module ID: Bytes 117-125 */
1385 	PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1386 	PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1387 	PRINT_NXS(119, spd->mloc,     "Mfg Location");
1388 	PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1389 
1390 	printf("%-3d-%3d: ", 122, 125);
1391 
1392 	for (i = 122; i <= 125; i++)
1393 		printf("%02x ", spd->sernum[i - 122]);
1394 	printf("   Module Serial Number\n");
1395 
1396 	/* CRC: Bytes 126-127 */
1397 	PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1398 
1399 	/* Other Manufacturer Fields and User Space: Bytes 128-255 */
1400 	printf("%-3d-%3d: ", 128, 145);
1401 	for (i = 128; i <= 145; i++)
1402 		printf("%02x ", spd->mpart[i - 128]);
1403 	printf("   Mfg's Module Part Number\n");
1404 
1405 	PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1406 		"Module Revision code");
1407 
1408 	PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1409 	PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1410 
1411 	printf("%-3d-%3d: ", 150, 175);
1412 	for (i = 150; i <= 175; i++)
1413 		printf("%02x ", spd->msd[i - 150]);
1414 	printf("   Mfg's Specific Data\n");
1415 
1416 	printf("%-3d-%3d: ", 176, 255);
1417 	for (i = 176; i <= 255; i++)
1418 		printf("%02x", spd->cust[i - 176]);
1419 	printf("   Mfg's Specific Data\n");
1420 
1421 }
1422 #endif
1423 
1424 #ifdef CONFIG_SYS_FSL_DDR4
ddr4_spd_dump(const struct ddr4_spd_eeprom_s * spd)1425 void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1426 {
1427 	unsigned int i;
1428 
1429 	/* General Section: Bytes 0-127 */
1430 
1431 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1432 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1433 	printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1434 
1435 	PRINT_NXS(0, spd->info_size_crc,
1436 		  "info_size_crc  bytes written into serial memory, CRC coverage");
1437 	PRINT_NXS(1, spd->spd_rev,
1438 		  "spd_rev        SPD Revision");
1439 	PRINT_NXS(2, spd->mem_type,
1440 		  "mem_type       Key Byte / DRAM Device Type");
1441 	PRINT_NXS(3, spd->module_type,
1442 		  "module_type    Key Byte / Module Type");
1443 	PRINT_NXS(4, spd->density_banks,
1444 		  "density_banks  SDRAM Density and Banks");
1445 	PRINT_NXS(5, spd->addressing,
1446 		  "addressing     SDRAM Addressing");
1447 	PRINT_NXS(6, spd->package_type,
1448 		  "package_type   Package type");
1449 	PRINT_NXS(7, spd->opt_feature,
1450 		  "opt_feature    Optional features");
1451 	PRINT_NXS(8, spd->thermal_ref,
1452 		  "thermal_ref    Thermal and Refresh options");
1453 	PRINT_NXS(9, spd->oth_opt_features,
1454 		  "oth_opt_features Other SDRAM optional features");
1455 	PRINT_NXS(10, spd->res_10,
1456 		  "res_10         Reserved");
1457 	PRINT_NXS(11, spd->module_vdd,
1458 		  "module_vdd     Module Nominal Voltage, VDD");
1459 	PRINT_NXS(12, spd->organization,
1460 		  "organization Module Organization");
1461 	PRINT_NXS(13, spd->bus_width,
1462 		  "bus_width      Module Memory Bus Width");
1463 	PRINT_NXS(14, spd->therm_sensor,
1464 		  "therm_sensor   Module Thermal Sensor");
1465 	PRINT_NXS(15, spd->ext_type,
1466 		  "ext_type       Extended module type");
1467 	PRINT_NXS(16, spd->res_16,
1468 		  "res_16       Reserved");
1469 	PRINT_NXS(17, spd->timebases,
1470 		  "timebases    MTb and FTB");
1471 	PRINT_NXS(18, spd->tck_min,
1472 		  "tck_min      tCKAVGmin");
1473 	PRINT_NXS(19, spd->tck_max,
1474 		  "tck_max      TCKAVGmax");
1475 	PRINT_NXS(20, spd->caslat_b1,
1476 		  "caslat_b1    CAS latencies, 1st byte");
1477 	PRINT_NXS(21, spd->caslat_b2,
1478 		  "caslat_b2    CAS latencies, 2nd byte");
1479 	PRINT_NXS(22, spd->caslat_b3,
1480 		  "caslat_b3    CAS latencies, 3rd byte ");
1481 	PRINT_NXS(23, spd->caslat_b4,
1482 		  "caslat_b4    CAS latencies, 4th byte");
1483 	PRINT_NXS(24, spd->taa_min,
1484 		  "taa_min      Min CAS Latency Time");
1485 	PRINT_NXS(25, spd->trcd_min,
1486 		  "trcd_min     Min RAS# to CAS# Delay Time");
1487 	PRINT_NXS(26, spd->trp_min,
1488 		  "trp_min      Min Row Precharge Delay Time");
1489 	PRINT_NXS(27, spd->tras_trc_ext,
1490 		  "tras_trc_ext Upper Nibbles for tRAS and tRC");
1491 	PRINT_NXS(28, spd->tras_min_lsb,
1492 		  "tras_min_lsb tRASmin, lsb");
1493 	PRINT_NXS(29, spd->trc_min_lsb,
1494 		  "trc_min_lsb  tRCmin, lsb");
1495 	PRINT_NXS(30, spd->trfc1_min_lsb,
1496 		  "trfc1_min_lsb  Min Refresh Recovery Delay Time, LSB");
1497 	PRINT_NXS(31, spd->trfc1_min_msb,
1498 		  "trfc1_min_msb  Min Refresh Recovery Delay Time, MSB ");
1499 	PRINT_NXS(32, spd->trfc2_min_lsb,
1500 		  "trfc2_min_lsb  Min Refresh Recovery Delay Time, LSB");
1501 	PRINT_NXS(33, spd->trfc2_min_msb,
1502 		  "trfc2_min_msb  Min Refresh Recovery Delay Time, MSB");
1503 	PRINT_NXS(34, spd->trfc4_min_lsb,
1504 		  "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1505 	PRINT_NXS(35, spd->trfc4_min_msb,
1506 		  "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1507 	PRINT_NXS(36, spd->tfaw_msb,
1508 		  "tfaw_msb      Upper Nibble for tFAW");
1509 	PRINT_NXS(37, spd->tfaw_min,
1510 		  "tfaw_min      tFAW, lsb");
1511 	PRINT_NXS(38, spd->trrds_min,
1512 		  "trrds_min     tRRD_Smin, MTB");
1513 	PRINT_NXS(39, spd->trrdl_min,
1514 		  "trrdl_min     tRRD_Lmin, MTB");
1515 	PRINT_NXS(40, spd->tccdl_min,
1516 		  "tccdl_min     tCCS_Lmin, MTB");
1517 
1518 	printf("%-3d-%3d: ", 41, 59);  /* Reserved, General Section */
1519 	for (i = 41; i <= 59; i++)
1520 		printf("%02x ", spd->res_41[i - 41]);
1521 
1522 	puts("\n");
1523 	printf("%-3d-%3d: ", 60, 77);
1524 	for (i = 60; i <= 77; i++)
1525 		printf("%02x ", spd->mapping[i - 60]);
1526 	puts("   mapping[] Connector to SDRAM bit map\n");
1527 
1528 	PRINT_NXS(117, spd->fine_tccdl_min,
1529 		  "fine_tccdl_min Fine offset for tCCD_Lmin");
1530 	PRINT_NXS(118, spd->fine_trrdl_min,
1531 		  "fine_trrdl_min Fine offset for tRRD_Lmin");
1532 	PRINT_NXS(119, spd->fine_trrds_min,
1533 		  "fine_trrds_min Fine offset for tRRD_Smin");
1534 	PRINT_NXS(120, spd->fine_trc_min,
1535 		  "fine_trc_min   Fine offset for tRCmin");
1536 	PRINT_NXS(121, spd->fine_trp_min,
1537 		  "fine_trp_min   Fine offset for tRPmin");
1538 	PRINT_NXS(122, spd->fine_trcd_min,
1539 		  "fine_trcd_min  Fine offset for tRCDmin");
1540 	PRINT_NXS(123, spd->fine_taa_min,
1541 		  "fine_taa_min   Fine offset for tAAmin");
1542 	PRINT_NXS(124, spd->fine_tck_max,
1543 		  "fine_tck_max   Fine offset for tCKAVGmax");
1544 	PRINT_NXS(125, spd->fine_tck_min,
1545 		  "fine_tck_min   Fine offset for tCKAVGmin");
1546 
1547 	/* CRC: Bytes 126-127 */
1548 	PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1549 
1550 	switch (spd->module_type) {
1551 	case 0x02:  /* UDIMM */
1552 	case 0x03:  /* SO-DIMM */
1553 		PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1554 			  "mod_height    (Unbuffered) Module Nominal Height");
1555 		PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1556 			  "mod_thickness (Unbuffered) Module Maximum Thickness");
1557 		PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1558 			  "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1559 		PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1560 			  "addr_mapping  (Unbuffered) Address mapping from Edge Connector to DRAM");
1561 		PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1562 			    spd->mod_section.unbuffered.crc[1], "  Module CRC");
1563 		break;
1564 	case 0x01:  /* RDIMM */
1565 		PRINT_NXS(128, spd->mod_section.registered.mod_height,
1566 			  "mod_height    (Registered) Module Nominal Height");
1567 		PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1568 			  "mod_thickness (Registered) Module Maximum Thickness");
1569 		PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1570 			  "ref_raw_card  (Registered) Reference Raw Card Used");
1571 		PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1572 			  "modu_attr     (Registered) DIMM Module Attributes");
1573 		PRINT_NXS(132, spd->mod_section.registered.thermal,
1574 			  "thermal       (Registered) Thermal Heat Spreader Solution");
1575 		PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1576 			  "reg_id_lo     (Registered) Register Manufacturer ID Code, LSB");
1577 		PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1578 			  "reg_id_hi     (Registered) Register Manufacturer ID Code, MSB");
1579 		PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1580 			  "reg_rev       (Registered) Register Revision Number");
1581 		PRINT_NXS(136, spd->mod_section.registered.reg_map,
1582 			  "reg_map       (Registered) Address mapping");
1583 		PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1584 			    spd->mod_section.registered.crc[1], "  Module CRC");
1585 		break;
1586 	case 0x04:  /* LRDIMM */
1587 		PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1588 			  "mod_height    (Loadreduced) Module Nominal Height");
1589 		PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1590 			  "mod_thickness (Loadreduced) Module Maximum Thickness");
1591 		PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1592 			  "ref_raw_card  (Loadreduced) Reference Raw Card Used");
1593 		PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1594 			  "modu_attr     (Loadreduced) DIMM Module Attributes");
1595 		PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1596 			  "thermal       (Loadreduced) Thermal Heat Spreader Solution");
1597 		PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1598 			  "reg_id_lo     (Loadreduced) Register Manufacturer ID Code, LSB");
1599 		PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1600 			  "reg_id_hi     (Loadreduced) Register Manufacturer ID Code, MSB");
1601 		PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1602 			  "reg_rev       (Loadreduced) Register Revision Number");
1603 		PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1604 			  "reg_map       (Loadreduced) Address mapping");
1605 		PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1606 			  "reg_drv       (Loadreduced) Reg output drive strength");
1607 		PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1608 			  "reg_drv_ck    (Loadreduced) Reg output drive strength for CK");
1609 		PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1610 			  "data_buf_rev  (Loadreduced) Data Buffer Revision Numbe");
1611 		PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1612 			  "vrefqe_r0     (Loadreduced) DRAM VrefDQ for Package Rank 0");
1613 		PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1614 			  "vrefqe_r1     (Loadreduced) DRAM VrefDQ for Package Rank 1");
1615 		PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1616 			  "vrefqe_r2     (Loadreduced) DRAM VrefDQ for Package Rank 2");
1617 		PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1618 			  "vrefqe_r3     (Loadreduced) DRAM VrefDQ for Package Rank 3");
1619 		PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1620 			  "data_intf     (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1621 		PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1622 			  "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1623 		PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1624 			  "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1625 		PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1626 			  "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1627 		PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1628 			  "dram_drv      (Loadreduced) DRAM Drive Strength");
1629 		PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1630 			  "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1631 		PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1632 			  "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1633 		PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1634 			  "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1635 		PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1636 			  "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1637 		PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1638 			  "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1639 		PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1640 			  "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1641 		PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1642 			    spd->mod_section.loadreduced.crc[1],
1643 			    "  Module CRC");
1644 		break;
1645 	default:
1646 		/* Module-specific Section, Unsupported Module Type */
1647 		printf("%-3d-%3d: ", 128, 255);
1648 
1649 		for (i = 128; i <= 255; i++)
1650 			printf("%02x", spd->mod_section.uc[i - 128]);
1651 
1652 		break;
1653 	}
1654 
1655 	/* Unique Module ID: Bytes 320-383 */
1656 	PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1657 	PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1658 	PRINT_NXS(322, spd->mloc,     "Mfg Location");
1659 	PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1660 
1661 	printf("%-3d-%3d: ", 325, 328);
1662 
1663 	for (i = 325; i <= 328; i++)
1664 		printf("%02x ", spd->sernum[i - 325]);
1665 	printf("   Module Serial Number\n");
1666 
1667 	printf("%-3d-%3d: ", 329, 348);
1668 	for (i = 329; i <= 348; i++)
1669 		printf("%02x ", spd->mpart[i - 329]);
1670 	printf("   Mfg's Module Part Number\n");
1671 
1672 	PRINT_NXS(349, spd->mrev, "Module Revision code");
1673 	PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1674 	PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1675 	PRINT_NXS(352, spd->stepping, "DRAM stepping");
1676 
1677 	printf("%-3d-%3d: ", 353, 381);
1678 	for (i = 353; i <= 381; i++)
1679 		printf("%02x ", spd->msd[i - 353]);
1680 	printf("   Mfg's Specific Data\n");
1681 }
1682 #endif
1683 
generic_spd_dump(const generic_spd_eeprom_t * spd)1684 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1685 {
1686 #if defined(CONFIG_SYS_FSL_DDR1)
1687 	ddr1_spd_dump(spd);
1688 #elif defined(CONFIG_SYS_FSL_DDR2)
1689 	ddr2_spd_dump(spd);
1690 #elif defined(CONFIG_SYS_FSL_DDR3)
1691 	ddr3_spd_dump(spd);
1692 #elif defined(CONFIG_SYS_FSL_DDR4)
1693 	ddr4_spd_dump(spd);
1694 #endif
1695 }
1696 
fsl_ddr_printinfo(const fsl_ddr_info_t * pinfo,unsigned int ctrl_mask,unsigned int dimm_mask,unsigned int do_mask)1697 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1698 			unsigned int ctrl_mask,
1699 			unsigned int dimm_mask,
1700 			unsigned int do_mask)
1701 {
1702 	unsigned int i, j, retval;
1703 
1704 	/* STEP 1:  DIMM SPD data */
1705 	if (do_mask & STEP_GET_SPD) {
1706 		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1707 			if (!(ctrl_mask & (1 << i)))
1708 				continue;
1709 
1710 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1711 				if (!(dimm_mask & (1 << j)))
1712 					continue;
1713 
1714 				printf("SPD info:  Controller=%u "
1715 						"DIMM=%u\n", i, j);
1716 				generic_spd_dump(
1717 					&(pinfo->spd_installed_dimms[i][j]));
1718 				printf("\n");
1719 			}
1720 			printf("\n");
1721 		}
1722 		printf("\n");
1723 	}
1724 
1725 	/* STEP 2:  DIMM Parameters */
1726 	if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1727 		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1728 			if (!(ctrl_mask & (1 << i)))
1729 				continue;
1730 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1731 				if (!(dimm_mask & (1 << j)))
1732 					continue;
1733 				printf("DIMM parameters:  Controller=%u "
1734 						"DIMM=%u\n", i, j);
1735 				print_dimm_parameters(
1736 					&(pinfo->dimm_params[i][j]));
1737 				printf("\n");
1738 			}
1739 			printf("\n");
1740 		}
1741 		printf("\n");
1742 	}
1743 
1744 	/* STEP 3:  Common Parameters */
1745 	if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1746 		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1747 			if (!(ctrl_mask & (1 << i)))
1748 				continue;
1749 			printf("\"lowest common\" DIMM parameters:  "
1750 					"Controller=%u\n", i);
1751 			print_lowest_common_dimm_parameters(
1752 				&pinfo->common_timing_params[i]);
1753 			printf("\n");
1754 		}
1755 		printf("\n");
1756 	}
1757 
1758 	/* STEP 4:  User Configuration Options */
1759 	if (do_mask & STEP_GATHER_OPTS) {
1760 		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1761 			if (!(ctrl_mask & (1 << i)))
1762 				continue;
1763 			printf("User Config Options: Controller=%u\n", i);
1764 			print_memctl_options(&pinfo->memctl_opts[i]);
1765 			printf("\n");
1766 		}
1767 		printf("\n");
1768 	}
1769 
1770 	/* STEP 5:  Address assignment */
1771 	if (do_mask & STEP_ASSIGN_ADDRESSES) {
1772 		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1773 			if (!(ctrl_mask & (1 << i)))
1774 				continue;
1775 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1776 				printf("Address Assignment: Controller=%u "
1777 						"DIMM=%u\n", i, j);
1778 				printf("Don't have this functionality yet\n");
1779 			}
1780 			printf("\n");
1781 		}
1782 		printf("\n");
1783 	}
1784 
1785 	/* STEP 6:  computed controller register values */
1786 	if (do_mask & STEP_COMPUTE_REGS) {
1787 		for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1788 			if (!(ctrl_mask & (1 << i)))
1789 				continue;
1790 			printf("Computed Register Values: Controller=%u\n", i);
1791 			print_fsl_memctl_config_regs(
1792 				&pinfo->fsl_ddr_config_reg[i]);
1793 			retval = check_fsl_memctl_config_regs(
1794 				&pinfo->fsl_ddr_config_reg[i]);
1795 			if (retval) {
1796 				printf("check_fsl_memctl_config_regs "
1797 					"result = %u\n", retval);
1798 			}
1799 			printf("\n");
1800 		}
1801 		printf("\n");
1802 	}
1803 }
1804 
1805 struct data_strings {
1806 	const char *data_name;
1807 	unsigned int step_mask;
1808 	unsigned int dimm_number_required;
1809 };
1810 
1811 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1812 
fsl_ddr_parse_interactive_cmd(char ** argv,int argc,unsigned int * pstep_mask,unsigned int * pctlr_mask,unsigned int * pdimm_mask,unsigned int * pdimm_number_required)1813 static unsigned int fsl_ddr_parse_interactive_cmd(
1814 	char **argv,
1815 	int argc,
1816 	unsigned int *pstep_mask,
1817 	unsigned int *pctlr_mask,
1818 	unsigned int *pdimm_mask,
1819 	unsigned int *pdimm_number_required
1820 	 ) {
1821 
1822 	static const struct data_strings options[] = {
1823 		DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1824 		DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1825 		DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1826 		DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1827 		DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1828 		DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1829 	};
1830 	static const unsigned int n_opts = ARRAY_SIZE(options);
1831 
1832 	unsigned int i, j;
1833 	unsigned int error = 0;
1834 
1835 	for (i = 1; i < argc; i++) {
1836 		unsigned int matched = 0;
1837 
1838 		for (j = 0; j < n_opts; j++) {
1839 			if (strcmp(options[j].data_name, argv[i]) != 0)
1840 				continue;
1841 			*pstep_mask |= options[j].step_mask;
1842 			*pdimm_number_required =
1843 				options[j].dimm_number_required;
1844 			matched = 1;
1845 			break;
1846 		}
1847 
1848 		if (matched)
1849 			continue;
1850 
1851 		if (argv[i][0] == 'c') {
1852 			char c = argv[i][1];
1853 			if (isdigit(c))
1854 				*pctlr_mask |= 1 << (c - '0');
1855 			continue;
1856 		}
1857 
1858 		if (argv[i][0] == 'd') {
1859 			char c = argv[i][1];
1860 			if (isdigit(c))
1861 				*pdimm_mask |= 1 << (c - '0');
1862 			continue;
1863 		}
1864 
1865 		printf("unknown arg %s\n", argv[i]);
1866 		*pstep_mask = 0;
1867 		error = 1;
1868 		break;
1869 	}
1870 
1871 	return error;
1872 }
1873 
fsl_ddr_interactive_env_var_exists(void)1874 int fsl_ddr_interactive_env_var_exists(void)
1875 {
1876 	char buffer[CONFIG_SYS_CBSIZE];
1877 
1878 	if (env_get_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1879 		return 1;
1880 
1881 	return 0;
1882 }
1883 
fsl_ddr_interactive(fsl_ddr_info_t * pinfo,int var_is_set)1884 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
1885 {
1886 	unsigned long long ddrsize;
1887 	const char *prompt = "FSL DDR>";
1888 	char buffer[CONFIG_SYS_CBSIZE];
1889 	char buffer2[CONFIG_SYS_CBSIZE];
1890 	char *p = NULL;
1891 	char *argv[CONFIG_SYS_MAXARGS + 1];	/* NULL terminated */
1892 	int argc;
1893 	unsigned int next_step = STEP_GET_SPD;
1894 	const char *usage = {
1895 		"commands:\n"
1896 		"print      print SPD and intermediate computed data\n"
1897 		"reset      reboot machine\n"
1898 		"recompute  reload SPD and options to default and recompute regs\n"
1899 		"edit       modify spd, parameter, or option\n"
1900 		"compute    recompute registers from current next_step to end\n"
1901 		"copy       copy parameters\n"
1902 		"next_step  shows current next_step\n"
1903 		"help       this message\n"
1904 		"go         program the memory controller and continue with u-boot\n"
1905 	};
1906 
1907 	if (var_is_set) {
1908 		if (env_get_f("ddr_interactive", buffer2,
1909 			      CONFIG_SYS_CBSIZE) > 0)
1910 			p = buffer2;
1911 		else
1912 			var_is_set = 0;
1913 	}
1914 
1915 	/*
1916 	 * The strategy for next_step is that it points to the next
1917 	 * step in the computation process that needs to be done.
1918 	 */
1919 	while (1) {
1920 		if (var_is_set) {
1921 			char *pend = strchr(p, ';');
1922 			if (pend) {
1923 				/* found command separator, copy sub-command */
1924 				*pend = '\0';
1925 				strcpy(buffer, p);
1926 				p = pend + 1;
1927 			} else {
1928 				/* separator not found, copy whole string */
1929 				strcpy(buffer, p);
1930 				p = NULL;
1931 				var_is_set = 0;
1932 			}
1933 		} else {
1934 			/*
1935 			 * No need to worry for buffer overflow here in
1936 			 * this function;  cli_readline() maxes out at
1937 			 * CFG_CBSIZE
1938 			 */
1939 			cli_readline_into_buffer(prompt, buffer, 0);
1940 		}
1941 		argc = cli_simple_parse_line(buffer, argv);
1942 		if (argc == 0)
1943 			continue;
1944 
1945 
1946 		if (strcmp(argv[0], "help") == 0) {
1947 			puts(usage);
1948 			continue;
1949 		}
1950 
1951 		if (strcmp(argv[0], "next_step") == 0) {
1952 			printf("next_step = 0x%02X (%s)\n",
1953 			       next_step,
1954 			       step_to_string(next_step));
1955 			continue;
1956 		}
1957 
1958 		if (strcmp(argv[0], "copy") == 0) {
1959 			unsigned int error = 0;
1960 			unsigned int step_mask = 0;
1961 			unsigned int src_ctlr_mask = 0;
1962 			unsigned int src_dimm_mask = 0;
1963 			unsigned int dimm_number_required = 0;
1964 			unsigned int src_ctlr_num = 0;
1965 			unsigned int src_dimm_num = 0;
1966 			unsigned int dst_ctlr_num = -1;
1967 			unsigned int dst_dimm_num = -1;
1968 			unsigned int i, num_dest_parms;
1969 
1970 			if (argc == 1) {
1971 				printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1972 				continue;
1973 			}
1974 
1975 			error = fsl_ddr_parse_interactive_cmd(
1976 				argv, argc,
1977 				&step_mask,
1978 				&src_ctlr_mask,
1979 				&src_dimm_mask,
1980 				&dimm_number_required
1981 			);
1982 
1983 			/* XXX: only dimm_number_required and step_mask will
1984 			   be used by this function.  Parse the controller and
1985 			   DIMM number separately because it is easier.  */
1986 
1987 			if (error)
1988 				continue;
1989 
1990 			/* parse source destination controller / DIMM */
1991 
1992 			num_dest_parms = dimm_number_required ? 2 : 1;
1993 
1994 			for (i = 0; i < argc; i++) {
1995 				if (argv[i][0] == 'c') {
1996 					char c = argv[i][1];
1997 					if (isdigit(c)) {
1998 						src_ctlr_num = (c - '0');
1999 						break;
2000 					}
2001 				}
2002 			}
2003 
2004 			for (i = 0; i < argc; i++) {
2005 				if (argv[i][0] == 'd') {
2006 					char c = argv[i][1];
2007 					if (isdigit(c)) {
2008 						src_dimm_num = (c - '0');
2009 						break;
2010 					}
2011 				}
2012 			}
2013 
2014 			/* parse destination controller / DIMM */
2015 
2016 			for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2017 				if (argv[i][0] == 'c') {
2018 					char c = argv[i][1];
2019 					if (isdigit(c)) {
2020 						dst_ctlr_num = (c - '0');
2021 						break;
2022 					}
2023 				}
2024 			}
2025 
2026 			for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2027 				if (argv[i][0] == 'd') {
2028 					char c = argv[i][1];
2029 					if (isdigit(c)) {
2030 						dst_dimm_num = (c - '0');
2031 						break;
2032 					}
2033 				}
2034 			}
2035 
2036 			/* TODO: validate inputs */
2037 
2038 			debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
2039 				src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
2040 
2041 
2042 			switch (step_mask) {
2043 
2044 			case STEP_GET_SPD:
2045 				memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
2046 					&(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
2047 					sizeof(pinfo->spd_installed_dimms[0][0]));
2048 				break;
2049 
2050 			case STEP_COMPUTE_DIMM_PARMS:
2051 				memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
2052 					&(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
2053 					sizeof(pinfo->dimm_params[0][0]));
2054 				break;
2055 
2056 			case STEP_COMPUTE_COMMON_PARMS:
2057 				memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
2058 					&(pinfo->common_timing_params[src_ctlr_num]),
2059 					sizeof(pinfo->common_timing_params[0]));
2060 				break;
2061 
2062 			case STEP_GATHER_OPTS:
2063 				memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
2064 					&(pinfo->memctl_opts[src_ctlr_num]),
2065 					sizeof(pinfo->memctl_opts[0]));
2066 				break;
2067 
2068 			/* someday be able to have addresses to copy addresses... */
2069 
2070 			case STEP_COMPUTE_REGS:
2071 				memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
2072 					&(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
2073 					sizeof(pinfo->memctl_opts[0]));
2074 				break;
2075 
2076 			default:
2077 				printf("unexpected step_mask value\n");
2078 			}
2079 
2080 			continue;
2081 
2082 		}
2083 
2084 		if (strcmp(argv[0], "edit") == 0) {
2085 			unsigned int error = 0;
2086 			unsigned int step_mask = 0;
2087 			unsigned int ctlr_mask = 0;
2088 			unsigned int dimm_mask = 0;
2089 			char *p_element = NULL;
2090 			char *p_value = NULL;
2091 			unsigned int dimm_number_required = 0;
2092 			unsigned int ctrl_num;
2093 			unsigned int dimm_num;
2094 
2095 			if (argc == 1) {
2096 				/* Only the element and value must be last */
2097 				printf("edit <c#> <d#> "
2098 					"<spd|dimmparms|commonparms|opts|"
2099 					"addresses|regs> <element> <value>\n");
2100 				printf("for spd, specify byte number for "
2101 					"element\n");
2102 				continue;
2103 			}
2104 
2105 			error = fsl_ddr_parse_interactive_cmd(
2106 				argv, argc - 2,
2107 				&step_mask,
2108 				&ctlr_mask,
2109 				&dimm_mask,
2110 				&dimm_number_required
2111 			);
2112 
2113 			if (error)
2114 				continue;
2115 
2116 
2117 			/* Check arguments */
2118 
2119 			/* ERROR: If no steps were found */
2120 			if (step_mask == 0) {
2121 				printf("Error: No valid steps were specified "
2122 						"in argument.\n");
2123 				continue;
2124 			}
2125 
2126 			/* ERROR: If multiple steps were found */
2127 			if (step_mask & (step_mask - 1)) {
2128 				printf("Error: Multiple steps specified in "
2129 						"argument.\n");
2130 				continue;
2131 			}
2132 
2133 			/* ERROR: Controller not specified */
2134 			if (ctlr_mask == 0) {
2135 				printf("Error: controller number not "
2136 					"specified or no element and "
2137 					"value specified\n");
2138 				continue;
2139 			}
2140 
2141 			if (ctlr_mask & (ctlr_mask - 1)) {
2142 				printf("Error: multiple controllers "
2143 						"specified, %X\n", ctlr_mask);
2144 				continue;
2145 			}
2146 
2147 			/* ERROR: DIMM number not specified */
2148 			if (dimm_number_required && dimm_mask == 0) {
2149 				printf("Error: DIMM number number not "
2150 					"specified or no element and "
2151 					"value specified\n");
2152 				continue;
2153 			}
2154 
2155 			if (dimm_mask & (dimm_mask - 1)) {
2156 				printf("Error: multipled DIMMs specified\n");
2157 				continue;
2158 			}
2159 
2160 			p_element = argv[argc - 2];
2161 			p_value = argv[argc - 1];
2162 
2163 			ctrl_num = __ilog2(ctlr_mask);
2164 			dimm_num = __ilog2(dimm_mask);
2165 
2166 			switch (step_mask) {
2167 			case STEP_GET_SPD:
2168 				{
2169 					unsigned int element_num;
2170 					unsigned int value;
2171 
2172 					element_num = simple_strtoul(p_element,
2173 								     NULL, 0);
2174 					value = simple_strtoul(p_value,
2175 							       NULL, 0);
2176 					fsl_ddr_spd_edit(pinfo,
2177 							       ctrl_num,
2178 							       dimm_num,
2179 							       element_num,
2180 							       value);
2181 					next_step = STEP_COMPUTE_DIMM_PARMS;
2182 				}
2183 				break;
2184 
2185 			case STEP_COMPUTE_DIMM_PARMS:
2186 				fsl_ddr_dimm_parameters_edit(
2187 						 pinfo, ctrl_num, dimm_num,
2188 						 p_element, p_value);
2189 				next_step = STEP_COMPUTE_COMMON_PARMS;
2190 				break;
2191 
2192 			case STEP_COMPUTE_COMMON_PARMS:
2193 				lowest_common_dimm_parameters_edit(pinfo,
2194 						ctrl_num, p_element, p_value);
2195 				next_step = STEP_GATHER_OPTS;
2196 				break;
2197 
2198 			case STEP_GATHER_OPTS:
2199 				fsl_ddr_options_edit(pinfo, ctrl_num,
2200 							   p_element, p_value);
2201 				next_step = STEP_ASSIGN_ADDRESSES;
2202 				break;
2203 
2204 			case STEP_ASSIGN_ADDRESSES:
2205 				printf("editing of address assignment "
2206 						"not yet implemented\n");
2207 				break;
2208 
2209 			case STEP_COMPUTE_REGS:
2210 				{
2211 					fsl_ddr_regs_edit(pinfo,
2212 								ctrl_num,
2213 								p_element,
2214 								p_value);
2215 					next_step = STEP_PROGRAM_REGS;
2216 				}
2217 				break;
2218 
2219 			default:
2220 				printf("programming error\n");
2221 				while (1)
2222 					;
2223 				break;
2224 			}
2225 			continue;
2226 		}
2227 
2228 		if (strcmp(argv[0], "reset") == 0) {
2229 			/*
2230 			 * Reboot machine.
2231 			 * Args don't seem to matter because this
2232 			 * doesn't return
2233 			 */
2234 			do_reset(NULL, 0, 0, NULL);
2235 			printf("Reset didn't work\n");
2236 		}
2237 
2238 		if (strcmp(argv[0], "recompute") == 0) {
2239 			/*
2240 			 * Recalculate everything, starting with
2241 			 * loading SPD EEPROM from DIMMs
2242 			 */
2243 			next_step = STEP_GET_SPD;
2244 			ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2245 			continue;
2246 		}
2247 
2248 		if (strcmp(argv[0], "compute") == 0) {
2249 			/*
2250 			 * Compute rest of steps starting at
2251 			 * the current next_step/
2252 			 */
2253 			ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2254 			continue;
2255 		}
2256 
2257 		if (strcmp(argv[0], "print") == 0) {
2258 			unsigned int error = 0;
2259 			unsigned int step_mask = 0;
2260 			unsigned int ctlr_mask = 0;
2261 			unsigned int dimm_mask = 0;
2262 			unsigned int dimm_number_required = 0;
2263 
2264 			if (argc == 1) {
2265 				printf("print [c<n>] [d<n>] [spd] [dimmparms] "
2266 				  "[commonparms] [opts] [addresses] [regs]\n");
2267 				continue;
2268 			}
2269 
2270 			error = fsl_ddr_parse_interactive_cmd(
2271 				argv, argc,
2272 				&step_mask,
2273 				&ctlr_mask,
2274 				&dimm_mask,
2275 				&dimm_number_required
2276 			);
2277 
2278 			if (error)
2279 				continue;
2280 
2281 			/* If no particular controller was found, print all */
2282 			if (ctlr_mask == 0)
2283 				ctlr_mask = 0xFF;
2284 
2285 			/* If no particular dimm was found, print all dimms. */
2286 			if (dimm_mask == 0)
2287 				dimm_mask = 0xFF;
2288 
2289 			/* If no steps were found, print all steps. */
2290 			if (step_mask == 0)
2291 				step_mask = STEP_ALL;
2292 
2293 			fsl_ddr_printinfo(pinfo, ctlr_mask,
2294 						dimm_mask, step_mask);
2295 			continue;
2296 		}
2297 
2298 		if (strcmp(argv[0], "go") == 0) {
2299 			if (next_step)
2300 				ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2301 			break;
2302 		}
2303 
2304 		printf("unknown command %s\n", argv[0]);
2305 	}
2306 
2307 	debug("end of memory = %llu\n", (u64)ddrsize);
2308 
2309 	return ddrsize;
2310 }
2311