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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef __AXP_MC_STATIC_H
7 #define __AXP_MC_STATIC_H
8 
9 MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
10 #ifdef CONFIG_DDR_32BIT
11 	{0x00001400, 0x7301c924},	/*DDR SDRAM Configuration Register */
12 #else /*CONFIG_DDR_64BIT */
13 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
14 #endif
15 	{0x00001404, 0x3630b800},	/*Dunit Control Low Register */
16 	{0x00001408, 0x43149775},	/*DDR SDRAM Timing (Low) Register */
17 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
18 	{0x0000140C, 0x38d83fe0},	/*DDR SDRAM Timing (High) Register */
19 
20 #ifdef DB_78X60_PCAC
21 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
22 #else
23 	{0x00001410, 0x040F0000},	/*DDR SDRAM Open Pages Control Register */
24 #endif
25 
26 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
27 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
28 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
29 	{0x00001424, 0x0000D3FF},	/*Dunit Control High Register */
30 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
31 	{0x0000142C, 0x214C2F38},	/*Dunit Control High Register */
32 	{0x0000147C, 0x0000c671},
33 
34 	{0x000014a0, 0x000002A9},
35 	{0x000014a8, 0x00000101},	/*2:1 */
36 	{0x00020220, 0x00000007},
37 
38 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
39 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
40 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
41 
42 	{0x000014C0, 0x192434e9},	/* DRAM address and Control Driving Strenght  */
43 	{0x000014C4, 0x092434e9},	/* DRAM Data and DQS Driving Strenght  */
44 
45 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
46 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
47 
48 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
49 	{0x000150C, 0x00000000},	/* CS1 Size */
50 	{0x0001514, 0x00000000},	/* CS2 Size */
51 	{0x000151C, 0x00000000},	/* CS3 Size */
52 
53 	/*     {0x00001524, 0x0000C800},  */
54 	{0x00001538, 0x0000000b},	/*Read Data Sample Delays Register */
55 	{0x0000153C, 0x0000000d},	/*Read Data Ready Delay Register */
56 
57 	{0x000015D0, 0x00000640},	/*MR0 */
58 	{0x000015D4, 0x00000046},	/*MR1 */
59 	{0x000015D8, 0x00000010},	/*MR2 */
60 	{0x000015DC, 0x00000000},	/*MR3 */
61 
62 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
63 	{0x000015EC, 0xd800aa25},	/*DDR PHY */
64 	{0x0, 0x0}
65 };
66 
67 MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
68 #ifdef CONFIG_DDR_32BIT
69 	{0x00001400, 0x7301c924},	/*DDR SDRAM Configuration Register */
70 #else /*CONFIG_DDR_64BIT */
71 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
72 #endif
73 	{0x00001404, 0x3630b800},	/*Dunit Control Low Register */
74 	{0x00001408, 0x43149775},	/*DDR SDRAM Timing (Low) Register */
75 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
76 	{0x0000140C, 0x38d83fe0},	/*DDR SDRAM Timing (High) Register */
77 
78 #ifdef DB_78X60_PCAC
79 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
80 #else
81 	{0x00001410, 0x040F000C},	/*DDR SDRAM Open Pages Control Register */
82 #endif
83 
84 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
85 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
86 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
87 	{0x00001424, 0x0000D3FF},	/*Dunit Control High Register */
88 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
89 	{0x0000142C, 0x214C2F38},	/*Dunit Control High Register */
90 	{0x0000147C, 0x0000c671},
91 
92 	{0x000014a0, 0x000002A9},
93 	{0x000014a8, 0x00000101},	/*2:1 */
94 	{0x00020220, 0x00000007},
95 
96 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
97 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
98 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
99 
100 	{0x000014C0, 0x192434e9},	/* DRAM address and Control Driving Strenght  */
101 	{0x000014C4, 0x092434e9},	/* DRAM Data and DQS Driving Strenght  */
102 
103 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
104 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
105 
106 	{0x0001504, 0x3FFFFFF1},	/* CS0 Size */
107 	{0x000150C, 0x00000000},	/* CS1 Size */
108 	{0x0001514, 0x00000000},	/* CS2 Size */
109 	{0x000151C, 0x00000000},	/* CS3 Size */
110 
111 	/*     {0x00001524, 0x0000C800},  */
112 	{0x00001538, 0x0000000b},	/*Read Data Sample Delays Register */
113 	{0x0000153C, 0x0000000d},	/*Read Data Ready Delay Register */
114 
115 	{0x000015D0, 0x00000640},	/*MR0 */
116 	{0x000015D4, 0x00000046},	/*MR1 */
117 	{0x000015D8, 0x00000010},	/*MR2 */
118 	{0x000015DC, 0x00000000},	/*MR3 */
119 
120 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
121 	{0x000015EC, 0xd800aa25},	/*DDR PHY */
122 	{0x0, 0x0}
123 };
124 
125 MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
126 #ifdef CONFIG_DDR_32BIT
127 	{0x00001400, 0x73004C30},	/*DDR SDRAM Configuration Register */
128 #else /* CONFIG_DDR_64BIT */
129 	{0x00001400, 0x7300CC30},	/*DDR SDRAM Configuration Register */
130 #endif
131 	{0x00001404, 0x3630B840},	/*Dunit Control Low Register */
132 	{0x00001408, 0x33137663},	/*DDR SDRAM Timing (Low) Register */
133 	{0x0000140C, 0x38000C55},	/*DDR SDRAM Timing (High) Register */
134 	{0x00001410, 0x040F0000},	/*DDR SDRAM Address Control Register */
135 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
136 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
137 	{0x0000141C, 0x00000672},	/*DDR SDRAM Mode Register */
138 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
139 	{0x00001424, 0x0100D3FF},	/*Dunit Control High Register */
140 	{0x00001428, 0x000D6720},	/*Dunit Control High Register */
141 	{0x0000142C, 0x014C2F38},	/*Dunit Control High Register */
142 	{0x0000147C, 0x00006571},
143 
144 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
145 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
146 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
147 
148 	{0x000014a0, 0x000002A9},
149 	{0x000014a8, 0x00000101},	/*2:1 */
150 	{0x00020220, 0x00000007},
151 
152 	{0x000014C0, 0x192424C8},	/* DRAM address and Control Driving Strenght  */
153 	{0x000014C4, 0xEFB24C8},	/* DRAM Data and DQS Driving Strenght  */
154 
155 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
156 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
157 
158 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
159 	{0x000150C, 0x00000000},	/* CS1 Size */
160 	{0x0001514, 0x00000000},	/* CS2 Size */
161 	{0x000151C, 0x00000000},	/* CS3 Size */
162 
163 	{0x00001538, 0x00000008},	/*Read Data Sample Delays Register */
164 	{0x0000153C, 0x0000000A},	/*Read Data Ready Delay Register */
165 
166 	{0x000015D0, 0x00000630},	/*MR0 */
167 	{0x000015D4, 0x00000046},	/*MR1 */
168 	{0x000015D8, 0x00000008},	/*MR2 */
169 	{0x000015DC, 0x00000000},	/*MR3 */
170 
171 	{0x000015E4, 0x00203c18},	/*ZQDS Configuration Register */
172 	/* {0x000015EC, 0xDE000025}, *//*DDR PHY */
173 	{0x000015EC, 0xF800AA25},	/*DDR PHY */
174 	{0x0, 0x0}
175 };
176 
177 MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
178 #ifdef CONFIG_DDR_32BIT
179 	{0x00001400, 0x73014A28},	/*DDR SDRAM Configuration Register */
180 #else /*CONFIG_DDR_64BIT */
181 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
182 #endif
183 	{0x00001404, 0x3630B040},	/*Dunit Control Low Register */
184 	{0x00001408, 0x44149887},	/*DDR SDRAM Timing (Low) Register */
185 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
186 	{0x0000140C, 0x38D83FE0},	/*DDR SDRAM Timing (High) Register */
187 
188 #ifdef DB_78X60_PCAC
189 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
190 #else
191 	{0x00001410, 0x040F0000},	/*DDR SDRAM Open Pages Control Register */
192 #endif
193 
194 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
195 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
196 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
197 	{0x00001424, 0x0100D1FF},	/*Dunit Control High Register */
198 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
199 	{0x0000142C, 0x214C2F38},	/*Dunit Control High Register */
200 	{0x0000147C, 0x0000c671},
201 
202 	{0x000014a8, 0x00000101},	/*2:1 */
203 	{0x00020220, 0x00000007},
204 
205 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
206 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
207 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
208 
209 	{0x000014C0, 0x192424C8},	/* DRAM address and Control Driving Strenght  */
210 	{0x000014C4, 0xEFB24C8},	/* DRAM Data and DQS Driving Strenght  */
211 
212 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
213 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
214 
215 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
216 	{0x000150C, 0x00000000},	/* CS1 Size */
217 	{0x0001514, 0x00000000},	/* CS2 Size */
218 	{0x000151C, 0x00000000},	/* CS3 Size */
219 
220 	/*     {0x00001524, 0x0000C800},  */
221 	{0x00001538, 0x0000000b},	/*Read Data Sample Delays Register */
222 	{0x0000153C, 0x0000000d},	/*Read Data Ready Delay Register */
223 
224 	{0x000015D0, 0x00000650},	/*MR0 */
225 	{0x000015D4, 0x00000046},	/*MR1 */
226 	{0x000015D8, 0x00000010},	/*MR2 */
227 	{0x000015DC, 0x00000000},	/*MR3 */
228 
229 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
230 	{0x000015EC, 0xDE000025},	/*DDR PHY */
231 	{0x0, 0x0}
232 };
233 
234 MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
235 #ifdef CONFIG_DDR_32BIT
236 	{0x00001400, 0x73004C30},	/*DDR SDRAM Configuration Register */
237 #else /*CONFIG_DDR_64BIT */
238 	{0x00001400, 0x7300CC30},	/*DDR SDRAM Configuration Register */
239 	/*{0x00001400, 0x7304CC30},  *//*DDR SDRAM Configuration Register */
240 #endif
241 	{0x00001404, 0x3630B840},	/*Dunit Control Low Register */
242 	{0x00001408, 0x33137663},	/*DDR SDRAM Timing (Low) Register */
243 	{0x0000140C, 0x38000C55},	/*DDR SDRAM Timing (High) Register */
244 	{0x00001410, 0x040F0000},	/*DDR SDRAM Address Control Register */
245 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
246 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
247 	{0x0000141C, 0x00000672},	/*DDR SDRAM Mode Register */
248 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
249 	{0x00001424, 0x0100F1FF},	/*Dunit Control High Register */
250 	{0x00001428, 0x000D6720},	/*Dunit Control High Register */
251 	{0x0000142C, 0x014C2F38},	/*Dunit Control High Register */
252 	{0x0000147C, 0x00006571},
253 
254 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
255 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
256 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
257 
258 	{0x000014C0, 0x192424C8},	/* DRAM address and Control Driving Strenght  */
259 	{0x000014C4, 0xEFB24C8},	/* DRAM Data and DQS Driving Strenght  */
260 
261 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
262 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
263 
264 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
265 	{0x000150C, 0x00000000},	/* CS1 Size */
266 	{0x0001514, 0x00000000},	/* CS2 Size */
267 	{0x000151C, 0x00000000},	/* CS3 Size */
268 
269 	{0x00001538, 0x00000008},	/*Read Data Sample Delays Register */
270 	{0x0000153C, 0x0000000A},	/*Read Data Ready Delay Register */
271 
272 	{0x000015D0, 0x00000630},	/*MR0 */
273 	{0x000015D4, 0x00000046},	/*MR1 */
274 	{0x000015D8, 0x00000008},	/*MR2 */
275 	{0x000015DC, 0x00000000},	/*MR3 */
276 
277 	{0x000015E4, 0x00203c18},	/*ZQDS Configuration Register */
278 	{0x000015EC, 0xDE000025},	/*DDR PHY */
279 
280 	{0x0, 0x0}
281 };
282 
283 #endif /* __AXP_MC_STATIC_H */
284