1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__ 7 #define __ASM_ARCH_MX5_IMX_REGS_H__ 8 9 #define ARCH_MXC 10 11 #if defined(CONFIG_MX51) 12 #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ 13 #define IPU_SOC_BASE_ADDR 0x40000000 14 #define IPU_SOC_OFFSET 0x1E000000 15 #define SPBA0_BASE_ADDR 0x70000000 16 #define AIPS1_BASE_ADDR 0x73F00000 17 #define AIPS2_BASE_ADDR 0x83F00000 18 #define CSD0_BASE_ADDR 0x90000000 19 #define CSD1_BASE_ADDR 0xA0000000 20 #define NFC_BASE_ADDR_AXI 0xCFFF0000 21 #define CS1_BASE_ADDR 0xB8000000 22 #elif defined(CONFIG_MX53) 23 #define IPU_SOC_BASE_ADDR 0x18000000 24 #define IPU_SOC_OFFSET 0x06000000 25 #define SPBA0_BASE_ADDR 0x50000000 26 #define AIPS1_BASE_ADDR 0x53F00000 27 #define AIPS2_BASE_ADDR 0x63F00000 28 #define CSD0_BASE_ADDR 0x70000000 29 #define CSD1_BASE_ADDR 0xB0000000 30 #define NFC_BASE_ADDR_AXI 0xF7FF0000 31 #define IRAM_BASE_ADDR 0xF8000000 32 #define CS1_BASE_ADDR 0xF4000000 33 #define SATA_BASE_ADDR 0x10000000 34 #else 35 #error "CPU_TYPE not defined" 36 #endif 37 38 #define IRAM_SIZE 0x00020000 /* 128 KB */ 39 40 /* 41 * SPBA global module enabled #0 42 */ 43 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 44 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 45 #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) 46 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) 47 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) 48 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) 49 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) 50 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) 51 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) 52 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) 53 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) 54 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) 55 56 /* 57 * AIPS 1 58 */ 59 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) 60 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) 61 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 62 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 63 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) 64 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) 65 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) 66 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) 67 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) 68 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) 69 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) 70 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) 71 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 72 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 73 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) 74 #define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) 75 #define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) 76 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) 77 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) 78 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) 79 80 #if defined(CONFIG_MX53) 81 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) 82 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) 83 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) 84 #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) 85 #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) 86 #endif 87 /* 88 * AIPS 2 89 */ 90 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) 91 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 92 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) 93 #ifdef CONFIG_MX53 94 #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) 95 #endif 96 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) 97 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) 98 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) 99 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) 100 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) 101 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) 102 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) 103 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) 104 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) 105 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) 106 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) 107 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) 108 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) 109 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 110 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) 111 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) 112 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) 113 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) 114 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) 115 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) 116 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) 117 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) 118 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) 119 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) 120 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) 121 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) 122 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) 123 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) 124 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) 125 126 #if defined(CONFIG_MX53) 127 #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) 128 #endif 129 130 /* 131 * WEIM CSnGCR1 132 */ 133 #define CSEN 1 134 #define SWR (1 << 1) 135 #define SRD (1 << 2) 136 #define MUM (1 << 3) 137 #define WFL (1 << 4) 138 #define RFL (1 << 5) 139 #define CRE (1 << 6) 140 #define CREP (1 << 7) 141 #define BL(x) (((x) & 0x7) << 8) 142 #define WC (1 << 11) 143 #define BCD(x) (((x) & 0x3) << 12) 144 #define BCS(x) (((x) & 0x3) << 14) 145 #define DSZ(x) (((x) & 0x7) << 16) 146 #define SP (1 << 19) 147 #define CSREC(x) (((x) & 0x7) << 20) 148 #define AUS (1 << 23) 149 #define GBC(x) (((x) & 0x7) << 24) 150 #define WP (1 << 27) 151 #define PSZ(x) (((x) & 0x0f << 28) 152 153 /* 154 * WEIM CSnGCR2 155 */ 156 #define ADH(x) (((x) & 0x3)) 157 #define DAPS(x) (((x) & 0x0f << 4) 158 #define DAE (1 << 8) 159 #define DAP (1 << 9) 160 #define MUX16_BYP (1 << 12) 161 162 /* 163 * WEIM CSnRCR1 164 */ 165 #define RCSN(x) (((x) & 0x7)) 166 #define RCSA(x) (((x) & 0x7) << 4) 167 #define OEN(x) (((x) & 0x7) << 8) 168 #define OEA(x) (((x) & 0x7) << 12) 169 #define RADVN(x) (((x) & 0x7) << 16) 170 #define RAL (1 << 19) 171 #define RADVA(x) (((x) & 0x7) << 20) 172 #define RWSC(x) (((x) & 0x3f) << 24) 173 174 /* 175 * WEIM CSnRCR2 176 */ 177 #define RBEN(x) (((x) & 0x7)) 178 #define RBE (1 << 3) 179 #define RBEA(x) (((x) & 0x7) << 4) 180 #define RL(x) (((x) & 0x3) << 8) 181 #define PAT(x) (((x) & 0x7) << 12) 182 #define APR (1 << 15) 183 184 /* 185 * WEIM CSnWCR1 186 */ 187 #define WCSN(x) (((x) & 0x7)) 188 #define WCSA(x) (((x) & 0x7) << 3) 189 #define WEN(x) (((x) & 0x7) << 6) 190 #define WEA(x) (((x) & 0x7) << 9) 191 #define WBEN(x) (((x) & 0x7) << 12) 192 #define WBEA(x) (((x) & 0x7) << 15) 193 #define WADVN(x) (((x) & 0x7) << 18) 194 #define WADVA(x) (((x) & 0x7) << 21) 195 #define WWSC(x) (((x) & 0x3f) << 24) 196 #define WBED1 (1 << 30) 197 #define WAL (1 << 31) 198 199 /* 200 * WEIM CSnWCR2 201 */ 202 #define WBED 1 203 204 /* 205 * CSPI register definitions 206 */ 207 #define MXC_ECSPI 208 #define MXC_CSPICTRL_EN (1 << 0) 209 #define MXC_CSPICTRL_MODE (1 << 1) 210 #define MXC_CSPICTRL_XCH (1 << 2) 211 #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 212 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 213 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 214 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 215 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 216 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 217 #define MXC_CSPICTRL_MAXBITS 0xfff 218 #define MXC_CSPICTRL_TC (1 << 7) 219 #define MXC_CSPICTRL_RXOVF (1 << 6) 220 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 221 #define MAX_SPI_BYTES 32 222 223 /* Bit position inside CTRL register to be associated with SS */ 224 #define MXC_CSPICTRL_CHAN 18 225 226 /* Bit position inside CON register to be associated with SS */ 227 #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 228 #define MXC_CSPICON_POL 4 /* SCLK polarity */ 229 #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 230 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 231 #define MXC_SPI_BASE_ADDRESSES \ 232 CSPI1_BASE_ADDR, \ 233 CSPI2_BASE_ADDR, \ 234 CSPI3_BASE_ADDR, 235 236 /* 237 * Number of GPIO pins per port 238 */ 239 #define GPIO_NUM_PIN 32 240 241 #define IIM_SREV 0x24 242 #define ROM_SI_REV 0x48 243 244 #define NFC_BUF_SIZE 0x1000 245 246 /* M4IF */ 247 #define M4IF_FBPM0 0x40 248 #define M4IF_FIDBP 0x48 249 #define M4IF_GENP_WEIM_MM_MASK 0x00000001 250 #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 251 252 /* Assuming 24MHz input clock with doubler ON */ 253 /* MFI PDF */ 254 #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0)) 255 #define DP_MFD_864 (180 - 1) /* PL Dither mode */ 256 #define DP_MFN_864 180 257 #define DP_MFN_800_DIT 60 /* PL Dither mode */ 258 259 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) 260 #define DP_MFD_850 (48 - 1) 261 #define DP_MFN_850 41 262 263 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) 264 #define DP_MFD_800 (3 - 1) 265 #define DP_MFN_800 1 266 267 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) 268 #define DP_MFD_700 (24 - 1) 269 #define DP_MFN_700 7 270 271 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) 272 #define DP_MFD_665 (96 - 1) 273 #define DP_MFN_665 89 274 275 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) 276 #define DP_MFD_532 (24 - 1) 277 #define DP_MFN_532 13 278 279 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) 280 #define DP_MFD_400 (3 - 1) 281 #define DP_MFN_400 1 282 283 #define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) 284 #define DP_MFD_455 (48 - 1) 285 #define DP_MFN_455 23 286 287 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) 288 #define DP_MFD_216 (4 - 1) 289 #define DP_MFN_216 3 290 291 #define IMX_IIM_BASE (IIM_BASE_ADDR) 292 293 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 294 #include <asm/types.h> 295 296 #define __REG(x) (*((volatile u32 *)(x))) 297 #define __REG16(x) (*((volatile u16 *)(x))) 298 #define __REG8(x) (*((volatile u8 *)(x))) 299 300 struct clkctl { 301 u32 ccr; 302 u32 ccdr; 303 u32 csr; 304 u32 ccsr; 305 u32 cacrr; 306 u32 cbcdr; 307 u32 cbcmr; 308 u32 cscmr1; 309 u32 cscmr2; 310 u32 cscdr1; 311 u32 cs1cdr; 312 u32 cs2cdr; 313 u32 cdcdr; 314 u32 chsccdr; 315 u32 cscdr2; 316 u32 cscdr3; 317 u32 cscdr4; 318 u32 cwdr; 319 u32 cdhipr; 320 u32 cdcr; 321 u32 ctor; 322 u32 clpcr; 323 u32 cisr; 324 u32 cimr; 325 u32 ccosr; 326 u32 cgpr; 327 u32 ccgr0; 328 u32 ccgr1; 329 u32 ccgr2; 330 u32 ccgr3; 331 u32 ccgr4; 332 u32 ccgr5; 333 u32 ccgr6; 334 #if defined(CONFIG_MX53) 335 u32 ccgr7; 336 #endif 337 u32 cmeor; 338 }; 339 340 /* DPLL registers */ 341 struct dpll { 342 u32 dp_ctl; 343 u32 dp_config; 344 u32 dp_op; 345 u32 dp_mfd; 346 u32 dp_mfn; 347 u32 dp_mfn_minus; 348 u32 dp_mfn_plus; 349 u32 dp_hfs_op; 350 u32 dp_hfs_mfd; 351 u32 dp_hfs_mfn; 352 u32 dp_mfn_togc; 353 u32 dp_destat; 354 }; 355 /* WEIM registers */ 356 struct weim { 357 u32 cs0gcr1; 358 u32 cs0gcr2; 359 u32 cs0rcr1; 360 u32 cs0rcr2; 361 u32 cs0wcr1; 362 u32 cs0wcr2; 363 u32 cs1gcr1; 364 u32 cs1gcr2; 365 u32 cs1rcr1; 366 u32 cs1rcr2; 367 u32 cs1wcr1; 368 u32 cs1wcr2; 369 u32 cs2gcr1; 370 u32 cs2gcr2; 371 u32 cs2rcr1; 372 u32 cs2rcr2; 373 u32 cs2wcr1; 374 u32 cs2wcr2; 375 u32 cs3gcr1; 376 u32 cs3gcr2; 377 u32 cs3rcr1; 378 u32 cs3rcr2; 379 u32 cs3wcr1; 380 u32 cs3wcr2; 381 u32 cs4gcr1; 382 u32 cs4gcr2; 383 u32 cs4rcr1; 384 u32 cs4rcr2; 385 u32 cs4wcr1; 386 u32 cs4wcr2; 387 u32 cs5gcr1; 388 u32 cs5gcr2; 389 u32 cs5rcr1; 390 u32 cs5rcr2; 391 u32 cs5wcr1; 392 u32 cs5wcr2; 393 u32 wcr; 394 u32 wiar; 395 u32 ear; 396 }; 397 398 #if defined(CONFIG_MX51) 399 struct iomuxc { 400 u32 gpr[2]; 401 u32 omux0; 402 u32 omux1; 403 u32 omux2; 404 u32 omux3; 405 u32 omux4; 406 }; 407 #elif defined(CONFIG_MX53) 408 struct iomuxc { 409 u32 gpr[3]; 410 u32 omux0; 411 u32 omux1; 412 u32 omux2; 413 u32 omux3; 414 u32 omux4; 415 }; 416 #endif 417 418 #define IOMUXC_GPR2_BITMAP_SPWG 0 419 #define IOMUXC_GPR2_BITMAP_JEIDA 1 420 421 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 422 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 423 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \ 424 IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 425 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \ 426 IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 427 428 #define IOMUXC_GPR2_DATA_WIDTH_18 0 429 #define IOMUXC_GPR2_DATA_WIDTH_24 1 430 431 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 432 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 433 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \ 434 IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 435 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \ 436 IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 437 438 #define IOMUXC_GPR2_MODE_DISABLED 0 439 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 440 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 441 442 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 443 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 444 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \ 445 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 446 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \ 447 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 448 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \ 449 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 450 451 /* System Reset Controller (SRC) */ 452 struct src { 453 u32 scr; 454 u32 sbmr; 455 u32 srsr; 456 u32 reserved1[2]; 457 u32 sisr; 458 u32 simr; 459 }; 460 461 struct srtc_regs { 462 u32 lpscmr; /* 0x00 */ 463 u32 lpsclr; /* 0x04 */ 464 u32 lpsar; /* 0x08 */ 465 u32 lpsmcr; /* 0x0c */ 466 u32 lpcr; /* 0x10 */ 467 u32 lpsr; /* 0x14 */ 468 u32 lppdr; /* 0x18 */ 469 u32 lpgr; /* 0x1c */ 470 u32 hpcmr; /* 0x20 */ 471 u32 hpclr; /* 0x24 */ 472 u32 hpamr; /* 0x28 */ 473 u32 hpalr; /* 0x2c */ 474 u32 hpcr; /* 0x30 */ 475 u32 hpisr; /* 0x34 */ 476 u32 hpienr; /* 0x38 */ 477 }; 478 479 /* CSPI registers */ 480 struct cspi_regs { 481 u32 rxdata; 482 u32 txdata; 483 u32 ctrl; 484 u32 cfg; 485 u32 intr; 486 u32 dma; 487 u32 stat; 488 u32 period; 489 }; 490 491 struct iim_regs { 492 u32 stat; 493 u32 statm; 494 u32 err; 495 u32 emask; 496 u32 fctl; 497 u32 ua; 498 u32 la; 499 u32 sdat; 500 u32 prev; 501 u32 srev; 502 u32 prg_p; 503 u32 scs0; 504 u32 scs1; 505 u32 scs2; 506 u32 scs3; 507 u32 res0[0x1f1]; 508 struct fuse_bank { 509 u32 fuse_regs[0x20]; 510 u32 fuse_rsvd[0xe0]; 511 #if defined(CONFIG_MX51) 512 } bank[4]; 513 #elif defined(CONFIG_MX53) 514 } bank[5]; 515 #endif 516 }; 517 518 struct fuse_bank0_regs { 519 u32 fuse0_7[8]; 520 u32 uid[8]; 521 u32 fuse16_23[8]; 522 #if defined(CONFIG_MX51) 523 u32 imei[8]; 524 #elif defined(CONFIG_MX53) 525 u32 gp[8]; 526 #endif 527 }; 528 529 struct fuse_bank1_regs { 530 u32 fuse0_8[9]; 531 u32 mac_addr[6]; 532 u32 fuse15_31[0x11]; 533 }; 534 535 #if defined(CONFIG_MX53) 536 struct fuse_bank4_regs { 537 u32 fuse0_4[5]; 538 u32 gp[3]; 539 u32 fuse8_31[0x18]; 540 }; 541 #endif 542 543 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) 544 #define PWMCR_DOZEEN (1 << 24) 545 #define PWMCR_WAITEN (1 << 23) 546 #define PWMCR_DBGEN (1 << 22) 547 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) 548 #define PWMCR_CLKSRC_IPG (1 << 16) 549 #define PWMCR_EN (1 << 0) 550 551 struct pwm_regs { 552 u32 cr; 553 u32 sr; 554 u32 ir; 555 u32 sar; 556 u32 pr; 557 u32 cnr; 558 }; 559 560 #endif /* __ASSEMBLER__*/ 561 562 #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ 563