1 /* 2 * Copyright © 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 */ 25 26 #ifndef AC_GPU_INFO_H 27 #define AC_GPU_INFO_H 28 29 #include <stddef.h> 30 #include <stdint.h> 31 #include <stdbool.h> 32 #include "amd_family.h" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* Prior to C11 the following may trigger a typedef redeclaration warning */ 39 typedef struct amdgpu_device *amdgpu_device_handle; 40 struct amdgpu_gpu_info; 41 42 struct radeon_info { 43 /* PCI info: domain:bus:dev:func */ 44 uint32_t pci_domain; 45 uint32_t pci_bus; 46 uint32_t pci_dev; 47 uint32_t pci_func; 48 49 /* Device info. */ 50 uint32_t pci_id; 51 enum radeon_family family; 52 enum chip_class chip_class; 53 uint32_t pte_fragment_size; 54 uint32_t gart_page_size; 55 uint64_t gart_size; 56 uint64_t vram_size; 57 uint64_t vram_vis_size; 58 uint64_t max_alloc_size; 59 uint32_t min_alloc_size; 60 bool has_dedicated_vram; 61 bool has_virtual_memory; 62 bool gfx_ib_pad_with_type2; 63 bool has_hw_decode; 64 unsigned ib_start_alignment; 65 uint32_t num_sdma_rings; 66 uint32_t num_compute_rings; 67 uint32_t uvd_fw_version; 68 uint32_t vce_fw_version; 69 uint32_t me_fw_version; 70 uint32_t me_fw_feature; 71 uint32_t pfp_fw_version; 72 uint32_t pfp_fw_feature; 73 uint32_t ce_fw_version; 74 uint32_t ce_fw_feature; 75 uint32_t vce_harvest_config; 76 uint32_t clock_crystal_freq; 77 uint32_t tcc_cache_line_size; 78 79 /* Kernel info. */ 80 uint32_t drm_major; /* version */ 81 uint32_t drm_minor; 82 uint32_t drm_patchlevel; 83 bool has_userptr; 84 bool has_syncobj; 85 bool has_syncobj_wait_for_submit; 86 bool has_fence_to_handle; 87 bool has_ctx_priority; 88 89 /* Shader cores. */ 90 uint32_t r600_max_quad_pipes; /* wave size / 16 */ 91 uint32_t max_shader_clock; 92 uint32_t num_good_compute_units; 93 uint32_t max_se; /* shader engines */ 94 uint32_t max_sh_per_se; /* shader arrays per shader engine */ 95 96 /* Render backends (color + depth blocks). */ 97 uint32_t r300_num_gb_pipes; 98 uint32_t r300_num_z_pipes; 99 uint32_t r600_gb_backend_map; /* R600 harvest config */ 100 bool r600_gb_backend_map_valid; 101 uint32_t r600_num_banks; 102 uint32_t num_render_backends; 103 uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ 104 uint32_t pipe_interleave_bytes; 105 uint32_t enabled_rb_mask; /* GCN harvest config */ 106 107 uint64_t max_alignment; /* from addrlib */ 108 /* Tile modes. */ 109 uint32_t si_tile_mode_array[32]; 110 uint32_t cik_macrotile_mode_array[16]; 111 }; 112 113 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, 114 struct radeon_info *info, 115 struct amdgpu_gpu_info *amdinfo); 116 117 void ac_compute_driver_uuid(char *uuid, size_t size); 118 119 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size); 120 void ac_print_gpu_info(struct radeon_info *info); 121 122 #ifdef __cplusplus 123 } 124 #endif 125 126 #endif /* AC_GPU_INFO_H */ 127