1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "freedreno_blitter.h"
28 #include "freedreno_resource.h"
29
30 #include "fd5_blitter.h"
31 #include "fd5_format.h"
32 #include "fd5_emit.h"
33
34 /* Make sure none of the requested dimensions extend beyond the size of the
35 * resource. Not entirely sure why this happens, but sometimes it does, and
36 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
37 * back to u_blitter
38 */
39 static bool
ok_dims(const struct pipe_resource * r,const struct pipe_box * b,int lvl)40 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
41 {
42 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
43 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
44 (b->z >= 0) && (b->z + b->depth <= u_minify(r->depth0, lvl));
45 }
46
47 /* Not sure if format restrictions differ for src and dst, or if
48 * they only matter when src fmt != dst fmt.. but there appear to
49 * be *some* limitations so let's just start blacklisting stuff that
50 * piglit complains about
51 */
52 static bool
ok_format(enum pipe_format fmt)53 ok_format(enum pipe_format fmt)
54 {
55 if (util_format_is_compressed(fmt))
56 return false;
57
58 switch (fmt) {
59 case PIPE_FORMAT_R10G10B10A2_SSCALED:
60 case PIPE_FORMAT_R10G10B10A2_SNORM:
61 case PIPE_FORMAT_B10G10R10A2_USCALED:
62 case PIPE_FORMAT_B10G10R10A2_SSCALED:
63 case PIPE_FORMAT_B10G10R10A2_SNORM:
64 case PIPE_FORMAT_R10G10B10A2_UNORM:
65 case PIPE_FORMAT_R10G10B10A2_USCALED:
66 case PIPE_FORMAT_B10G10R10A2_UNORM:
67 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
68 case PIPE_FORMAT_B10G10R10A2_UINT:
69 case PIPE_FORMAT_R10G10B10A2_UINT:
70 return false;
71 default:
72 break;
73 }
74
75 if (fd5_pipe2color(fmt) == ~0)
76 return false;
77
78 return true;
79 }
80
81 static bool
can_do_blit(const struct pipe_blit_info * info)82 can_do_blit(const struct pipe_blit_info *info)
83 {
84 /* I think we can do scaling, but not in z dimension since that would
85 * require blending..
86 */
87 if (info->dst.box.depth != info->src.box.depth)
88 return false;
89
90 if (!ok_format(info->dst.format))
91 return false;
92
93 if (!ok_format(info->src.format))
94 return false;
95
96 /* hw ignores {SRC,DST}_INFO.COLOR_SWAP if {SRC,DST}_INFO.TILE_MODE
97 * is set (not linear). We can kind of get around that when tiling/
98 * untiling by setting both src and dst COLOR_SWAP=WZYX, but that
99 * means the formats must match:
100 */
101 if ((fd_resource(info->dst.resource)->tile_mode ||
102 fd_resource(info->src.resource)->tile_mode) &&
103 info->dst.format != info->src.format)
104 return false;
105
106 /* until we figure out a few more registers: */
107 if ((info->dst.box.width != info->src.box.width) ||
108 (info->dst.box.height != info->src.box.height))
109 return false;
110
111 /* src box can be inverted, which we don't support.. dst box cannot: */
112 if ((info->src.box.width < 0) || (info->src.box.height < 0))
113 return false;
114
115 if (!ok_dims(info->src.resource, &info->src.box, info->src.level))
116 return false;
117
118 if (!ok_dims(info->dst.resource, &info->dst.box, info->dst.level))
119 return false;
120
121 debug_assert(info->dst.box.width >= 0);
122 debug_assert(info->dst.box.height >= 0);
123 debug_assert(info->dst.box.depth >= 0);
124
125 if (info->dst.resource->nr_samples + info->src.resource->nr_samples)
126 return false;
127
128 if (info->scissor_enable)
129 return false;
130
131 if (info->window_rectangle_include)
132 return false;
133
134 if (info->render_condition_enable)
135 return false;
136
137 if (info->alpha_blend)
138 return false;
139
140 if (info->filter != PIPE_TEX_FILTER_NEAREST)
141 return false;
142
143 if (info->mask != util_format_get_mask(info->src.format))
144 return false;
145
146 if (info->mask != util_format_get_mask(info->dst.format))
147 return false;
148
149 return true;
150 }
151
152 static void
emit_setup(struct fd_ringbuffer * ring)153 emit_setup(struct fd_ringbuffer *ring)
154 {
155 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
156 OUT_RING(ring, LRZ_FLUSH);
157
158 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
159 OUT_RING(ring, 0x0);
160
161 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
162 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
163
164 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
165 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
166
167 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
168 OUT_WFI5(ring);
169 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
170 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
171
172 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
173 OUT_RING(ring, 0x00000008);
174
175 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2100, 1);
176 OUT_RING(ring, 0x86000000); /* UNKNOWN_2100 */
177
178 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2180, 1);
179 OUT_RING(ring, 0x86000000); /* UNKNOWN_2180 */
180
181 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2184, 1);
182 OUT_RING(ring, 0x00000009); /* UNKNOWN_2184 */
183
184 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
185 OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
186
187 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
188 OUT_RING(ring, 0x00000004); /* RB_MODE_CNTL */
189
190 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
191 OUT_RING(ring, 0x0000000c); /* SP_MODE_CNTL */
192
193 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
194 OUT_RING(ring, 0x00000344); /* TPL1_MODE_CNTL */
195
196 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
197 OUT_RING(ring, 0x00000002); /* HLSQ_MODE_CNTL */
198
199 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
200 OUT_RING(ring, 0x00000181); /* GRAS_CL_CNTL */
201 }
202
203 /* buffers need to be handled specially since x/width can exceed the bounds
204 * supported by hw.. if necessary decompose into (potentially) two 2D blits
205 */
206 static void
emit_blit_buffer(struct fd_ringbuffer * ring,const struct pipe_blit_info * info)207 emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
208 {
209 const struct pipe_box *sbox = &info->src.box;
210 const struct pipe_box *dbox = &info->dst.box;
211 struct fd_resource *src, *dst;
212 unsigned sshift, dshift;
213
214 src = fd_resource(info->src.resource);
215 dst = fd_resource(info->dst.resource);
216
217 debug_assert(src->cpp == 1);
218 debug_assert(dst->cpp == 1);
219 debug_assert(info->src.resource->format == info->dst.resource->format);
220 debug_assert((sbox->y == 0) && (sbox->height == 1));
221 debug_assert((dbox->y == 0) && (dbox->height == 1));
222 debug_assert((sbox->z == 0) && (sbox->depth == 1));
223 debug_assert((dbox->z == 0) && (dbox->depth == 1));
224 debug_assert(sbox->width == dbox->width);
225 debug_assert(info->src.level == 0);
226 debug_assert(info->dst.level == 0);
227
228 /*
229 * Buffers can have dimensions bigger than max width, remap into
230 * multiple 1d blits to fit within max dimension
231 *
232 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
233 * seems to prevent overfetch related faults. Not quite sure what
234 * the deal is there.
235 *
236 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
237 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
238 * difference. On top of already splitting up the blit so width
239 * isn't > 16k.
240 *
241 * We perhaps could do a bit better, if src and dst are aligned but
242 * in the worst case this means we have to split the copy up into
243 * 16k (0x4000) minus 64 (0x40).
244 */
245
246 sshift = sbox->x & 0x3f;
247 dshift = dbox->x & 0x3f;
248
249 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
250 unsigned soff, doff, w, p;
251
252 soff = (sbox->x + off) & ~0x3f;
253 doff = (dbox->x + off) & ~0x3f;
254
255 w = MIN2(sbox->width - off, (0x4000 - 0x40));
256 p = align(w, 64);
257
258 debug_assert((soff + w) <= fd_bo_size(src->bo));
259 debug_assert((doff + w) <= fd_bo_size(dst->bo));
260
261 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
262 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(BLIT2D));
263
264 /*
265 * Emit source:
266 */
267 OUT_PKT4(ring, REG_A5XX_RB_2D_SRC_INFO, 9);
268 OUT_RING(ring, A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
269 A5XX_RB_2D_SRC_INFO_TILE_MODE(TILE5_LINEAR) |
270 A5XX_RB_2D_SRC_INFO_COLOR_SWAP(WZYX));
271 OUT_RELOC(ring, src->bo, soff, 0, 0); /* RB_2D_SRC_LO/HI */
272 OUT_RING(ring, A5XX_RB_2D_SRC_SIZE_PITCH(p) |
273 A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(128));
274 OUT_RING(ring, 0x00000000);
275 OUT_RING(ring, 0x00000000);
276 OUT_RING(ring, 0x00000000);
277 OUT_RING(ring, 0x00000000);
278 OUT_RING(ring, 0x00000000);
279
280 OUT_PKT4(ring, REG_A5XX_GRAS_2D_SRC_INFO, 1);
281 OUT_RING(ring, A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
282 A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(WZYX));
283
284 /*
285 * Emit destination:
286 */
287 OUT_PKT4(ring, REG_A5XX_RB_2D_DST_INFO, 9);
288 OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
289 A5XX_RB_2D_DST_INFO_TILE_MODE(TILE5_LINEAR) |
290 A5XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
291 OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
292 OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(p) |
293 A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(128));
294 OUT_RING(ring, 0x00000000);
295 OUT_RING(ring, 0x00000000);
296 OUT_RING(ring, 0x00000000);
297 OUT_RING(ring, 0x00000000);
298 OUT_RING(ring, 0x00000000);
299
300 OUT_PKT4(ring, REG_A5XX_GRAS_2D_DST_INFO, 1);
301 OUT_RING(ring, A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
302 A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(WZYX));
303
304 /*
305 * Blit command:
306 */
307 OUT_PKT7(ring, CP_BLIT, 5);
308 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_COPY));
309 OUT_RING(ring, CP_BLIT_1_SRC_X1(sshift) | CP_BLIT_1_SRC_Y1(0));
310 OUT_RING(ring, CP_BLIT_2_SRC_X2(sshift+w-1) | CP_BLIT_2_SRC_Y2(0));
311 OUT_RING(ring, CP_BLIT_3_DST_X1(dshift) | CP_BLIT_3_DST_Y1(0));
312 OUT_RING(ring, CP_BLIT_4_DST_X2(dshift+w-1) | CP_BLIT_4_DST_Y2(0));
313
314 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
315 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(END2D));
316
317 OUT_WFI5(ring);
318 }
319 }
320
321 static void
emit_blit(struct fd_ringbuffer * ring,const struct pipe_blit_info * info)322 emit_blit(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
323 {
324 const struct pipe_box *sbox = &info->src.box;
325 const struct pipe_box *dbox = &info->dst.box;
326 struct fd_resource *src, *dst;
327 struct fd_resource_slice *sslice, *dslice;
328 enum a5xx_color_fmt sfmt, dfmt;
329 enum a5xx_tile_mode stile, dtile;
330 enum a3xx_color_swap sswap, dswap;
331 unsigned ssize, dsize, spitch, dpitch;
332 unsigned sx1, sy1, sx2, sy2;
333 unsigned dx1, dy1, dx2, dy2;
334
335 src = fd_resource(info->src.resource);
336 dst = fd_resource(info->dst.resource);
337
338 sslice = fd_resource_slice(src, info->src.level);
339 dslice = fd_resource_slice(dst, info->dst.level);
340
341 sfmt = fd5_pipe2color(info->src.format);
342 dfmt = fd5_pipe2color(info->dst.format);
343
344 stile = fd_resource_level_linear(info->src.resource, info->src.level) ?
345 TILE5_LINEAR : src->tile_mode;
346 dtile = fd_resource_level_linear(info->dst.resource, info->dst.level) ?
347 TILE5_LINEAR : dst->tile_mode;
348
349 sswap = fd5_pipe2swap(info->src.format);
350 dswap = fd5_pipe2swap(info->dst.format);
351
352 spitch = sslice->pitch * src->cpp;
353 dpitch = dslice->pitch * dst->cpp;
354
355 /* if dtile, then dswap ignored by hw, and likewise if stile then sswap
356 * ignored by hw.. but in this case we have already rejected the blit
357 * if src and dst formats differ, so juse use WZYX for both src and
358 * dst swap mode (so we don't change component order)
359 */
360 if (stile || dtile) {
361 debug_assert(info->src.format == info->dst.format);
362 sswap = dswap = WZYX;
363 }
364
365 sx1 = sbox->x;
366 sy1 = sbox->y;
367 sx2 = sbox->x + sbox->width - 1;
368 sy2 = sbox->y + sbox->height - 1;
369
370 dx1 = dbox->x;
371 dy1 = dbox->y;
372 dx2 = dbox->x + dbox->width - 1;
373 dy2 = dbox->y + dbox->height - 1;
374
375 if (info->src.resource->target == PIPE_TEXTURE_3D)
376 ssize = sslice->size0;
377 else
378 ssize = src->layer_size;
379
380 if (info->dst.resource->target == PIPE_TEXTURE_3D)
381 dsize = dslice->size0;
382 else
383 dsize = dst->layer_size;
384
385 for (unsigned i = 0; i < info->dst.box.depth; i++) {
386 unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i);
387 unsigned doff = fd_resource_offset(dst, info->dst.level, dbox->z + i);
388
389 debug_assert((soff + (sbox->height * spitch)) <= fd_bo_size(src->bo));
390 debug_assert((doff + (dbox->height * dpitch)) <= fd_bo_size(dst->bo));
391
392 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
393 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(BLIT2D));
394
395 /*
396 * Emit source:
397 */
398 OUT_PKT4(ring, REG_A5XX_RB_2D_SRC_INFO, 9);
399 OUT_RING(ring, A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
400 A5XX_RB_2D_SRC_INFO_TILE_MODE(stile) |
401 A5XX_RB_2D_SRC_INFO_COLOR_SWAP(sswap));
402 OUT_RELOC(ring, src->bo, soff, 0, 0); /* RB_2D_SRC_LO/HI */
403 OUT_RING(ring, A5XX_RB_2D_SRC_SIZE_PITCH(spitch) |
404 A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(ssize));
405 OUT_RING(ring, 0x00000000);
406 OUT_RING(ring, 0x00000000);
407 OUT_RING(ring, 0x00000000);
408 OUT_RING(ring, 0x00000000);
409 OUT_RING(ring, 0x00000000);
410
411 OUT_PKT4(ring, REG_A5XX_GRAS_2D_SRC_INFO, 1);
412 OUT_RING(ring, A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
413 A5XX_GRAS_2D_SRC_INFO_TILE_MODE(stile) |
414 A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(sswap));
415
416 /*
417 * Emit destination:
418 */
419 OUT_PKT4(ring, REG_A5XX_RB_2D_DST_INFO, 9);
420 OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
421 A5XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
422 A5XX_RB_2D_DST_INFO_COLOR_SWAP(dswap));
423 OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
424 OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(dpitch) |
425 A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(dsize));
426 OUT_RING(ring, 0x00000000);
427 OUT_RING(ring, 0x00000000);
428 OUT_RING(ring, 0x00000000);
429 OUT_RING(ring, 0x00000000);
430 OUT_RING(ring, 0x00000000);
431
432 OUT_PKT4(ring, REG_A5XX_GRAS_2D_DST_INFO, 1);
433 OUT_RING(ring, A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(dfmt) |
434 A5XX_GRAS_2D_DST_INFO_TILE_MODE(dtile) |
435 A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(dswap));
436
437 /*
438 * Blit command:
439 */
440 OUT_PKT7(ring, CP_BLIT, 5);
441 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_COPY));
442 OUT_RING(ring, CP_BLIT_1_SRC_X1(sx1) | CP_BLIT_1_SRC_Y1(sy1));
443 OUT_RING(ring, CP_BLIT_2_SRC_X2(sx2) | CP_BLIT_2_SRC_Y2(sy2));
444 OUT_RING(ring, CP_BLIT_3_DST_X1(dx1) | CP_BLIT_3_DST_Y1(dy1));
445 OUT_RING(ring, CP_BLIT_4_DST_X2(dx2) | CP_BLIT_4_DST_Y2(dy2));
446
447 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
448 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(END2D));
449 }
450 }
451
452 void
fd5_blitter_blit(struct fd_context * ctx,const struct pipe_blit_info * info)453 fd5_blitter_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
454 {
455 struct fd_batch *batch;
456
457 if (!can_do_blit(info)) {
458 fd_blitter_blit(ctx, info);
459 return;
460 }
461
462 batch = fd_batch_create(ctx, true);
463
464 fd5_emit_restore(batch, batch->draw);
465 fd5_emit_lrz_flush(batch->draw);
466
467 emit_setup(batch->draw);
468
469 if ((info->src.resource->target == PIPE_BUFFER) &&
470 (info->dst.resource->target == PIPE_BUFFER)) {
471 assert(fd_resource(info->src.resource)->tile_mode == TILE5_LINEAR);
472 assert(fd_resource(info->dst.resource)->tile_mode == TILE5_LINEAR);
473 emit_blit_buffer(batch->draw, info);
474 } else {
475 /* I don't *think* we need to handle blits between buffer <-> !buffer */
476 debug_assert(info->src.resource->target != PIPE_BUFFER);
477 debug_assert(info->dst.resource->target != PIPE_BUFFER);
478 emit_blit(batch->draw, info);
479 }
480
481 fd_resource(info->dst.resource)->valid = true;
482 batch->needs_flush = true;
483
484 fd_batch_flush(batch, false, false);
485 }
486
487 unsigned
fd5_tile_mode(const struct pipe_resource * tmpl)488 fd5_tile_mode(const struct pipe_resource *tmpl)
489 {
490 /* basically just has to be a format we can blit, so uploads/downloads
491 * via linear staging buffer works:
492 */
493 if (ok_format(tmpl->format))
494 return TILE5_3;
495
496 return TILE5_LINEAR;
497 }
498