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1 // SPDX-License-Identifier: GPL-2.0
2 /**
3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4  *
5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6  *
7  * Authors: Felipe Balbi <balbi@ti.com>,
8  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9  *
10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
11  * to uboot.
12  *
13  * commit c00552ebaf : Merge 3.18-rc7 into usb-next
14  */
15 
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 
19 #include <linux/usb/ch9.h>
20 #include <linux/usb/gadget.h>
21 #include <linux/usb/composite.h>
22 
23 #include "core.h"
24 #include "gadget.h"
25 #include "io.h"
26 
27 #include "linux-compat.h"
28 
29 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
30 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
31 		struct dwc3_ep *dep, struct dwc3_request *req);
32 
dwc3_ep0_state_string(enum dwc3_ep0_state state)33 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
34 {
35 	switch (state) {
36 	case EP0_UNCONNECTED:
37 		return "Unconnected";
38 	case EP0_SETUP_PHASE:
39 		return "Setup Phase";
40 	case EP0_DATA_PHASE:
41 		return "Data Phase";
42 	case EP0_STATUS_PHASE:
43 		return "Status Phase";
44 	default:
45 		return "UNKNOWN";
46 	}
47 }
48 
dwc3_ep0_start_trans(struct dwc3 * dwc,u8 epnum,dma_addr_t buf_dma,u32 len,u32 type,unsigned chain)49 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
50 				u32 len, u32 type, unsigned chain)
51 {
52 	struct dwc3_gadget_ep_cmd_params params;
53 	struct dwc3_trb			*trb;
54 	struct dwc3_ep			*dep;
55 
56 	int				ret;
57 
58 	dep = dwc->eps[epnum];
59 	if (dep->flags & DWC3_EP_BUSY) {
60 		dev_vdbg(dwc->dev, "%s still busy", dep->name);
61 		return 0;
62 	}
63 
64 	trb = &dwc->ep0_trb[dep->free_slot];
65 
66 	if (chain)
67 		dep->free_slot++;
68 
69 	trb->bpl = lower_32_bits(buf_dma);
70 	trb->bph = upper_32_bits(buf_dma);
71 	trb->size = len;
72 	trb->ctrl = type;
73 
74 	trb->ctrl |= (DWC3_TRB_CTRL_HWO
75 			| DWC3_TRB_CTRL_ISP_IMI);
76 
77 	if (chain)
78 		trb->ctrl |= DWC3_TRB_CTRL_CHN;
79 	else
80 		trb->ctrl |= (DWC3_TRB_CTRL_IOC
81 				| DWC3_TRB_CTRL_LST);
82 
83 	dwc3_flush_cache((uintptr_t)buf_dma, len);
84 	dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
85 
86 	if (chain)
87 		return 0;
88 
89 	memset(&params, 0, sizeof(params));
90 	params.param0 = upper_32_bits(dwc->ep0_trb_addr);
91 	params.param1 = lower_32_bits(dwc->ep0_trb_addr);
92 
93 	ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
94 			DWC3_DEPCMD_STARTTRANSFER, &params);
95 	if (ret < 0) {
96 		dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
97 		return ret;
98 	}
99 
100 	dep->flags |= DWC3_EP_BUSY;
101 	dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
102 			dep->number);
103 
104 	dwc->ep0_next_event = DWC3_EP0_COMPLETE;
105 
106 	return 0;
107 }
108 
__dwc3_gadget_ep0_queue(struct dwc3_ep * dep,struct dwc3_request * req)109 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
110 		struct dwc3_request *req)
111 {
112 	struct dwc3		*dwc = dep->dwc;
113 
114 	req->request.actual	= 0;
115 	req->request.status	= -EINPROGRESS;
116 	req->epnum		= dep->number;
117 
118 	list_add_tail(&req->list, &dep->request_list);
119 
120 	/*
121 	 * Gadget driver might not be quick enough to queue a request
122 	 * before we get a Transfer Not Ready event on this endpoint.
123 	 *
124 	 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
125 	 * flag is set, it's telling us that as soon as Gadget queues the
126 	 * required request, we should kick the transfer here because the
127 	 * IRQ we were waiting for is long gone.
128 	 */
129 	if (dep->flags & DWC3_EP_PENDING_REQUEST) {
130 		unsigned	direction;
131 
132 		direction = !!(dep->flags & DWC3_EP0_DIR_IN);
133 
134 		if (dwc->ep0state != EP0_DATA_PHASE) {
135 			dev_WARN(dwc->dev, "Unexpected pending request\n");
136 			return 0;
137 		}
138 
139 		__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
140 
141 		dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
142 				DWC3_EP0_DIR_IN);
143 
144 		return 0;
145 	}
146 
147 	/*
148 	 * In case gadget driver asked us to delay the STATUS phase,
149 	 * handle it here.
150 	 */
151 	if (dwc->delayed_status) {
152 		unsigned	direction;
153 
154 		direction = !dwc->ep0_expect_in;
155 		dwc->delayed_status = false;
156 		usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
157 
158 		if (dwc->ep0state == EP0_STATUS_PHASE)
159 			__dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
160 		else
161 			dev_dbg(dwc->dev, "too early for delayed status");
162 
163 		return 0;
164 	}
165 
166 	/*
167 	 * Unfortunately we have uncovered a limitation wrt the Data Phase.
168 	 *
169 	 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
170 	 * come before issueing Start Transfer command, but if we do, we will
171 	 * miss situations where the host starts another SETUP phase instead of
172 	 * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
173 	 * Layer Compliance Suite.
174 	 *
175 	 * The problem surfaces due to the fact that in case of back-to-back
176 	 * SETUP packets there will be no XferNotReady(DATA) generated and we
177 	 * will be stuck waiting for XferNotReady(DATA) forever.
178 	 *
179 	 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
180 	 * it tells us to start Data Phase right away. It also mentions that if
181 	 * we receive a SETUP phase instead of the DATA phase, core will issue
182 	 * XferComplete for the DATA phase, before actually initiating it in
183 	 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
184 	 * can only be used to print some debugging logs, as the core expects
185 	 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
186 	 * just so it completes right away, without transferring anything and,
187 	 * only then, we can go back to the SETUP phase.
188 	 *
189 	 * Because of this scenario, SNPS decided to change the programming
190 	 * model of control transfers and support on-demand transfers only for
191 	 * the STATUS phase. To fix the issue we have now, we will always wait
192 	 * for gadget driver to queue the DATA phase's struct usb_request, then
193 	 * start it right away.
194 	 *
195 	 * If we're actually in a 2-stage transfer, we will wait for
196 	 * XferNotReady(STATUS).
197 	 */
198 	if (dwc->three_stage_setup) {
199 		unsigned        direction;
200 
201 		direction = dwc->ep0_expect_in;
202 		dwc->ep0state = EP0_DATA_PHASE;
203 
204 		__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
205 
206 		dep->flags &= ~DWC3_EP0_DIR_IN;
207 	}
208 
209 	return 0;
210 }
211 
dwc3_gadget_ep0_queue(struct usb_ep * ep,struct usb_request * request,gfp_t gfp_flags)212 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
213 		gfp_t gfp_flags)
214 {
215 	struct dwc3_request		*req = to_dwc3_request(request);
216 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
217 	struct dwc3			*dwc = dep->dwc;
218 
219 	unsigned long			flags;
220 
221 	int				ret;
222 
223 	spin_lock_irqsave(&dwc->lock, flags);
224 	if (!dep->endpoint.desc) {
225 		dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
226 				request, dep->name);
227 		ret = -ESHUTDOWN;
228 		goto out;
229 	}
230 
231 	/* we share one TRB for ep0/1 */
232 	if (!list_empty(&dep->request_list)) {
233 		ret = -EBUSY;
234 		goto out;
235 	}
236 
237 	dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
238 			request, dep->name, request->length,
239 			dwc3_ep0_state_string(dwc->ep0state));
240 
241 	ret = __dwc3_gadget_ep0_queue(dep, req);
242 
243 out:
244 	spin_unlock_irqrestore(&dwc->lock, flags);
245 
246 	return ret;
247 }
248 
dwc3_ep0_stall_and_restart(struct dwc3 * dwc)249 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
250 {
251 	struct dwc3_ep		*dep;
252 
253 	/* reinitialize physical ep1 */
254 	dep = dwc->eps[1];
255 	dep->flags = DWC3_EP_ENABLED;
256 
257 	/* stall is always issued on EP0 */
258 	dep = dwc->eps[0];
259 	__dwc3_gadget_ep_set_halt(dep, 1, false);
260 	dep->flags = DWC3_EP_ENABLED;
261 	dwc->delayed_status = false;
262 
263 	if (!list_empty(&dep->request_list)) {
264 		struct dwc3_request	*req;
265 
266 		req = next_request(&dep->request_list);
267 		dwc3_gadget_giveback(dep, req, -ECONNRESET);
268 	}
269 
270 	dwc->ep0state = EP0_SETUP_PHASE;
271 	dwc3_ep0_out_start(dwc);
272 }
273 
__dwc3_gadget_ep0_set_halt(struct usb_ep * ep,int value)274 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
275 {
276 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
277 	struct dwc3			*dwc = dep->dwc;
278 
279 	dwc3_ep0_stall_and_restart(dwc);
280 
281 	return 0;
282 }
283 
dwc3_gadget_ep0_set_halt(struct usb_ep * ep,int value)284 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
285 {
286 	unsigned long			flags;
287 	int				ret;
288 
289 	spin_lock_irqsave(&dwc->lock, flags);
290 	ret = __dwc3_gadget_ep0_set_halt(ep, value);
291 	spin_unlock_irqrestore(&dwc->lock, flags);
292 
293 	return ret;
294 }
295 
dwc3_ep0_out_start(struct dwc3 * dwc)296 void dwc3_ep0_out_start(struct dwc3 *dwc)
297 {
298 	int				ret;
299 
300 	ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
301 				   DWC3_TRBCTL_CONTROL_SETUP, 0);
302 	WARN_ON(ret < 0);
303 }
304 
dwc3_wIndex_to_dep(struct dwc3 * dwc,__le16 wIndex_le)305 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
306 {
307 	struct dwc3_ep		*dep;
308 	u32			windex = le16_to_cpu(wIndex_le);
309 	u32			epnum;
310 
311 	epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
312 	if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
313 		epnum |= 1;
314 
315 	dep = dwc->eps[epnum];
316 	if (dep->flags & DWC3_EP_ENABLED)
317 		return dep;
318 
319 	return NULL;
320 }
321 
dwc3_ep0_status_cmpl(struct usb_ep * ep,struct usb_request * req)322 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
323 {
324 }
325 /*
326  * ch 9.4.5
327  */
dwc3_ep0_handle_status(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)328 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
329 		struct usb_ctrlrequest *ctrl)
330 {
331 	struct dwc3_ep		*dep;
332 	u32			recip;
333 	u32			reg;
334 	u16			usb_status = 0;
335 	__le16			*response_pkt;
336 
337 	recip = ctrl->bRequestType & USB_RECIP_MASK;
338 	switch (recip) {
339 	case USB_RECIP_DEVICE:
340 		/*
341 		 * LTM will be set once we know how to set this in HW.
342 		 */
343 		usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
344 
345 		if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
346 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
347 			if (reg & DWC3_DCTL_INITU1ENA)
348 				usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
349 			if (reg & DWC3_DCTL_INITU2ENA)
350 				usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
351 		}
352 
353 		break;
354 
355 	case USB_RECIP_INTERFACE:
356 		/*
357 		 * Function Remote Wake Capable	D0
358 		 * Function Remote Wakeup	D1
359 		 */
360 		break;
361 
362 	case USB_RECIP_ENDPOINT:
363 		dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
364 		if (!dep)
365 			return -EINVAL;
366 
367 		if (dep->flags & DWC3_EP_STALL)
368 			usb_status = 1 << USB_ENDPOINT_HALT;
369 		break;
370 	default:
371 		return -EINVAL;
372 	}
373 
374 	response_pkt = (__le16 *) dwc->setup_buf;
375 	*response_pkt = cpu_to_le16(usb_status);
376 
377 	dep = dwc->eps[0];
378 	dwc->ep0_usb_req.dep = dep;
379 	dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
380 	dwc->ep0_usb_req.request.buf = dwc->setup_buf;
381 	dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
382 
383 	return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
384 }
385 
dwc3_ep0_handle_feature(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl,int set)386 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
387 		struct usb_ctrlrequest *ctrl, int set)
388 {
389 	struct dwc3_ep		*dep;
390 	u32			recip;
391 	u32			wValue;
392 	u32			wIndex;
393 	u32			reg;
394 	int			ret;
395 	enum usb_device_state	state;
396 
397 	wValue = le16_to_cpu(ctrl->wValue);
398 	wIndex = le16_to_cpu(ctrl->wIndex);
399 	recip = ctrl->bRequestType & USB_RECIP_MASK;
400 	state = dwc->gadget.state;
401 
402 	switch (recip) {
403 	case USB_RECIP_DEVICE:
404 
405 		switch (wValue) {
406 		case USB_DEVICE_REMOTE_WAKEUP:
407 			break;
408 		/*
409 		 * 9.4.1 says only only for SS, in AddressState only for
410 		 * default control pipe
411 		 */
412 		case USB_DEVICE_U1_ENABLE:
413 			if (state != USB_STATE_CONFIGURED)
414 				return -EINVAL;
415 			if (dwc->speed != DWC3_DSTS_SUPERSPEED)
416 				return -EINVAL;
417 
418 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
419 			if (set)
420 				reg |= DWC3_DCTL_INITU1ENA;
421 			else
422 				reg &= ~DWC3_DCTL_INITU1ENA;
423 			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
424 			break;
425 
426 		case USB_DEVICE_U2_ENABLE:
427 			if (state != USB_STATE_CONFIGURED)
428 				return -EINVAL;
429 			if (dwc->speed != DWC3_DSTS_SUPERSPEED)
430 				return -EINVAL;
431 
432 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
433 			if (set)
434 				reg |= DWC3_DCTL_INITU2ENA;
435 			else
436 				reg &= ~DWC3_DCTL_INITU2ENA;
437 			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
438 			break;
439 
440 		case USB_DEVICE_LTM_ENABLE:
441 			return -EINVAL;
442 
443 		case USB_DEVICE_TEST_MODE:
444 			if ((wIndex & 0xff) != 0)
445 				return -EINVAL;
446 			if (!set)
447 				return -EINVAL;
448 
449 			dwc->test_mode_nr = wIndex >> 8;
450 			dwc->test_mode = true;
451 			break;
452 		default:
453 			return -EINVAL;
454 		}
455 		break;
456 
457 	case USB_RECIP_INTERFACE:
458 		switch (wValue) {
459 		case USB_INTRF_FUNC_SUSPEND:
460 			if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
461 				/* XXX enable Low power suspend */
462 				;
463 			if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
464 				/* XXX enable remote wakeup */
465 				;
466 			break;
467 		default:
468 			return -EINVAL;
469 		}
470 		break;
471 
472 	case USB_RECIP_ENDPOINT:
473 		switch (wValue) {
474 		case USB_ENDPOINT_HALT:
475 			dep = dwc3_wIndex_to_dep(dwc, wIndex);
476 			if (!dep)
477 				return -EINVAL;
478 			if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
479 				break;
480 			ret = __dwc3_gadget_ep_set_halt(dep, set, true);
481 			if (ret)
482 				return -EINVAL;
483 			break;
484 		default:
485 			return -EINVAL;
486 		}
487 		break;
488 
489 	default:
490 		return -EINVAL;
491 	}
492 
493 	return 0;
494 }
495 
dwc3_ep0_set_address(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)496 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
497 {
498 	enum usb_device_state state = dwc->gadget.state;
499 	u32 addr;
500 	u32 reg;
501 
502 	addr = le16_to_cpu(ctrl->wValue);
503 	if (addr > 127) {
504 		dev_dbg(dwc->dev, "invalid device address %d", addr);
505 		return -EINVAL;
506 	}
507 
508 	if (state == USB_STATE_CONFIGURED) {
509 		dev_dbg(dwc->dev, "trying to set address when configured");
510 		return -EINVAL;
511 	}
512 
513 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
514 	reg &= ~(DWC3_DCFG_DEVADDR_MASK);
515 	reg |= DWC3_DCFG_DEVADDR(addr);
516 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
517 
518 	if (addr)
519 		usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
520 	else
521 		usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
522 
523 	return 0;
524 }
525 
dwc3_ep0_delegate_req(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)526 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
527 {
528 	int ret;
529 
530 	spin_unlock(&dwc->lock);
531 	ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
532 	spin_lock(&dwc->lock);
533 	return ret;
534 }
535 
dwc3_ep0_set_config(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)536 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
537 {
538 	enum usb_device_state state = dwc->gadget.state;
539 	u32 cfg;
540 	int ret;
541 	u32 reg;
542 
543 	dwc->start_config_issued = false;
544 	cfg = le16_to_cpu(ctrl->wValue);
545 
546 	switch (state) {
547 	case USB_STATE_DEFAULT:
548 		return -EINVAL;
549 
550 	case USB_STATE_ADDRESS:
551 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
552 		/* if the cfg matches and the cfg is non zero */
553 		if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
554 
555 			/*
556 			 * only change state if set_config has already
557 			 * been processed. If gadget driver returns
558 			 * USB_GADGET_DELAYED_STATUS, we will wait
559 			 * to change the state on the next usb_ep_queue()
560 			 */
561 			if (ret == 0)
562 				usb_gadget_set_state(&dwc->gadget,
563 						USB_STATE_CONFIGURED);
564 
565 			/*
566 			 * Enable transition to U1/U2 state when
567 			 * nothing is pending from application.
568 			 */
569 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
570 			reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
571 			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
572 
573 			dwc->resize_fifos = true;
574 			dev_dbg(dwc->dev, "resize FIFOs flag SET");
575 		}
576 		break;
577 
578 	case USB_STATE_CONFIGURED:
579 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
580 		if (!cfg && !ret)
581 			usb_gadget_set_state(&dwc->gadget,
582 					USB_STATE_ADDRESS);
583 		break;
584 	default:
585 		ret = -EINVAL;
586 	}
587 	return ret;
588 }
589 
dwc3_ep0_set_sel_cmpl(struct usb_ep * ep,struct usb_request * req)590 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
591 {
592 	struct dwc3_ep	*dep = to_dwc3_ep(ep);
593 	struct dwc3	*dwc = dep->dwc;
594 
595 	u32		param = 0;
596 	u32		reg;
597 
598 	struct timing {
599 		u8	u1sel;
600 		u8	u1pel;
601 		u16	u2sel;
602 		u16	u2pel;
603 	} __packed timing;
604 
605 	int		ret;
606 
607 	memcpy(&timing, req->buf, sizeof(timing));
608 
609 	dwc->u1sel = timing.u1sel;
610 	dwc->u1pel = timing.u1pel;
611 	dwc->u2sel = le16_to_cpu(timing.u2sel);
612 	dwc->u2pel = le16_to_cpu(timing.u2pel);
613 
614 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
615 	if (reg & DWC3_DCTL_INITU2ENA)
616 		param = dwc->u2pel;
617 	if (reg & DWC3_DCTL_INITU1ENA)
618 		param = dwc->u1pel;
619 
620 	/*
621 	 * According to Synopsys Databook, if parameter is
622 	 * greater than 125, a value of zero should be
623 	 * programmed in the register.
624 	 */
625 	if (param > 125)
626 		param = 0;
627 
628 	/* now that we have the time, issue DGCMD Set Sel */
629 	ret = dwc3_send_gadget_generic_command(dwc,
630 			DWC3_DGCMD_SET_PERIODIC_PAR, param);
631 	WARN_ON(ret < 0);
632 }
633 
dwc3_ep0_set_sel(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)634 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
635 {
636 	struct dwc3_ep	*dep;
637 	enum usb_device_state state = dwc->gadget.state;
638 	u16		wLength;
639 
640 	if (state == USB_STATE_DEFAULT)
641 		return -EINVAL;
642 
643 	wLength = le16_to_cpu(ctrl->wLength);
644 
645 	if (wLength != 6) {
646 		dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
647 				wLength);
648 		return -EINVAL;
649 	}
650 
651 	/*
652 	 * To handle Set SEL we need to receive 6 bytes from Host. So let's
653 	 * queue a usb_request for 6 bytes.
654 	 *
655 	 * Remember, though, this controller can't handle non-wMaxPacketSize
656 	 * aligned transfers on the OUT direction, so we queue a request for
657 	 * wMaxPacketSize instead.
658 	 */
659 	dep = dwc->eps[0];
660 	dwc->ep0_usb_req.dep = dep;
661 	dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
662 	dwc->ep0_usb_req.request.buf = dwc->setup_buf;
663 	dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
664 
665 	return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
666 }
667 
dwc3_ep0_set_isoch_delay(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)668 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
669 {
670 	u16		wLength;
671 	u16		wValue;
672 	u16		wIndex;
673 
674 	wValue = le16_to_cpu(ctrl->wValue);
675 	wLength = le16_to_cpu(ctrl->wLength);
676 	wIndex = le16_to_cpu(ctrl->wIndex);
677 
678 	if (wIndex || wLength)
679 		return -EINVAL;
680 
681 	/*
682 	 * REVISIT It's unclear from Databook what to do with this
683 	 * value. For now, just cache it.
684 	 */
685 	dwc->isoch_delay = wValue;
686 
687 	return 0;
688 }
689 
dwc3_ep0_std_request(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)690 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
691 {
692 	int ret;
693 
694 	switch (ctrl->bRequest) {
695 	case USB_REQ_GET_STATUS:
696 		dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
697 		ret = dwc3_ep0_handle_status(dwc, ctrl);
698 		break;
699 	case USB_REQ_CLEAR_FEATURE:
700 		dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
701 		ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
702 		break;
703 	case USB_REQ_SET_FEATURE:
704 		dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
705 		ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
706 		break;
707 	case USB_REQ_SET_ADDRESS:
708 		dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
709 		ret = dwc3_ep0_set_address(dwc, ctrl);
710 		break;
711 	case USB_REQ_SET_CONFIGURATION:
712 		dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
713 		ret = dwc3_ep0_set_config(dwc, ctrl);
714 		break;
715 	case USB_REQ_SET_SEL:
716 		dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
717 		ret = dwc3_ep0_set_sel(dwc, ctrl);
718 		break;
719 	case USB_REQ_SET_ISOCH_DELAY:
720 		dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
721 		ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
722 		break;
723 	default:
724 		dev_vdbg(dwc->dev, "Forwarding to gadget driver");
725 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
726 		break;
727 	}
728 
729 	return ret;
730 }
731 
dwc3_ep0_inspect_setup(struct dwc3 * dwc,const struct dwc3_event_depevt * event)732 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
733 		const struct dwc3_event_depevt *event)
734 {
735 	struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
736 	int ret = -EINVAL;
737 	u32 len;
738 
739 	if (!dwc->gadget_driver)
740 		goto out;
741 
742 	len = le16_to_cpu(ctrl->wLength);
743 	if (!len) {
744 		dwc->three_stage_setup = false;
745 		dwc->ep0_expect_in = false;
746 		dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
747 	} else {
748 		dwc->three_stage_setup = true;
749 		dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
750 		dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
751 	}
752 
753 	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
754 		ret = dwc3_ep0_std_request(dwc, ctrl);
755 	else
756 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
757 
758 	if (ret == USB_GADGET_DELAYED_STATUS)
759 		dwc->delayed_status = true;
760 
761 out:
762 	if (ret < 0)
763 		dwc3_ep0_stall_and_restart(dwc);
764 }
765 
dwc3_ep0_complete_data(struct dwc3 * dwc,const struct dwc3_event_depevt * event)766 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
767 		const struct dwc3_event_depevt *event)
768 {
769 	struct dwc3_request	*r = NULL;
770 	struct usb_request	*ur;
771 	struct dwc3_trb		*trb;
772 	struct dwc3_ep		*ep0;
773 	unsigned		transfer_size = 0;
774 	unsigned		maxp;
775 	void			*buf;
776 	u32			transferred = 0;
777 	u32			status;
778 	u32			length;
779 	u8			epnum;
780 
781 	epnum = event->endpoint_number;
782 	ep0 = dwc->eps[0];
783 
784 	dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
785 
786 	trb = dwc->ep0_trb;
787 
788 	r = next_request(&ep0->request_list);
789 	if (!r)
790 		return;
791 
792 	dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
793 
794 	status = DWC3_TRB_SIZE_TRBSTS(trb->size);
795 	if (status == DWC3_TRBSTS_SETUP_PENDING) {
796 		dev_dbg(dwc->dev, "Setup Pending received");
797 
798 		if (r)
799 			dwc3_gadget_giveback(ep0, r, -ECONNRESET);
800 
801 		return;
802 	}
803 
804 	ur = &r->request;
805 	buf = ur->buf;
806 
807 	length = trb->size & DWC3_TRB_SIZE_MASK;
808 
809 	maxp = ep0->endpoint.maxpacket;
810 
811 	if (dwc->ep0_bounced) {
812 		/*
813 		 * Handle the first TRB before handling the bounce buffer if
814 		 * the request length is greater than the bounce buffer size.
815 		 */
816 		if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
817 			transfer_size = (ur->length / maxp) * maxp;
818 			transferred = transfer_size - length;
819 			buf = (u8 *)buf + transferred;
820 			ur->actual += transferred;
821 
822 			trb++;
823 			dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
824 			length = trb->size & DWC3_TRB_SIZE_MASK;
825 
826 			ep0->free_slot = 0;
827 		}
828 
829 		transfer_size = roundup((ur->length - transfer_size),
830 					maxp);
831 		transferred = min_t(u32, ur->length - transferred,
832 				    transfer_size - length);
833 		dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
834 		memcpy(buf, dwc->ep0_bounce, transferred);
835 	} else {
836 		transferred = ur->length - length;
837 	}
838 
839 	ur->actual += transferred;
840 
841 	if ((epnum & 1) && ur->actual < ur->length) {
842 		/* for some reason we did not get everything out */
843 
844 		dwc3_ep0_stall_and_restart(dwc);
845 	} else {
846 		dwc3_gadget_giveback(ep0, r, 0);
847 
848 		if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
849 				ur->length && ur->zero) {
850 			int ret;
851 
852 			dwc->ep0_next_event = DWC3_EP0_COMPLETE;
853 
854 			ret = dwc3_ep0_start_trans(dwc, epnum,
855 					dwc->ctrl_req_addr, 0,
856 					DWC3_TRBCTL_CONTROL_DATA, 0);
857 			WARN_ON(ret < 0);
858 		}
859 	}
860 }
861 
dwc3_ep0_complete_status(struct dwc3 * dwc,const struct dwc3_event_depevt * event)862 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
863 		const struct dwc3_event_depevt *event)
864 {
865 	struct dwc3_request	*r;
866 	struct dwc3_ep		*dep;
867 	struct dwc3_trb		*trb;
868 	u32			status;
869 
870 	dep = dwc->eps[0];
871 	trb = dwc->ep0_trb;
872 
873 	if (!list_empty(&dep->request_list)) {
874 		r = next_request(&dep->request_list);
875 
876 		dwc3_gadget_giveback(dep, r, 0);
877 	}
878 
879 	if (dwc->test_mode) {
880 		int ret;
881 
882 		ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
883 		if (ret < 0) {
884 			dev_dbg(dwc->dev, "Invalid Test #%d",
885 					dwc->test_mode_nr);
886 			dwc3_ep0_stall_and_restart(dwc);
887 			return;
888 		}
889 	}
890 
891 	status = DWC3_TRB_SIZE_TRBSTS(trb->size);
892 	if (status == DWC3_TRBSTS_SETUP_PENDING)
893 		dev_dbg(dwc->dev, "Setup Pending received");
894 
895 	dwc->ep0state = EP0_SETUP_PHASE;
896 	dwc3_ep0_out_start(dwc);
897 }
898 
dwc3_ep0_xfer_complete(struct dwc3 * dwc,const struct dwc3_event_depevt * event)899 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
900 			const struct dwc3_event_depevt *event)
901 {
902 	struct dwc3_ep		*dep = dwc->eps[event->endpoint_number];
903 
904 	dep->flags &= ~DWC3_EP_BUSY;
905 	dep->resource_index = 0;
906 	dwc->setup_packet_pending = false;
907 
908 	switch (dwc->ep0state) {
909 	case EP0_SETUP_PHASE:
910 		dev_vdbg(dwc->dev, "Setup Phase");
911 		dwc3_ep0_inspect_setup(dwc, event);
912 		break;
913 
914 	case EP0_DATA_PHASE:
915 		dev_vdbg(dwc->dev, "Data Phase");
916 		dwc3_ep0_complete_data(dwc, event);
917 		break;
918 
919 	case EP0_STATUS_PHASE:
920 		dev_vdbg(dwc->dev, "Status Phase");
921 		dwc3_ep0_complete_status(dwc, event);
922 		break;
923 	default:
924 		WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
925 	}
926 }
927 
__dwc3_ep0_do_control_data(struct dwc3 * dwc,struct dwc3_ep * dep,struct dwc3_request * req)928 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
929 		struct dwc3_ep *dep, struct dwc3_request *req)
930 {
931 	int			ret;
932 
933 	req->direction = !!dep->number;
934 
935 	if (req->request.length == 0) {
936 		ret = dwc3_ep0_start_trans(dwc, dep->number,
937 					   dwc->ctrl_req_addr, 0,
938 					   DWC3_TRBCTL_CONTROL_DATA, 0);
939 	} else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
940 			(dep->number == 0)) {
941 		u32	transfer_size = 0;
942 		u32	maxpacket;
943 
944 		ret = usb_gadget_map_request(&dwc->gadget, &req->request,
945 				dep->number);
946 		if (ret) {
947 			dev_dbg(dwc->dev, "failed to map request\n");
948 			return;
949 		}
950 
951 		maxpacket = dep->endpoint.maxpacket;
952 		if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
953 			transfer_size = (req->request.length / maxpacket) *
954 						maxpacket;
955 			ret = dwc3_ep0_start_trans(dwc, dep->number,
956 						   req->request.dma,
957 						   transfer_size,
958 						   DWC3_TRBCTL_CONTROL_DATA, 1);
959 		}
960 
961 		transfer_size = roundup((req->request.length - transfer_size),
962 					maxpacket);
963 
964 		dwc->ep0_bounced = true;
965 
966 		/*
967 		 * REVISIT in case request length is bigger than
968 		 * DWC3_EP0_BOUNCE_SIZE we will need two chained
969 		 * TRBs to handle the transfer.
970 		 */
971 		ret = dwc3_ep0_start_trans(dwc, dep->number,
972 					   dwc->ep0_bounce_addr, transfer_size,
973 					   DWC3_TRBCTL_CONTROL_DATA, 0);
974 	} else {
975 		ret = usb_gadget_map_request(&dwc->gadget, &req->request,
976 				dep->number);
977 		if (ret) {
978 			dev_dbg(dwc->dev, "failed to map request\n");
979 			return;
980 		}
981 
982 		ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
983 					   req->request.length,
984 					   DWC3_TRBCTL_CONTROL_DATA, 0);
985 	}
986 
987 	WARN_ON(ret < 0);
988 }
989 
dwc3_ep0_start_control_status(struct dwc3_ep * dep)990 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
991 {
992 	struct dwc3		*dwc = dep->dwc;
993 	u32			type;
994 
995 	type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
996 		: DWC3_TRBCTL_CONTROL_STATUS2;
997 
998 	return dwc3_ep0_start_trans(dwc, dep->number,
999 			dwc->ctrl_req_addr, 0, type, 0);
1000 }
1001 
__dwc3_ep0_do_control_status(struct dwc3 * dwc,struct dwc3_ep * dep)1002 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1003 {
1004 	if (dwc->resize_fifos) {
1005 		dev_dbg(dwc->dev, "Resizing FIFOs");
1006 		dwc3_gadget_resize_tx_fifos(dwc);
1007 		dwc->resize_fifos = 0;
1008 	}
1009 
1010 	WARN_ON(dwc3_ep0_start_control_status(dep));
1011 }
1012 
dwc3_ep0_do_control_status(struct dwc3 * dwc,const struct dwc3_event_depevt * event)1013 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1014 		const struct dwc3_event_depevt *event)
1015 {
1016 	struct dwc3_ep		*dep = dwc->eps[event->endpoint_number];
1017 
1018 	__dwc3_ep0_do_control_status(dwc, dep);
1019 }
1020 
dwc3_ep0_end_control_data(struct dwc3 * dwc,struct dwc3_ep * dep)1021 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1022 {
1023 	struct dwc3_gadget_ep_cmd_params params;
1024 	u32			cmd;
1025 	int			ret;
1026 
1027 	if (!dep->resource_index)
1028 		return;
1029 
1030 	cmd = DWC3_DEPCMD_ENDTRANSFER;
1031 	cmd |= DWC3_DEPCMD_CMDIOC;
1032 	cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1033 	memset(&params, 0, sizeof(params));
1034 	ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1035 	WARN_ON_ONCE(ret);
1036 	dep->resource_index = 0;
1037 }
1038 
dwc3_ep0_xfernotready(struct dwc3 * dwc,const struct dwc3_event_depevt * event)1039 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1040 		const struct dwc3_event_depevt *event)
1041 {
1042 	dwc->setup_packet_pending = true;
1043 
1044 	switch (event->status) {
1045 	case DEPEVT_STATUS_CONTROL_DATA:
1046 		dev_vdbg(dwc->dev, "Control Data");
1047 
1048 		/*
1049 		 * We already have a DATA transfer in the controller's cache,
1050 		 * if we receive a XferNotReady(DATA) we will ignore it, unless
1051 		 * it's for the wrong direction.
1052 		 *
1053 		 * In that case, we must issue END_TRANSFER command to the Data
1054 		 * Phase we already have started and issue SetStall on the
1055 		 * control endpoint.
1056 		 */
1057 		if (dwc->ep0_expect_in != event->endpoint_number) {
1058 			struct dwc3_ep	*dep = dwc->eps[dwc->ep0_expect_in];
1059 
1060 			dev_vdbg(dwc->dev, "Wrong direction for Data phase");
1061 			dwc3_ep0_end_control_data(dwc, dep);
1062 			dwc3_ep0_stall_and_restart(dwc);
1063 			return;
1064 		}
1065 
1066 		break;
1067 
1068 	case DEPEVT_STATUS_CONTROL_STATUS:
1069 		if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1070 			return;
1071 
1072 		dev_vdbg(dwc->dev, "Control Status");
1073 
1074 		dwc->ep0state = EP0_STATUS_PHASE;
1075 
1076 		if (dwc->delayed_status) {
1077 			WARN_ON_ONCE(event->endpoint_number != 1);
1078 			dev_vdbg(dwc->dev, "Delayed Status");
1079 			return;
1080 		}
1081 
1082 		dwc3_ep0_do_control_status(dwc, event);
1083 	}
1084 }
1085 
dwc3_ep0_interrupt(struct dwc3 * dwc,const struct dwc3_event_depevt * event)1086 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1087 		const struct dwc3_event_depevt *event)
1088 {
1089 	u8			epnum = event->endpoint_number;
1090 
1091 	dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
1092 			dwc3_ep_event_string(event->endpoint_event),
1093 			epnum >> 1, (epnum & 1) ? "in" : "out",
1094 			dwc3_ep0_state_string(dwc->ep0state));
1095 
1096 	switch (event->endpoint_event) {
1097 	case DWC3_DEPEVT_XFERCOMPLETE:
1098 		dwc3_ep0_xfer_complete(dwc, event);
1099 		break;
1100 
1101 	case DWC3_DEPEVT_XFERNOTREADY:
1102 		dwc3_ep0_xfernotready(dwc, event);
1103 		break;
1104 
1105 	case DWC3_DEPEVT_XFERINPROGRESS:
1106 	case DWC3_DEPEVT_RXTXFIFOEVT:
1107 	case DWC3_DEPEVT_STREAMEVT:
1108 	case DWC3_DEPEVT_EPCMDCMPLT:
1109 		break;
1110 	}
1111 }
1112