1 /* SPDX-License-Identifier: GPL-2.0 */
2 /**
3 * io.h - DesignWare USB3 DRD IO Header
4 *
5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/io.h) and ported
11 * to uboot.
12 *
13 * commit 2c4cbe6e5a : usb: dwc3: add tracepoints to aid debugging
14 *
15 */
16
17 #ifndef __DRIVERS_USB_DWC3_IO_H
18 #define __DRIVERS_USB_DWC3_IO_H
19
20 #include <asm/io.h>
21
22 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
dwc3_readl(void __iomem * base,u32 offset)23 static inline u32 dwc3_readl(void __iomem *base, u32 offset)
24 {
25 unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
26 u32 value;
27
28 /*
29 * We requested the mem region starting from the Globals address
30 * space, see dwc3_probe in core.c.
31 * However, the offsets are given starting from xHCI address space.
32 */
33 value = readl(base + offs);
34
35 return value;
36 }
37
dwc3_writel(void __iomem * base,u32 offset,u32 value)38 static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
39 {
40 unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
41
42 /*
43 * We requested the mem region starting from the Globals address
44 * space, see dwc3_probe in core.c.
45 * However, the offsets are given starting from xHCI address space.
46 */
47 writel(value, base + offs);
48 }
49
dwc3_flush_cache(uintptr_t addr,int length)50 static inline void dwc3_flush_cache(uintptr_t addr, int length)
51 {
52 flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
53 }
54 #endif /* __DRIVERS_USB_DWC3_IO_H */
55