1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014 Freescale Semiconductor
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <fsl_csu.h>
9 #include <asm/arch/ns_access.h>
10 #include <asm/arch/fsl_serdes.h>
11
set_devices_ns_access(unsigned long index,u16 val)12 void set_devices_ns_access(unsigned long index, u16 val)
13 {
14 u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
15 u32 *reg;
16 uint32_t tmp;
17
18 reg = base + index / 2;
19 tmp = in_be32(reg);
20 if (index % 2 == 0) {
21 tmp &= 0x0000ffff;
22 tmp |= val << 16;
23 } else {
24 tmp &= 0xffff0000;
25 tmp |= val;
26 }
27
28 out_be32(reg, tmp);
29 }
30
enable_devices_ns_access(struct csu_ns_dev * ns_dev,uint32_t num)31 static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
32 {
33 int i;
34
35 for (i = 0; i < num; i++)
36 set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
37 }
38
enable_layerscape_ns_access(void)39 void enable_layerscape_ns_access(void)
40 {
41 #ifdef CONFIG_ARM64
42 if (current_el() == 3)
43 #endif
44 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
45 }
46
set_pcie_ns_access(int pcie,u16 val)47 void set_pcie_ns_access(int pcie, u16 val)
48 {
49 switch (pcie) {
50 #ifdef CONFIG_PCIE1
51 case PCIE1:
52 set_devices_ns_access(CSU_CSLX_PCIE1, val);
53 set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
54 return;
55 #endif
56 #ifdef CONFIG_PCIE2
57 case PCIE2:
58 set_devices_ns_access(CSU_CSLX_PCIE2, val);
59 set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
60 return;
61 #endif
62 #ifdef CONFIG_PCIE3
63 case PCIE3:
64 set_devices_ns_access(CSU_CSLX_PCIE3, val);
65 set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
66 return;
67 #endif
68 default:
69 debug("The PCIE%d doesn't exist!\n", pcie);
70 return;
71 }
72 }
73