1 /*
2 * Overview:
3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
5 *
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
8 *
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
11 *
12 * Credits:
13 * David Woodhouse for adding multichip support
14 *
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
17 *
18 * TODO:
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <common.h>
32 #if CONFIG_IS_ENABLED(OF_CONTROL)
33 #include <fdtdec.h>
34 #endif
35 #include <malloc.h>
36 #include <watchdog.h>
37 #include <linux/err.h>
38 #include <linux/compat.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/rawnand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #ifdef CONFIG_MTD_PARTITIONS
44 #include <linux/mtd/partitions.h>
45 #endif
46 #include <asm/io.h>
47 #include <linux/errno.h>
48
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8 = {
51 .eccbytes = 3,
52 .eccpos = {0, 1, 2},
53 .oobfree = {
54 {.offset = 3,
55 .length = 2},
56 {.offset = 6,
57 .length = 2} }
58 };
59
60 static struct nand_ecclayout nand_oob_16 = {
61 .eccbytes = 6,
62 .eccpos = {0, 1, 2, 3, 6, 7},
63 .oobfree = {
64 {.offset = 8,
65 . length = 8} }
66 };
67
68 static struct nand_ecclayout nand_oob_64 = {
69 .eccbytes = 24,
70 .eccpos = {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
74 .oobfree = {
75 {.offset = 2,
76 .length = 38} }
77 };
78
79 static struct nand_ecclayout nand_oob_128 = {
80 .eccbytes = 48,
81 .eccpos = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
88 .oobfree = {
89 {.offset = 2,
90 .length = 78} }
91 };
92
93 static int nand_get_device(struct mtd_info *mtd, int new_state);
94
95 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
97
98 /*
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
101 */
102 DEFINE_LED_TRIGGER(nand_led_trigger);
103
check_offs_len(struct mtd_info * mtd,loff_t ofs,uint64_t len)104 static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
106 {
107 struct nand_chip *chip = mtd_to_nand(mtd);
108 int ret = 0;
109
110 /* Start address must align on block boundary */
111 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__);
113 ret = -EINVAL;
114 }
115
116 /* Length must align on block boundary */
117 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__);
119 ret = -EINVAL;
120 }
121
122 return ret;
123 }
124
125 /**
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
128 *
129 * Release chip lock and wake up anyone waiting on the device.
130 */
nand_release_device(struct mtd_info * mtd)131 static void nand_release_device(struct mtd_info *mtd)
132 {
133 struct nand_chip *chip = mtd_to_nand(mtd);
134
135 /* De-select the NAND device */
136 chip->select_chip(mtd, -1);
137 }
138
139 /**
140 * nand_read_byte - [DEFAULT] read one byte from the chip
141 * @mtd: MTD device structure
142 *
143 * Default read function for 8bit buswidth
144 */
nand_read_byte(struct mtd_info * mtd)145 uint8_t nand_read_byte(struct mtd_info *mtd)
146 {
147 struct nand_chip *chip = mtd_to_nand(mtd);
148 return readb(chip->IO_ADDR_R);
149 }
150
151 /**
152 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
153 * @mtd: MTD device structure
154 *
155 * Default read function for 16bit buswidth with endianness conversion.
156 *
157 */
nand_read_byte16(struct mtd_info * mtd)158 static uint8_t nand_read_byte16(struct mtd_info *mtd)
159 {
160 struct nand_chip *chip = mtd_to_nand(mtd);
161 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
162 }
163
164 /**
165 * nand_read_word - [DEFAULT] read one word from the chip
166 * @mtd: MTD device structure
167 *
168 * Default read function for 16bit buswidth without endianness conversion.
169 */
nand_read_word(struct mtd_info * mtd)170 static u16 nand_read_word(struct mtd_info *mtd)
171 {
172 struct nand_chip *chip = mtd_to_nand(mtd);
173 return readw(chip->IO_ADDR_R);
174 }
175
176 /**
177 * nand_select_chip - [DEFAULT] control CE line
178 * @mtd: MTD device structure
179 * @chipnr: chipnumber to select, -1 for deselect
180 *
181 * Default select function for 1 chip devices.
182 */
nand_select_chip(struct mtd_info * mtd,int chipnr)183 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
184 {
185 struct nand_chip *chip = mtd_to_nand(mtd);
186
187 switch (chipnr) {
188 case -1:
189 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
190 break;
191 case 0:
192 break;
193
194 default:
195 BUG();
196 }
197 }
198
199 /**
200 * nand_write_byte - [DEFAULT] write single byte to chip
201 * @mtd: MTD device structure
202 * @byte: value to write
203 *
204 * Default function to write a byte to I/O[7:0]
205 */
nand_write_byte(struct mtd_info * mtd,uint8_t byte)206 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
207 {
208 struct nand_chip *chip = mtd_to_nand(mtd);
209
210 chip->write_buf(mtd, &byte, 1);
211 }
212
213 /**
214 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
215 * @mtd: MTD device structure
216 * @byte: value to write
217 *
218 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
219 */
nand_write_byte16(struct mtd_info * mtd,uint8_t byte)220 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
221 {
222 struct nand_chip *chip = mtd_to_nand(mtd);
223 uint16_t word = byte;
224
225 /*
226 * It's not entirely clear what should happen to I/O[15:8] when writing
227 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
228 *
229 * When the host supports a 16-bit bus width, only data is
230 * transferred at the 16-bit width. All address and command line
231 * transfers shall use only the lower 8-bits of the data bus. During
232 * command transfers, the host may place any value on the upper
233 * 8-bits of the data bus. During address transfers, the host shall
234 * set the upper 8-bits of the data bus to 00h.
235 *
236 * One user of the write_byte callback is nand_onfi_set_features. The
237 * four parameters are specified to be written to I/O[7:0], but this is
238 * neither an address nor a command transfer. Let's assume a 0 on the
239 * upper I/O lines is OK.
240 */
241 chip->write_buf(mtd, (uint8_t *)&word, 2);
242 }
243
iowrite8_rep(void * addr,const uint8_t * buf,int len)244 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
245 {
246 int i;
247
248 for (i = 0; i < len; i++)
249 writeb(buf[i], addr);
250 }
ioread8_rep(void * addr,uint8_t * buf,int len)251 static void ioread8_rep(void *addr, uint8_t *buf, int len)
252 {
253 int i;
254
255 for (i = 0; i < len; i++)
256 buf[i] = readb(addr);
257 }
258
ioread16_rep(void * addr,void * buf,int len)259 static void ioread16_rep(void *addr, void *buf, int len)
260 {
261 int i;
262 u16 *p = (u16 *) buf;
263
264 for (i = 0; i < len; i++)
265 p[i] = readw(addr);
266 }
267
iowrite16_rep(void * addr,void * buf,int len)268 static void iowrite16_rep(void *addr, void *buf, int len)
269 {
270 int i;
271 u16 *p = (u16 *) buf;
272
273 for (i = 0; i < len; i++)
274 writew(p[i], addr);
275 }
276
277 /**
278 * nand_write_buf - [DEFAULT] write buffer to chip
279 * @mtd: MTD device structure
280 * @buf: data buffer
281 * @len: number of bytes to write
282 *
283 * Default write function for 8bit buswidth.
284 */
nand_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)285 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
286 {
287 struct nand_chip *chip = mtd_to_nand(mtd);
288
289 iowrite8_rep(chip->IO_ADDR_W, buf, len);
290 }
291
292 /**
293 * nand_read_buf - [DEFAULT] read chip data into buffer
294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
297 *
298 * Default read function for 8bit buswidth.
299 */
nand_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)300 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
301 {
302 struct nand_chip *chip = mtd_to_nand(mtd);
303
304 ioread8_rep(chip->IO_ADDR_R, buf, len);
305 }
306
307 /**
308 * nand_write_buf16 - [DEFAULT] write buffer to chip
309 * @mtd: MTD device structure
310 * @buf: data buffer
311 * @len: number of bytes to write
312 *
313 * Default write function for 16bit buswidth.
314 */
nand_write_buf16(struct mtd_info * mtd,const uint8_t * buf,int len)315 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
316 {
317 struct nand_chip *chip = mtd_to_nand(mtd);
318 u16 *p = (u16 *) buf;
319
320 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
321 }
322
323 /**
324 * nand_read_buf16 - [DEFAULT] read chip data into buffer
325 * @mtd: MTD device structure
326 * @buf: buffer to store date
327 * @len: number of bytes to read
328 *
329 * Default read function for 16bit buswidth.
330 */
nand_read_buf16(struct mtd_info * mtd,uint8_t * buf,int len)331 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
332 {
333 struct nand_chip *chip = mtd_to_nand(mtd);
334 u16 *p = (u16 *) buf;
335
336 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
337 }
338
339 /**
340 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
341 * @mtd: MTD device structure
342 * @ofs: offset from device start
343 *
344 * Check, if the block is bad.
345 */
nand_block_bad(struct mtd_info * mtd,loff_t ofs)346 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
347 {
348 int page, res = 0, i = 0;
349 struct nand_chip *chip = mtd_to_nand(mtd);
350 u16 bad;
351
352 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
353 ofs += mtd->erasesize - mtd->writesize;
354
355 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
356
357 do {
358 if (chip->options & NAND_BUSWIDTH_16) {
359 chip->cmdfunc(mtd, NAND_CMD_READOOB,
360 chip->badblockpos & 0xFE, page);
361 bad = cpu_to_le16(chip->read_word(mtd));
362 if (chip->badblockpos & 0x1)
363 bad >>= 8;
364 else
365 bad &= 0xFF;
366 } else {
367 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
368 page);
369 bad = chip->read_byte(mtd);
370 }
371
372 if (likely(chip->badblockbits == 8))
373 res = bad != 0xFF;
374 else
375 res = hweight8(bad) < chip->badblockbits;
376 ofs += mtd->writesize;
377 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
378 i++;
379 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
380
381 return res;
382 }
383
384 /**
385 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
386 * @mtd: MTD device structure
387 * @ofs: offset from device start
388 *
389 * This is the default implementation, which can be overridden by a hardware
390 * specific driver. It provides the details for writing a bad block marker to a
391 * block.
392 */
nand_default_block_markbad(struct mtd_info * mtd,loff_t ofs)393 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
394 {
395 struct nand_chip *chip = mtd_to_nand(mtd);
396 struct mtd_oob_ops ops;
397 uint8_t buf[2] = { 0, 0 };
398 int ret = 0, res, i = 0;
399
400 memset(&ops, 0, sizeof(ops));
401 ops.oobbuf = buf;
402 ops.ooboffs = chip->badblockpos;
403 if (chip->options & NAND_BUSWIDTH_16) {
404 ops.ooboffs &= ~0x01;
405 ops.len = ops.ooblen = 2;
406 } else {
407 ops.len = ops.ooblen = 1;
408 }
409 ops.mode = MTD_OPS_PLACE_OOB;
410
411 /* Write to first/last page(s) if necessary */
412 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
413 ofs += mtd->erasesize - mtd->writesize;
414 do {
415 res = nand_do_write_oob(mtd, ofs, &ops);
416 if (!ret)
417 ret = res;
418
419 i++;
420 ofs += mtd->writesize;
421 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
422
423 return ret;
424 }
425
426 /**
427 * nand_block_markbad_lowlevel - mark a block bad
428 * @mtd: MTD device structure
429 * @ofs: offset from device start
430 *
431 * This function performs the generic NAND bad block marking steps (i.e., bad
432 * block table(s) and/or marker(s)). We only allow the hardware driver to
433 * specify how to write bad block markers to OOB (chip->block_markbad).
434 *
435 * We try operations in the following order:
436 * (1) erase the affected block, to allow OOB marker to be written cleanly
437 * (2) write bad block marker to OOB area of affected block (unless flag
438 * NAND_BBT_NO_OOB_BBM is present)
439 * (3) update the BBT
440 * Note that we retain the first error encountered in (2) or (3), finish the
441 * procedures, and dump the error in the end.
442 */
nand_block_markbad_lowlevel(struct mtd_info * mtd,loff_t ofs)443 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
444 {
445 struct nand_chip *chip = mtd_to_nand(mtd);
446 int res, ret = 0;
447
448 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
449 struct erase_info einfo;
450
451 /* Attempt erase before marking OOB */
452 memset(&einfo, 0, sizeof(einfo));
453 einfo.mtd = mtd;
454 einfo.addr = ofs;
455 einfo.len = 1ULL << chip->phys_erase_shift;
456 nand_erase_nand(mtd, &einfo, 0);
457
458 /* Write bad block marker to OOB */
459 nand_get_device(mtd, FL_WRITING);
460 ret = chip->block_markbad(mtd, ofs);
461 nand_release_device(mtd);
462 }
463
464 /* Mark block bad in BBT */
465 if (chip->bbt) {
466 res = nand_markbad_bbt(mtd, ofs);
467 if (!ret)
468 ret = res;
469 }
470
471 if (!ret)
472 mtd->ecc_stats.badblocks++;
473
474 return ret;
475 }
476
477 /**
478 * nand_check_wp - [GENERIC] check if the chip is write protected
479 * @mtd: MTD device structure
480 *
481 * Check, if the device is write protected. The function expects, that the
482 * device is already selected.
483 */
nand_check_wp(struct mtd_info * mtd)484 static int nand_check_wp(struct mtd_info *mtd)
485 {
486 struct nand_chip *chip = mtd_to_nand(mtd);
487
488 /* Broken xD cards report WP despite being writable */
489 if (chip->options & NAND_BROKEN_XD)
490 return 0;
491
492 /* Check the WP bit */
493 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
494 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
495 }
496
497 /**
498 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
499 * @mtd: MTD device structure
500 * @ofs: offset from device start
501 *
502 * Check if the block is marked as reserved.
503 */
nand_block_isreserved(struct mtd_info * mtd,loff_t ofs)504 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
505 {
506 struct nand_chip *chip = mtd_to_nand(mtd);
507
508 if (!chip->bbt)
509 return 0;
510 /* Return info from the table */
511 return nand_isreserved_bbt(mtd, ofs);
512 }
513
514 /**
515 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
516 * @mtd: MTD device structure
517 * @ofs: offset from device start
518 * @allowbbt: 1, if its allowed to access the bbt area
519 *
520 * Check, if the block is bad. Either by reading the bad block table or
521 * calling of the scan function.
522 */
nand_block_checkbad(struct mtd_info * mtd,loff_t ofs,int allowbbt)523 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
524 {
525 struct nand_chip *chip = mtd_to_nand(mtd);
526
527 if (!(chip->options & NAND_SKIP_BBTSCAN) &&
528 !(chip->options & NAND_BBT_SCANNED)) {
529 chip->options |= NAND_BBT_SCANNED;
530 chip->scan_bbt(mtd);
531 }
532
533 if (!chip->bbt)
534 return chip->block_bad(mtd, ofs);
535
536 /* Return info from the table */
537 return nand_isbad_bbt(mtd, ofs, allowbbt);
538 }
539
540 /**
541 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
542 * @mtd: MTD device structure
543 *
544 * Wait for the ready pin after a command, and warn if a timeout occurs.
545 */
nand_wait_ready(struct mtd_info * mtd)546 void nand_wait_ready(struct mtd_info *mtd)
547 {
548 struct nand_chip *chip = mtd_to_nand(mtd);
549 u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
550 u32 time_start;
551
552 time_start = get_timer(0);
553 /* Wait until command is processed or timeout occurs */
554 while (get_timer(time_start) < timeo) {
555 if (chip->dev_ready)
556 if (chip->dev_ready(mtd))
557 break;
558 }
559
560 if (!chip->dev_ready(mtd))
561 pr_warn("timeout while waiting for chip to become ready\n");
562 }
563 EXPORT_SYMBOL_GPL(nand_wait_ready);
564
565 /**
566 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
567 * @mtd: MTD device structure
568 * @timeo: Timeout in ms
569 *
570 * Wait for status ready (i.e. command done) or timeout.
571 */
nand_wait_status_ready(struct mtd_info * mtd,unsigned long timeo)572 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
573 {
574 register struct nand_chip *chip = mtd_to_nand(mtd);
575 u32 time_start;
576
577 timeo = (CONFIG_SYS_HZ * timeo) / 1000;
578 time_start = get_timer(0);
579 while (get_timer(time_start) < timeo) {
580 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
581 break;
582 WATCHDOG_RESET();
583 }
584 };
585
586 /**
587 * nand_command - [DEFAULT] Send command to NAND device
588 * @mtd: MTD device structure
589 * @command: the command to be sent
590 * @column: the column address for this command, -1 if none
591 * @page_addr: the page address for this command, -1 if none
592 *
593 * Send command to NAND device. This function is used for small page devices
594 * (512 Bytes per page).
595 */
nand_command(struct mtd_info * mtd,unsigned int command,int column,int page_addr)596 static void nand_command(struct mtd_info *mtd, unsigned int command,
597 int column, int page_addr)
598 {
599 register struct nand_chip *chip = mtd_to_nand(mtd);
600 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
601
602 /* Write out the command to the device */
603 if (command == NAND_CMD_SEQIN) {
604 int readcmd;
605
606 if (column >= mtd->writesize) {
607 /* OOB area */
608 column -= mtd->writesize;
609 readcmd = NAND_CMD_READOOB;
610 } else if (column < 256) {
611 /* First 256 bytes --> READ0 */
612 readcmd = NAND_CMD_READ0;
613 } else {
614 column -= 256;
615 readcmd = NAND_CMD_READ1;
616 }
617 chip->cmd_ctrl(mtd, readcmd, ctrl);
618 ctrl &= ~NAND_CTRL_CHANGE;
619 }
620 chip->cmd_ctrl(mtd, command, ctrl);
621
622 /* Address cycle, when necessary */
623 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
624 /* Serially input address */
625 if (column != -1) {
626 /* Adjust columns for 16 bit buswidth */
627 if (chip->options & NAND_BUSWIDTH_16 &&
628 !nand_opcode_8bits(command))
629 column >>= 1;
630 chip->cmd_ctrl(mtd, column, ctrl);
631 ctrl &= ~NAND_CTRL_CHANGE;
632 }
633 if (page_addr != -1) {
634 chip->cmd_ctrl(mtd, page_addr, ctrl);
635 ctrl &= ~NAND_CTRL_CHANGE;
636 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
637 if (chip->options & NAND_ROW_ADDR_3)
638 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
639 }
640 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
641
642 /*
643 * Program and erase have their own busy handlers status and sequential
644 * in needs no delay
645 */
646 switch (command) {
647
648 case NAND_CMD_PAGEPROG:
649 case NAND_CMD_ERASE1:
650 case NAND_CMD_ERASE2:
651 case NAND_CMD_SEQIN:
652 case NAND_CMD_STATUS:
653 case NAND_CMD_READID:
654 case NAND_CMD_SET_FEATURES:
655 return;
656
657 case NAND_CMD_RESET:
658 if (chip->dev_ready)
659 break;
660 udelay(chip->chip_delay);
661 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
662 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
663 chip->cmd_ctrl(mtd,
664 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
665 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
666 nand_wait_status_ready(mtd, 250);
667 return;
668
669 /* This applies to read commands */
670 default:
671 /*
672 * If we don't have access to the busy pin, we apply the given
673 * command delay
674 */
675 if (!chip->dev_ready) {
676 udelay(chip->chip_delay);
677 return;
678 }
679 }
680 /*
681 * Apply this short delay always to ensure that we do wait tWB in
682 * any case on any machine.
683 */
684 ndelay(100);
685
686 nand_wait_ready(mtd);
687 }
688
689 /**
690 * nand_command_lp - [DEFAULT] Send command to NAND large page device
691 * @mtd: MTD device structure
692 * @command: the command to be sent
693 * @column: the column address for this command, -1 if none
694 * @page_addr: the page address for this command, -1 if none
695 *
696 * Send command to NAND device. This is the version for the new large page
697 * devices. We don't have the separate regions as we have in the small page
698 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
699 */
nand_command_lp(struct mtd_info * mtd,unsigned int command,int column,int page_addr)700 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
701 int column, int page_addr)
702 {
703 register struct nand_chip *chip = mtd_to_nand(mtd);
704
705 /* Emulate NAND_CMD_READOOB */
706 if (command == NAND_CMD_READOOB) {
707 column += mtd->writesize;
708 command = NAND_CMD_READ0;
709 }
710
711 /* Command latch cycle */
712 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
713
714 if (column != -1 || page_addr != -1) {
715 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
716
717 /* Serially input address */
718 if (column != -1) {
719 /* Adjust columns for 16 bit buswidth */
720 if (chip->options & NAND_BUSWIDTH_16 &&
721 !nand_opcode_8bits(command))
722 column >>= 1;
723 chip->cmd_ctrl(mtd, column, ctrl);
724 ctrl &= ~NAND_CTRL_CHANGE;
725 chip->cmd_ctrl(mtd, column >> 8, ctrl);
726 }
727 if (page_addr != -1) {
728 chip->cmd_ctrl(mtd, page_addr, ctrl);
729 chip->cmd_ctrl(mtd, page_addr >> 8,
730 NAND_NCE | NAND_ALE);
731 if (chip->options & NAND_ROW_ADDR_3)
732 chip->cmd_ctrl(mtd, page_addr >> 16,
733 NAND_NCE | NAND_ALE);
734 }
735 }
736 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
737
738 /*
739 * Program and erase have their own busy handlers status, sequential
740 * in and status need no delay.
741 */
742 switch (command) {
743
744 case NAND_CMD_CACHEDPROG:
745 case NAND_CMD_PAGEPROG:
746 case NAND_CMD_ERASE1:
747 case NAND_CMD_ERASE2:
748 case NAND_CMD_SEQIN:
749 case NAND_CMD_RNDIN:
750 case NAND_CMD_STATUS:
751 case NAND_CMD_READID:
752 case NAND_CMD_SET_FEATURES:
753 return;
754
755 case NAND_CMD_RESET:
756 if (chip->dev_ready)
757 break;
758 udelay(chip->chip_delay);
759 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
760 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
761 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
762 NAND_NCE | NAND_CTRL_CHANGE);
763 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
764 nand_wait_status_ready(mtd, 250);
765 return;
766
767 case NAND_CMD_RNDOUT:
768 /* No ready / busy check necessary */
769 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
770 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
771 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
772 NAND_NCE | NAND_CTRL_CHANGE);
773 return;
774
775 case NAND_CMD_READ0:
776 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
777 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
778 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
779 NAND_NCE | NAND_CTRL_CHANGE);
780
781 /* This applies to read commands */
782 default:
783 /*
784 * If we don't have access to the busy pin, we apply the given
785 * command delay.
786 */
787 if (!chip->dev_ready) {
788 udelay(chip->chip_delay);
789 return;
790 }
791 }
792
793 /*
794 * Apply this short delay always to ensure that we do wait tWB in
795 * any case on any machine.
796 */
797 ndelay(100);
798
799 nand_wait_ready(mtd);
800 }
801
802 /**
803 * panic_nand_get_device - [GENERIC] Get chip for selected access
804 * @chip: the nand chip descriptor
805 * @mtd: MTD device structure
806 * @new_state: the state which is requested
807 *
808 * Used when in panic, no locks are taken.
809 */
panic_nand_get_device(struct nand_chip * chip,struct mtd_info * mtd,int new_state)810 static void panic_nand_get_device(struct nand_chip *chip,
811 struct mtd_info *mtd, int new_state)
812 {
813 /* Hardware controller shared among independent devices */
814 chip->controller->active = chip;
815 chip->state = new_state;
816 }
817
818 /**
819 * nand_get_device - [GENERIC] Get chip for selected access
820 * @mtd: MTD device structure
821 * @new_state: the state which is requested
822 *
823 * Get the device and lock it for exclusive access
824 */
825 static int
nand_get_device(struct mtd_info * mtd,int new_state)826 nand_get_device(struct mtd_info *mtd, int new_state)
827 {
828 struct nand_chip *chip = mtd_to_nand(mtd);
829 chip->state = new_state;
830 return 0;
831 }
832
833 /**
834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
837 * @timeo: timeout
838 *
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
841 * an oops through mtdoops.
842 */
panic_nand_wait(struct mtd_info * mtd,struct nand_chip * chip,unsigned long timeo)843 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
844 unsigned long timeo)
845 {
846 int i;
847 for (i = 0; i < timeo; i++) {
848 if (chip->dev_ready) {
849 if (chip->dev_ready(mtd))
850 break;
851 } else {
852 if (chip->read_byte(mtd) & NAND_STATUS_READY)
853 break;
854 }
855 mdelay(1);
856 }
857 }
858
859 /**
860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
863 *
864 * Wait for command done. This applies to erase and program only.
865 */
nand_wait(struct mtd_info * mtd,struct nand_chip * chip)866 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
867 {
868 int status;
869 unsigned long timeo = 400;
870
871 led_trigger_event(nand_led_trigger, LED_FULL);
872
873 /*
874 * Apply this short delay always to ensure that we do wait tWB in any
875 * case on any machine.
876 */
877 ndelay(100);
878
879 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
880
881 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
882 u32 time_start;
883
884 time_start = get_timer(0);
885 while (get_timer(time_start) < timer) {
886 if (chip->dev_ready) {
887 if (chip->dev_ready(mtd))
888 break;
889 } else {
890 if (chip->read_byte(mtd) & NAND_STATUS_READY)
891 break;
892 }
893 }
894 led_trigger_event(nand_led_trigger, LED_OFF);
895
896 status = (int)chip->read_byte(mtd);
897 /* This can happen if in case of timeout or buggy dev_ready */
898 WARN_ON(!(status & NAND_STATUS_READY));
899 return status;
900 }
901
902 /**
903 * nand_reset_data_interface - Reset data interface and timings
904 * @chip: The NAND chip
905 * @chipnr: Internal die id
906 *
907 * Reset the Data interface and timings to ONFI mode 0.
908 *
909 * Returns 0 for success or negative error code otherwise.
910 */
nand_reset_data_interface(struct nand_chip * chip,int chipnr)911 static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
912 {
913 struct mtd_info *mtd = nand_to_mtd(chip);
914 const struct nand_data_interface *conf;
915 int ret;
916
917 if (!chip->setup_data_interface)
918 return 0;
919
920 /*
921 * The ONFI specification says:
922 * "
923 * To transition from NV-DDR or NV-DDR2 to the SDR data
924 * interface, the host shall use the Reset (FFh) command
925 * using SDR timing mode 0. A device in any timing mode is
926 * required to recognize Reset (FFh) command issued in SDR
927 * timing mode 0.
928 * "
929 *
930 * Configure the data interface in SDR mode and set the
931 * timings to timing mode 0.
932 */
933
934 conf = nand_get_default_data_interface();
935 ret = chip->setup_data_interface(mtd, chipnr, conf);
936 if (ret)
937 pr_err("Failed to configure data interface to SDR timing mode 0\n");
938
939 return ret;
940 }
941
942 /**
943 * nand_setup_data_interface - Setup the best data interface and timings
944 * @chip: The NAND chip
945 * @chipnr: Internal die id
946 *
947 * Find and configure the best data interface and NAND timings supported by
948 * the chip and the driver.
949 * First tries to retrieve supported timing modes from ONFI information,
950 * and if the NAND chip does not support ONFI, relies on the
951 * ->onfi_timing_mode_default specified in the nand_ids table.
952 *
953 * Returns 0 for success or negative error code otherwise.
954 */
nand_setup_data_interface(struct nand_chip * chip,int chipnr)955 static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
956 {
957 struct mtd_info *mtd = nand_to_mtd(chip);
958 int ret;
959
960 if (!chip->setup_data_interface || !chip->data_interface)
961 return 0;
962
963 /*
964 * Ensure the timing mode has been changed on the chip side
965 * before changing timings on the controller side.
966 */
967 if (chip->onfi_version) {
968 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
969 chip->onfi_timing_mode_default,
970 };
971
972 ret = chip->onfi_set_features(mtd, chip,
973 ONFI_FEATURE_ADDR_TIMING_MODE,
974 tmode_param);
975 if (ret)
976 goto err;
977 }
978
979 ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
980 err:
981 return ret;
982 }
983
984 /**
985 * nand_init_data_interface - find the best data interface and timings
986 * @chip: The NAND chip
987 *
988 * Find the best data interface and NAND timings supported by the chip
989 * and the driver.
990 * First tries to retrieve supported timing modes from ONFI information,
991 * and if the NAND chip does not support ONFI, relies on the
992 * ->onfi_timing_mode_default specified in the nand_ids table. After this
993 * function nand_chip->data_interface is initialized with the best timing mode
994 * available.
995 *
996 * Returns 0 for success or negative error code otherwise.
997 */
nand_init_data_interface(struct nand_chip * chip)998 static int nand_init_data_interface(struct nand_chip *chip)
999 {
1000 struct mtd_info *mtd = nand_to_mtd(chip);
1001 int modes, mode, ret;
1002
1003 if (!chip->setup_data_interface)
1004 return 0;
1005
1006 /*
1007 * First try to identify the best timings from ONFI parameters and
1008 * if the NAND does not support ONFI, fallback to the default ONFI
1009 * timing mode.
1010 */
1011 modes = onfi_get_async_timing_mode(chip);
1012 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1013 if (!chip->onfi_timing_mode_default)
1014 return 0;
1015
1016 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1017 }
1018
1019 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1020 GFP_KERNEL);
1021 if (!chip->data_interface)
1022 return -ENOMEM;
1023
1024 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1025 ret = onfi_init_data_interface(chip, chip->data_interface,
1026 NAND_SDR_IFACE, mode);
1027 if (ret)
1028 continue;
1029
1030 /* Pass -1 to only */
1031 ret = chip->setup_data_interface(mtd,
1032 NAND_DATA_IFACE_CHECK_ONLY,
1033 chip->data_interface);
1034 if (!ret) {
1035 chip->onfi_timing_mode_default = mode;
1036 break;
1037 }
1038 }
1039
1040 return 0;
1041 }
1042
nand_release_data_interface(struct nand_chip * chip)1043 static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
1044 {
1045 kfree(chip->data_interface);
1046 }
1047
1048 /**
1049 * nand_reset - Reset and initialize a NAND device
1050 * @chip: The NAND chip
1051 * @chipnr: Internal die id
1052 *
1053 * Returns 0 for success or negative error code otherwise
1054 */
nand_reset(struct nand_chip * chip,int chipnr)1055 int nand_reset(struct nand_chip *chip, int chipnr)
1056 {
1057 struct mtd_info *mtd = nand_to_mtd(chip);
1058 int ret;
1059
1060 ret = nand_reset_data_interface(chip, chipnr);
1061 if (ret)
1062 return ret;
1063
1064 /*
1065 * The CS line has to be released before we can apply the new NAND
1066 * interface settings, hence this weird ->select_chip() dance.
1067 */
1068 chip->select_chip(mtd, chipnr);
1069 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1070 chip->select_chip(mtd, -1);
1071
1072 chip->select_chip(mtd, chipnr);
1073 ret = nand_setup_data_interface(chip, chipnr);
1074 chip->select_chip(mtd, -1);
1075 if (ret)
1076 return ret;
1077
1078 return 0;
1079 }
1080
1081 /**
1082 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1083 * @buf: buffer to test
1084 * @len: buffer length
1085 * @bitflips_threshold: maximum number of bitflips
1086 *
1087 * Check if a buffer contains only 0xff, which means the underlying region
1088 * has been erased and is ready to be programmed.
1089 * The bitflips_threshold specify the maximum number of bitflips before
1090 * considering the region is not erased.
1091 * Note: The logic of this function has been extracted from the memweight
1092 * implementation, except that nand_check_erased_buf function exit before
1093 * testing the whole buffer if the number of bitflips exceed the
1094 * bitflips_threshold value.
1095 *
1096 * Returns a positive number of bitflips less than or equal to
1097 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1098 * threshold.
1099 */
nand_check_erased_buf(void * buf,int len,int bitflips_threshold)1100 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1101 {
1102 const unsigned char *bitmap = buf;
1103 int bitflips = 0;
1104 int weight;
1105
1106 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1107 len--, bitmap++) {
1108 weight = hweight8(*bitmap);
1109 bitflips += BITS_PER_BYTE - weight;
1110 if (unlikely(bitflips > bitflips_threshold))
1111 return -EBADMSG;
1112 }
1113
1114 for (; len >= 4; len -= 4, bitmap += 4) {
1115 weight = hweight32(*((u32 *)bitmap));
1116 bitflips += 32 - weight;
1117 if (unlikely(bitflips > bitflips_threshold))
1118 return -EBADMSG;
1119 }
1120
1121 for (; len > 0; len--, bitmap++) {
1122 weight = hweight8(*bitmap);
1123 bitflips += BITS_PER_BYTE - weight;
1124 if (unlikely(bitflips > bitflips_threshold))
1125 return -EBADMSG;
1126 }
1127
1128 return bitflips;
1129 }
1130
1131 /**
1132 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1133 * 0xff data
1134 * @data: data buffer to test
1135 * @datalen: data length
1136 * @ecc: ECC buffer
1137 * @ecclen: ECC length
1138 * @extraoob: extra OOB buffer
1139 * @extraooblen: extra OOB length
1140 * @bitflips_threshold: maximum number of bitflips
1141 *
1142 * Check if a data buffer and its associated ECC and OOB data contains only
1143 * 0xff pattern, which means the underlying region has been erased and is
1144 * ready to be programmed.
1145 * The bitflips_threshold specify the maximum number of bitflips before
1146 * considering the region as not erased.
1147 *
1148 * Note:
1149 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1150 * different from the NAND page size. When fixing bitflips, ECC engines will
1151 * report the number of errors per chunk, and the NAND core infrastructure
1152 * expect you to return the maximum number of bitflips for the whole page.
1153 * This is why you should always use this function on a single chunk and
1154 * not on the whole page. After checking each chunk you should update your
1155 * max_bitflips value accordingly.
1156 * 2/ When checking for bitflips in erased pages you should not only check
1157 * the payload data but also their associated ECC data, because a user might
1158 * have programmed almost all bits to 1 but a few. In this case, we
1159 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1160 * this case.
1161 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1162 * data are protected by the ECC engine.
1163 * It could also be used if you support subpages and want to attach some
1164 * extra OOB data to an ECC chunk.
1165 *
1166 * Returns a positive number of bitflips less than or equal to
1167 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1168 * threshold. In case of success, the passed buffers are filled with 0xff.
1169 */
nand_check_erased_ecc_chunk(void * data,int datalen,void * ecc,int ecclen,void * extraoob,int extraooblen,int bitflips_threshold)1170 int nand_check_erased_ecc_chunk(void *data, int datalen,
1171 void *ecc, int ecclen,
1172 void *extraoob, int extraooblen,
1173 int bitflips_threshold)
1174 {
1175 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1176
1177 data_bitflips = nand_check_erased_buf(data, datalen,
1178 bitflips_threshold);
1179 if (data_bitflips < 0)
1180 return data_bitflips;
1181
1182 bitflips_threshold -= data_bitflips;
1183
1184 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1185 if (ecc_bitflips < 0)
1186 return ecc_bitflips;
1187
1188 bitflips_threshold -= ecc_bitflips;
1189
1190 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1191 bitflips_threshold);
1192 if (extraoob_bitflips < 0)
1193 return extraoob_bitflips;
1194
1195 if (data_bitflips)
1196 memset(data, 0xff, datalen);
1197
1198 if (ecc_bitflips)
1199 memset(ecc, 0xff, ecclen);
1200
1201 if (extraoob_bitflips)
1202 memset(extraoob, 0xff, extraooblen);
1203
1204 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1205 }
1206 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1207
1208 /**
1209 * nand_read_page_raw - [INTERN] read raw page data without ecc
1210 * @mtd: mtd info structure
1211 * @chip: nand chip info structure
1212 * @buf: buffer to store read data
1213 * @oob_required: caller requires OOB data read to chip->oob_poi
1214 * @page: page number to read
1215 *
1216 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1217 */
nand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1218 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1219 uint8_t *buf, int oob_required, int page)
1220 {
1221 chip->read_buf(mtd, buf, mtd->writesize);
1222 if (oob_required)
1223 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1224 return 0;
1225 }
1226
1227 /**
1228 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1229 * @mtd: mtd info structure
1230 * @chip: nand chip info structure
1231 * @buf: buffer to store read data
1232 * @oob_required: caller requires OOB data read to chip->oob_poi
1233 * @page: page number to read
1234 *
1235 * We need a special oob layout and handling even when OOB isn't used.
1236 */
nand_read_page_raw_syndrome(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1237 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1238 struct nand_chip *chip, uint8_t *buf,
1239 int oob_required, int page)
1240 {
1241 int eccsize = chip->ecc.size;
1242 int eccbytes = chip->ecc.bytes;
1243 uint8_t *oob = chip->oob_poi;
1244 int steps, size;
1245
1246 for (steps = chip->ecc.steps; steps > 0; steps--) {
1247 chip->read_buf(mtd, buf, eccsize);
1248 buf += eccsize;
1249
1250 if (chip->ecc.prepad) {
1251 chip->read_buf(mtd, oob, chip->ecc.prepad);
1252 oob += chip->ecc.prepad;
1253 }
1254
1255 chip->read_buf(mtd, oob, eccbytes);
1256 oob += eccbytes;
1257
1258 if (chip->ecc.postpad) {
1259 chip->read_buf(mtd, oob, chip->ecc.postpad);
1260 oob += chip->ecc.postpad;
1261 }
1262 }
1263
1264 size = mtd->oobsize - (oob - chip->oob_poi);
1265 if (size)
1266 chip->read_buf(mtd, oob, size);
1267
1268 return 0;
1269 }
1270
1271 /**
1272 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1273 * @mtd: mtd info structure
1274 * @chip: nand chip info structure
1275 * @buf: buffer to store read data
1276 * @oob_required: caller requires OOB data read to chip->oob_poi
1277 * @page: page number to read
1278 */
nand_read_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1279 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1280 uint8_t *buf, int oob_required, int page)
1281 {
1282 int i, eccsize = chip->ecc.size;
1283 int eccbytes = chip->ecc.bytes;
1284 int eccsteps = chip->ecc.steps;
1285 uint8_t *p = buf;
1286 uint8_t *ecc_calc = chip->buffers->ecccalc;
1287 uint8_t *ecc_code = chip->buffers->ecccode;
1288 uint32_t *eccpos = chip->ecc.layout->eccpos;
1289 unsigned int max_bitflips = 0;
1290
1291 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1292
1293 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1294 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1295
1296 for (i = 0; i < chip->ecc.total; i++)
1297 ecc_code[i] = chip->oob_poi[eccpos[i]];
1298
1299 eccsteps = chip->ecc.steps;
1300 p = buf;
1301
1302 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1303 int stat;
1304
1305 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1306 if (stat < 0) {
1307 mtd->ecc_stats.failed++;
1308 } else {
1309 mtd->ecc_stats.corrected += stat;
1310 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1311 }
1312 }
1313 return max_bitflips;
1314 }
1315
1316 /**
1317 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1318 * @mtd: mtd info structure
1319 * @chip: nand chip info structure
1320 * @data_offs: offset of requested data within the page
1321 * @readlen: data length
1322 * @bufpoi: buffer to store read data
1323 * @page: page number to read
1324 */
nand_read_subpage(struct mtd_info * mtd,struct nand_chip * chip,uint32_t data_offs,uint32_t readlen,uint8_t * bufpoi,int page)1325 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1326 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1327 int page)
1328 {
1329 int start_step, end_step, num_steps;
1330 uint32_t *eccpos = chip->ecc.layout->eccpos;
1331 uint8_t *p;
1332 int data_col_addr, i, gaps = 0;
1333 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1334 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1335 int index;
1336 unsigned int max_bitflips = 0;
1337
1338 /* Column address within the page aligned to ECC size (256bytes) */
1339 start_step = data_offs / chip->ecc.size;
1340 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1341 num_steps = end_step - start_step + 1;
1342 index = start_step * chip->ecc.bytes;
1343
1344 /* Data size aligned to ECC ecc.size */
1345 datafrag_len = num_steps * chip->ecc.size;
1346 eccfrag_len = num_steps * chip->ecc.bytes;
1347
1348 data_col_addr = start_step * chip->ecc.size;
1349 /* If we read not a page aligned data */
1350 if (data_col_addr != 0)
1351 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1352
1353 p = bufpoi + data_col_addr;
1354 chip->read_buf(mtd, p, datafrag_len);
1355
1356 /* Calculate ECC */
1357 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1358 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1359
1360 /*
1361 * The performance is faster if we position offsets according to
1362 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1363 */
1364 for (i = 0; i < eccfrag_len - 1; i++) {
1365 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1366 gaps = 1;
1367 break;
1368 }
1369 }
1370 if (gaps) {
1371 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1372 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1373 } else {
1374 /*
1375 * Send the command to read the particular ECC bytes take care
1376 * about buswidth alignment in read_buf.
1377 */
1378 aligned_pos = eccpos[index] & ~(busw - 1);
1379 aligned_len = eccfrag_len;
1380 if (eccpos[index] & (busw - 1))
1381 aligned_len++;
1382 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1383 aligned_len++;
1384
1385 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1386 mtd->writesize + aligned_pos, -1);
1387 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1388 }
1389
1390 for (i = 0; i < eccfrag_len; i++)
1391 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1392
1393 p = bufpoi + data_col_addr;
1394 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1395 int stat;
1396
1397 stat = chip->ecc.correct(mtd, p,
1398 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1399 if (stat == -EBADMSG &&
1400 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1401 /* check for empty pages with bitflips */
1402 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1403 &chip->buffers->ecccode[i],
1404 chip->ecc.bytes,
1405 NULL, 0,
1406 chip->ecc.strength);
1407 }
1408
1409 if (stat < 0) {
1410 mtd->ecc_stats.failed++;
1411 } else {
1412 mtd->ecc_stats.corrected += stat;
1413 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1414 }
1415 }
1416 return max_bitflips;
1417 }
1418
1419 /**
1420 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1421 * @mtd: mtd info structure
1422 * @chip: nand chip info structure
1423 * @buf: buffer to store read data
1424 * @oob_required: caller requires OOB data read to chip->oob_poi
1425 * @page: page number to read
1426 *
1427 * Not for syndrome calculating ECC controllers which need a special oob layout.
1428 */
nand_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1429 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1430 uint8_t *buf, int oob_required, int page)
1431 {
1432 int i, eccsize = chip->ecc.size;
1433 int eccbytes = chip->ecc.bytes;
1434 int eccsteps = chip->ecc.steps;
1435 uint8_t *p = buf;
1436 uint8_t *ecc_calc = chip->buffers->ecccalc;
1437 uint8_t *ecc_code = chip->buffers->ecccode;
1438 uint32_t *eccpos = chip->ecc.layout->eccpos;
1439 unsigned int max_bitflips = 0;
1440
1441 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1442 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1443 chip->read_buf(mtd, p, eccsize);
1444 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1445 }
1446 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1447
1448 for (i = 0; i < chip->ecc.total; i++)
1449 ecc_code[i] = chip->oob_poi[eccpos[i]];
1450
1451 eccsteps = chip->ecc.steps;
1452 p = buf;
1453
1454 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1455 int stat;
1456
1457 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1458 if (stat == -EBADMSG &&
1459 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1460 /* check for empty pages with bitflips */
1461 stat = nand_check_erased_ecc_chunk(p, eccsize,
1462 &ecc_code[i], eccbytes,
1463 NULL, 0,
1464 chip->ecc.strength);
1465 }
1466
1467 if (stat < 0) {
1468 mtd->ecc_stats.failed++;
1469 } else {
1470 mtd->ecc_stats.corrected += stat;
1471 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1472 }
1473 }
1474 return max_bitflips;
1475 }
1476
1477 /**
1478 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1479 * @mtd: mtd info structure
1480 * @chip: nand chip info structure
1481 * @buf: buffer to store read data
1482 * @oob_required: caller requires OOB data read to chip->oob_poi
1483 * @page: page number to read
1484 *
1485 * Hardware ECC for large page chips, require OOB to be read first. For this
1486 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1487 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1488 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1489 * the data area, by overwriting the NAND manufacturer bad block markings.
1490 */
nand_read_page_hwecc_oob_first(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1491 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1492 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1493 {
1494 int i, eccsize = chip->ecc.size;
1495 int eccbytes = chip->ecc.bytes;
1496 int eccsteps = chip->ecc.steps;
1497 uint8_t *p = buf;
1498 uint8_t *ecc_code = chip->buffers->ecccode;
1499 uint32_t *eccpos = chip->ecc.layout->eccpos;
1500 uint8_t *ecc_calc = chip->buffers->ecccalc;
1501 unsigned int max_bitflips = 0;
1502
1503 /* Read the OOB area first */
1504 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1505 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1506 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1507
1508 for (i = 0; i < chip->ecc.total; i++)
1509 ecc_code[i] = chip->oob_poi[eccpos[i]];
1510
1511 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1512 int stat;
1513
1514 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1515 chip->read_buf(mtd, p, eccsize);
1516 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1517
1518 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1519 if (stat == -EBADMSG &&
1520 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1521 /* check for empty pages with bitflips */
1522 stat = nand_check_erased_ecc_chunk(p, eccsize,
1523 &ecc_code[i], eccbytes,
1524 NULL, 0,
1525 chip->ecc.strength);
1526 }
1527
1528 if (stat < 0) {
1529 mtd->ecc_stats.failed++;
1530 } else {
1531 mtd->ecc_stats.corrected += stat;
1532 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1533 }
1534 }
1535 return max_bitflips;
1536 }
1537
1538 /**
1539 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1540 * @mtd: mtd info structure
1541 * @chip: nand chip info structure
1542 * @buf: buffer to store read data
1543 * @oob_required: caller requires OOB data read to chip->oob_poi
1544 * @page: page number to read
1545 *
1546 * The hw generator calculates the error syndrome automatically. Therefore we
1547 * need a special oob layout and handling.
1548 */
nand_read_page_syndrome(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1549 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1550 uint8_t *buf, int oob_required, int page)
1551 {
1552 int i, eccsize = chip->ecc.size;
1553 int eccbytes = chip->ecc.bytes;
1554 int eccsteps = chip->ecc.steps;
1555 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
1556 uint8_t *p = buf;
1557 uint8_t *oob = chip->oob_poi;
1558 unsigned int max_bitflips = 0;
1559
1560 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1561 int stat;
1562
1563 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1564 chip->read_buf(mtd, p, eccsize);
1565
1566 if (chip->ecc.prepad) {
1567 chip->read_buf(mtd, oob, chip->ecc.prepad);
1568 oob += chip->ecc.prepad;
1569 }
1570
1571 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1572 chip->read_buf(mtd, oob, eccbytes);
1573 stat = chip->ecc.correct(mtd, p, oob, NULL);
1574
1575 oob += eccbytes;
1576
1577 if (chip->ecc.postpad) {
1578 chip->read_buf(mtd, oob, chip->ecc.postpad);
1579 oob += chip->ecc.postpad;
1580 }
1581
1582 if (stat == -EBADMSG &&
1583 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1584 /* check for empty pages with bitflips */
1585 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1586 oob - eccpadbytes,
1587 eccpadbytes,
1588 NULL, 0,
1589 chip->ecc.strength);
1590 }
1591
1592 if (stat < 0) {
1593 mtd->ecc_stats.failed++;
1594 } else {
1595 mtd->ecc_stats.corrected += stat;
1596 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1597 }
1598 }
1599
1600 /* Calculate remaining oob bytes */
1601 i = mtd->oobsize - (oob - chip->oob_poi);
1602 if (i)
1603 chip->read_buf(mtd, oob, i);
1604
1605 return max_bitflips;
1606 }
1607
1608 /**
1609 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1610 * @chip: nand chip structure
1611 * @oob: oob destination address
1612 * @ops: oob ops structure
1613 * @len: size of oob to transfer
1614 */
nand_transfer_oob(struct nand_chip * chip,uint8_t * oob,struct mtd_oob_ops * ops,size_t len)1615 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1616 struct mtd_oob_ops *ops, size_t len)
1617 {
1618 switch (ops->mode) {
1619
1620 case MTD_OPS_PLACE_OOB:
1621 case MTD_OPS_RAW:
1622 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1623 return oob + len;
1624
1625 case MTD_OPS_AUTO_OOB: {
1626 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1627 uint32_t boffs = 0, roffs = ops->ooboffs;
1628 size_t bytes = 0;
1629
1630 for (; free->length && len; free++, len -= bytes) {
1631 /* Read request not from offset 0? */
1632 if (unlikely(roffs)) {
1633 if (roffs >= free->length) {
1634 roffs -= free->length;
1635 continue;
1636 }
1637 boffs = free->offset + roffs;
1638 bytes = min_t(size_t, len,
1639 (free->length - roffs));
1640 roffs = 0;
1641 } else {
1642 bytes = min_t(size_t, len, free->length);
1643 boffs = free->offset;
1644 }
1645 memcpy(oob, chip->oob_poi + boffs, bytes);
1646 oob += bytes;
1647 }
1648 return oob;
1649 }
1650 default:
1651 BUG();
1652 }
1653 return NULL;
1654 }
1655
1656 /**
1657 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1658 * @mtd: MTD device structure
1659 * @retry_mode: the retry mode to use
1660 *
1661 * Some vendors supply a special command to shift the Vt threshold, to be used
1662 * when there are too many bitflips in a page (i.e., ECC error). After setting
1663 * a new threshold, the host should retry reading the page.
1664 */
nand_setup_read_retry(struct mtd_info * mtd,int retry_mode)1665 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1666 {
1667 struct nand_chip *chip = mtd_to_nand(mtd);
1668
1669 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1670
1671 if (retry_mode >= chip->read_retries)
1672 return -EINVAL;
1673
1674 if (!chip->setup_read_retry)
1675 return -EOPNOTSUPP;
1676
1677 return chip->setup_read_retry(mtd, retry_mode);
1678 }
1679
1680 /**
1681 * nand_do_read_ops - [INTERN] Read data with ECC
1682 * @mtd: MTD device structure
1683 * @from: offset to read from
1684 * @ops: oob ops structure
1685 *
1686 * Internal function. Called with chip held.
1687 */
nand_do_read_ops(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)1688 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1689 struct mtd_oob_ops *ops)
1690 {
1691 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1692 struct nand_chip *chip = mtd_to_nand(mtd);
1693 int ret = 0;
1694 uint32_t readlen = ops->len;
1695 uint32_t oobreadlen = ops->ooblen;
1696 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
1697
1698 uint8_t *bufpoi, *oob, *buf;
1699 int use_bufpoi;
1700 unsigned int max_bitflips = 0;
1701 int retry_mode = 0;
1702 bool ecc_fail = false;
1703
1704 chipnr = (int)(from >> chip->chip_shift);
1705 chip->select_chip(mtd, chipnr);
1706
1707 realpage = (int)(from >> chip->page_shift);
1708 page = realpage & chip->pagemask;
1709
1710 col = (int)(from & (mtd->writesize - 1));
1711
1712 buf = ops->datbuf;
1713 oob = ops->oobbuf;
1714 oob_required = oob ? 1 : 0;
1715
1716 while (1) {
1717 unsigned int ecc_failures = mtd->ecc_stats.failed;
1718
1719 WATCHDOG_RESET();
1720 bytes = min(mtd->writesize - col, readlen);
1721 aligned = (bytes == mtd->writesize);
1722
1723 if (!aligned)
1724 use_bufpoi = 1;
1725 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1726 use_bufpoi = !IS_ALIGNED((unsigned long)buf,
1727 chip->buf_align);
1728 else
1729 use_bufpoi = 0;
1730
1731 /* Is the current page in the buffer? */
1732 if (realpage != chip->pagebuf || oob) {
1733 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1734
1735 if (use_bufpoi && aligned)
1736 pr_debug("%s: using read bounce buffer for buf@%p\n",
1737 __func__, buf);
1738
1739 read_retry:
1740 if (nand_standard_page_accessors(&chip->ecc))
1741 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1742
1743 /*
1744 * Now read the page into the buffer. Absent an error,
1745 * the read methods return max bitflips per ecc step.
1746 */
1747 if (unlikely(ops->mode == MTD_OPS_RAW))
1748 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1749 oob_required,
1750 page);
1751 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1752 !oob)
1753 ret = chip->ecc.read_subpage(mtd, chip,
1754 col, bytes, bufpoi,
1755 page);
1756 else
1757 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1758 oob_required, page);
1759 if (ret < 0) {
1760 if (use_bufpoi)
1761 /* Invalidate page cache */
1762 chip->pagebuf = -1;
1763 break;
1764 }
1765
1766 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1767
1768 /* Transfer not aligned data */
1769 if (use_bufpoi) {
1770 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1771 !(mtd->ecc_stats.failed - ecc_failures) &&
1772 (ops->mode != MTD_OPS_RAW)) {
1773 chip->pagebuf = realpage;
1774 chip->pagebuf_bitflips = ret;
1775 } else {
1776 /* Invalidate page cache */
1777 chip->pagebuf = -1;
1778 }
1779 memcpy(buf, chip->buffers->databuf + col, bytes);
1780 }
1781
1782 if (unlikely(oob)) {
1783 int toread = min(oobreadlen, max_oobsize);
1784
1785 if (toread) {
1786 oob = nand_transfer_oob(chip,
1787 oob, ops, toread);
1788 oobreadlen -= toread;
1789 }
1790 }
1791
1792 if (chip->options & NAND_NEED_READRDY) {
1793 /* Apply delay or wait for ready/busy pin */
1794 if (!chip->dev_ready)
1795 udelay(chip->chip_delay);
1796 else
1797 nand_wait_ready(mtd);
1798 }
1799
1800 if (mtd->ecc_stats.failed - ecc_failures) {
1801 if (retry_mode + 1 < chip->read_retries) {
1802 retry_mode++;
1803 ret = nand_setup_read_retry(mtd,
1804 retry_mode);
1805 if (ret < 0)
1806 break;
1807
1808 /* Reset failures; retry */
1809 mtd->ecc_stats.failed = ecc_failures;
1810 goto read_retry;
1811 } else {
1812 /* No more retry modes; real failure */
1813 ecc_fail = true;
1814 }
1815 }
1816
1817 buf += bytes;
1818 } else {
1819 memcpy(buf, chip->buffers->databuf + col, bytes);
1820 buf += bytes;
1821 max_bitflips = max_t(unsigned int, max_bitflips,
1822 chip->pagebuf_bitflips);
1823 }
1824
1825 readlen -= bytes;
1826
1827 /* Reset to retry mode 0 */
1828 if (retry_mode) {
1829 ret = nand_setup_read_retry(mtd, 0);
1830 if (ret < 0)
1831 break;
1832 retry_mode = 0;
1833 }
1834
1835 if (!readlen)
1836 break;
1837
1838 /* For subsequent reads align to page boundary */
1839 col = 0;
1840 /* Increment page address */
1841 realpage++;
1842
1843 page = realpage & chip->pagemask;
1844 /* Check, if we cross a chip boundary */
1845 if (!page) {
1846 chipnr++;
1847 chip->select_chip(mtd, -1);
1848 chip->select_chip(mtd, chipnr);
1849 }
1850 }
1851 chip->select_chip(mtd, -1);
1852
1853 ops->retlen = ops->len - (size_t) readlen;
1854 if (oob)
1855 ops->oobretlen = ops->ooblen - oobreadlen;
1856
1857 if (ret < 0)
1858 return ret;
1859
1860 if (ecc_fail)
1861 return -EBADMSG;
1862
1863 return max_bitflips;
1864 }
1865
1866 /**
1867 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1868 * @mtd: MTD device structure
1869 * @from: offset to read from
1870 * @len: number of bytes to read
1871 * @retlen: pointer to variable to store the number of read bytes
1872 * @buf: the databuffer to put data
1873 *
1874 * Get hold of the chip and call nand_do_read.
1875 */
nand_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,uint8_t * buf)1876 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1877 size_t *retlen, uint8_t *buf)
1878 {
1879 struct mtd_oob_ops ops;
1880 int ret;
1881
1882 nand_get_device(mtd, FL_READING);
1883 memset(&ops, 0, sizeof(ops));
1884 ops.len = len;
1885 ops.datbuf = buf;
1886 ops.mode = MTD_OPS_PLACE_OOB;
1887 ret = nand_do_read_ops(mtd, from, &ops);
1888 *retlen = ops.retlen;
1889 nand_release_device(mtd);
1890 return ret;
1891 }
1892
1893 /**
1894 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1895 * @mtd: mtd info structure
1896 * @chip: nand chip info structure
1897 * @page: page number to read
1898 */
nand_read_oob_std(struct mtd_info * mtd,struct nand_chip * chip,int page)1899 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1900 int page)
1901 {
1902 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1903 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1904 return 0;
1905 }
1906
1907 /**
1908 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1909 * with syndromes
1910 * @mtd: mtd info structure
1911 * @chip: nand chip info structure
1912 * @page: page number to read
1913 */
nand_read_oob_syndrome(struct mtd_info * mtd,struct nand_chip * chip,int page)1914 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1915 int page)
1916 {
1917 int length = mtd->oobsize;
1918 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1919 int eccsize = chip->ecc.size;
1920 uint8_t *bufpoi = chip->oob_poi;
1921 int i, toread, sndrnd = 0, pos;
1922
1923 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1924 for (i = 0; i < chip->ecc.steps; i++) {
1925 if (sndrnd) {
1926 pos = eccsize + i * (eccsize + chunk);
1927 if (mtd->writesize > 512)
1928 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1929 else
1930 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1931 } else
1932 sndrnd = 1;
1933 toread = min_t(int, length, chunk);
1934 chip->read_buf(mtd, bufpoi, toread);
1935 bufpoi += toread;
1936 length -= toread;
1937 }
1938 if (length > 0)
1939 chip->read_buf(mtd, bufpoi, length);
1940
1941 return 0;
1942 }
1943
1944 /**
1945 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1946 * @mtd: mtd info structure
1947 * @chip: nand chip info structure
1948 * @page: page number to write
1949 */
nand_write_oob_std(struct mtd_info * mtd,struct nand_chip * chip,int page)1950 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1951 int page)
1952 {
1953 int status = 0;
1954 const uint8_t *buf = chip->oob_poi;
1955 int length = mtd->oobsize;
1956
1957 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1958 chip->write_buf(mtd, buf, length);
1959 /* Send command to program the OOB data */
1960 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1961
1962 status = chip->waitfunc(mtd, chip);
1963
1964 return status & NAND_STATUS_FAIL ? -EIO : 0;
1965 }
1966
1967 /**
1968 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1969 * with syndrome - only for large page flash
1970 * @mtd: mtd info structure
1971 * @chip: nand chip info structure
1972 * @page: page number to write
1973 */
nand_write_oob_syndrome(struct mtd_info * mtd,struct nand_chip * chip,int page)1974 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1975 struct nand_chip *chip, int page)
1976 {
1977 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1978 int eccsize = chip->ecc.size, length = mtd->oobsize;
1979 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1980 const uint8_t *bufpoi = chip->oob_poi;
1981
1982 /*
1983 * data-ecc-data-ecc ... ecc-oob
1984 * or
1985 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1986 */
1987 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1988 pos = steps * (eccsize + chunk);
1989 steps = 0;
1990 } else
1991 pos = eccsize;
1992
1993 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1994 for (i = 0; i < steps; i++) {
1995 if (sndcmd) {
1996 if (mtd->writesize <= 512) {
1997 uint32_t fill = 0xFFFFFFFF;
1998
1999 len = eccsize;
2000 while (len > 0) {
2001 int num = min_t(int, len, 4);
2002 chip->write_buf(mtd, (uint8_t *)&fill,
2003 num);
2004 len -= num;
2005 }
2006 } else {
2007 pos = eccsize + i * (eccsize + chunk);
2008 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2009 }
2010 } else
2011 sndcmd = 1;
2012 len = min_t(int, length, chunk);
2013 chip->write_buf(mtd, bufpoi, len);
2014 bufpoi += len;
2015 length -= len;
2016 }
2017 if (length > 0)
2018 chip->write_buf(mtd, bufpoi, length);
2019
2020 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2021 status = chip->waitfunc(mtd, chip);
2022
2023 return status & NAND_STATUS_FAIL ? -EIO : 0;
2024 }
2025
2026 /**
2027 * nand_do_read_oob - [INTERN] NAND read out-of-band
2028 * @mtd: MTD device structure
2029 * @from: offset to read from
2030 * @ops: oob operations description structure
2031 *
2032 * NAND read out-of-band data from the spare area.
2033 */
nand_do_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)2034 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2035 struct mtd_oob_ops *ops)
2036 {
2037 int page, realpage, chipnr;
2038 struct nand_chip *chip = mtd_to_nand(mtd);
2039 struct mtd_ecc_stats stats;
2040 int readlen = ops->ooblen;
2041 int len;
2042 uint8_t *buf = ops->oobbuf;
2043 int ret = 0;
2044
2045 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2046 __func__, (unsigned long long)from, readlen);
2047
2048 stats = mtd->ecc_stats;
2049
2050 len = mtd_oobavail(mtd, ops);
2051
2052 if (unlikely(ops->ooboffs >= len)) {
2053 pr_debug("%s: attempt to start read outside oob\n",
2054 __func__);
2055 return -EINVAL;
2056 }
2057
2058 /* Do not allow reads past end of device */
2059 if (unlikely(from >= mtd->size ||
2060 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2061 (from >> chip->page_shift)) * len)) {
2062 pr_debug("%s: attempt to read beyond end of device\n",
2063 __func__);
2064 return -EINVAL;
2065 }
2066
2067 chipnr = (int)(from >> chip->chip_shift);
2068 chip->select_chip(mtd, chipnr);
2069
2070 /* Shift to get page */
2071 realpage = (int)(from >> chip->page_shift);
2072 page = realpage & chip->pagemask;
2073
2074 while (1) {
2075 WATCHDOG_RESET();
2076
2077 if (ops->mode == MTD_OPS_RAW)
2078 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2079 else
2080 ret = chip->ecc.read_oob(mtd, chip, page);
2081
2082 if (ret < 0)
2083 break;
2084
2085 len = min(len, readlen);
2086 buf = nand_transfer_oob(chip, buf, ops, len);
2087
2088 if (chip->options & NAND_NEED_READRDY) {
2089 /* Apply delay or wait for ready/busy pin */
2090 if (!chip->dev_ready)
2091 udelay(chip->chip_delay);
2092 else
2093 nand_wait_ready(mtd);
2094 }
2095
2096 readlen -= len;
2097 if (!readlen)
2098 break;
2099
2100 /* Increment page address */
2101 realpage++;
2102
2103 page = realpage & chip->pagemask;
2104 /* Check, if we cross a chip boundary */
2105 if (!page) {
2106 chipnr++;
2107 chip->select_chip(mtd, -1);
2108 chip->select_chip(mtd, chipnr);
2109 }
2110 }
2111 chip->select_chip(mtd, -1);
2112
2113 ops->oobretlen = ops->ooblen - readlen;
2114
2115 if (ret < 0)
2116 return ret;
2117
2118 if (mtd->ecc_stats.failed - stats.failed)
2119 return -EBADMSG;
2120
2121 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2122 }
2123
2124 /**
2125 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2126 * @mtd: MTD device structure
2127 * @from: offset to read from
2128 * @ops: oob operation description structure
2129 *
2130 * NAND read data and/or out-of-band data.
2131 */
nand_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)2132 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2133 struct mtd_oob_ops *ops)
2134 {
2135 int ret = -ENOTSUPP;
2136
2137 ops->retlen = 0;
2138
2139 /* Do not allow reads past end of device */
2140 if (ops->datbuf && (from + ops->len) > mtd->size) {
2141 pr_debug("%s: attempt to read beyond end of device\n",
2142 __func__);
2143 return -EINVAL;
2144 }
2145
2146 nand_get_device(mtd, FL_READING);
2147
2148 switch (ops->mode) {
2149 case MTD_OPS_PLACE_OOB:
2150 case MTD_OPS_AUTO_OOB:
2151 case MTD_OPS_RAW:
2152 break;
2153
2154 default:
2155 goto out;
2156 }
2157
2158 if (!ops->datbuf)
2159 ret = nand_do_read_oob(mtd, from, ops);
2160 else
2161 ret = nand_do_read_ops(mtd, from, ops);
2162
2163 out:
2164 nand_release_device(mtd);
2165 return ret;
2166 }
2167
2168
2169 /**
2170 * nand_write_page_raw - [INTERN] raw page write function
2171 * @mtd: mtd info structure
2172 * @chip: nand chip info structure
2173 * @buf: data buffer
2174 * @oob_required: must write chip->oob_poi to OOB
2175 * @page: page number to write
2176 *
2177 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2178 */
nand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2179 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2180 const uint8_t *buf, int oob_required, int page)
2181 {
2182 chip->write_buf(mtd, buf, mtd->writesize);
2183 if (oob_required)
2184 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2185
2186 return 0;
2187 }
2188
2189 /**
2190 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2191 * @mtd: mtd info structure
2192 * @chip: nand chip info structure
2193 * @buf: data buffer
2194 * @oob_required: must write chip->oob_poi to OOB
2195 * @page: page number to write
2196 *
2197 * We need a special oob layout and handling even when ECC isn't checked.
2198 */
nand_write_page_raw_syndrome(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2199 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2200 struct nand_chip *chip,
2201 const uint8_t *buf, int oob_required,
2202 int page)
2203 {
2204 int eccsize = chip->ecc.size;
2205 int eccbytes = chip->ecc.bytes;
2206 uint8_t *oob = chip->oob_poi;
2207 int steps, size;
2208
2209 for (steps = chip->ecc.steps; steps > 0; steps--) {
2210 chip->write_buf(mtd, buf, eccsize);
2211 buf += eccsize;
2212
2213 if (chip->ecc.prepad) {
2214 chip->write_buf(mtd, oob, chip->ecc.prepad);
2215 oob += chip->ecc.prepad;
2216 }
2217
2218 chip->write_buf(mtd, oob, eccbytes);
2219 oob += eccbytes;
2220
2221 if (chip->ecc.postpad) {
2222 chip->write_buf(mtd, oob, chip->ecc.postpad);
2223 oob += chip->ecc.postpad;
2224 }
2225 }
2226
2227 size = mtd->oobsize - (oob - chip->oob_poi);
2228 if (size)
2229 chip->write_buf(mtd, oob, size);
2230
2231 return 0;
2232 }
2233 /**
2234 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2235 * @mtd: mtd info structure
2236 * @chip: nand chip info structure
2237 * @buf: data buffer
2238 * @oob_required: must write chip->oob_poi to OOB
2239 * @page: page number to write
2240 */
nand_write_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2241 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2242 const uint8_t *buf, int oob_required,
2243 int page)
2244 {
2245 int i, eccsize = chip->ecc.size;
2246 int eccbytes = chip->ecc.bytes;
2247 int eccsteps = chip->ecc.steps;
2248 uint8_t *ecc_calc = chip->buffers->ecccalc;
2249 const uint8_t *p = buf;
2250 uint32_t *eccpos = chip->ecc.layout->eccpos;
2251
2252 /* Software ECC calculation */
2253 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2254 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2255
2256 for (i = 0; i < chip->ecc.total; i++)
2257 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2258
2259 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
2260 }
2261
2262 /**
2263 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2264 * @mtd: mtd info structure
2265 * @chip: nand chip info structure
2266 * @buf: data buffer
2267 * @oob_required: must write chip->oob_poi to OOB
2268 * @page: page number to write
2269 */
nand_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2270 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2271 const uint8_t *buf, int oob_required,
2272 int page)
2273 {
2274 int i, eccsize = chip->ecc.size;
2275 int eccbytes = chip->ecc.bytes;
2276 int eccsteps = chip->ecc.steps;
2277 uint8_t *ecc_calc = chip->buffers->ecccalc;
2278 const uint8_t *p = buf;
2279 uint32_t *eccpos = chip->ecc.layout->eccpos;
2280
2281 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2282 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2283 chip->write_buf(mtd, p, eccsize);
2284 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2285 }
2286
2287 for (i = 0; i < chip->ecc.total; i++)
2288 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2289
2290 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2291
2292 return 0;
2293 }
2294
2295
2296 /**
2297 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2298 * @mtd: mtd info structure
2299 * @chip: nand chip info structure
2300 * @offset: column address of subpage within the page
2301 * @data_len: data length
2302 * @buf: data buffer
2303 * @oob_required: must write chip->oob_poi to OOB
2304 * @page: page number to write
2305 */
nand_write_subpage_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,uint32_t data_len,const uint8_t * buf,int oob_required,int page)2306 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2307 struct nand_chip *chip, uint32_t offset,
2308 uint32_t data_len, const uint8_t *buf,
2309 int oob_required, int page)
2310 {
2311 uint8_t *oob_buf = chip->oob_poi;
2312 uint8_t *ecc_calc = chip->buffers->ecccalc;
2313 int ecc_size = chip->ecc.size;
2314 int ecc_bytes = chip->ecc.bytes;
2315 int ecc_steps = chip->ecc.steps;
2316 uint32_t *eccpos = chip->ecc.layout->eccpos;
2317 uint32_t start_step = offset / ecc_size;
2318 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2319 int oob_bytes = mtd->oobsize / ecc_steps;
2320 int step, i;
2321
2322 for (step = 0; step < ecc_steps; step++) {
2323 /* configure controller for WRITE access */
2324 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2325
2326 /* write data (untouched subpages already masked by 0xFF) */
2327 chip->write_buf(mtd, buf, ecc_size);
2328
2329 /* mask ECC of un-touched subpages by padding 0xFF */
2330 if ((step < start_step) || (step > end_step))
2331 memset(ecc_calc, 0xff, ecc_bytes);
2332 else
2333 chip->ecc.calculate(mtd, buf, ecc_calc);
2334
2335 /* mask OOB of un-touched subpages by padding 0xFF */
2336 /* if oob_required, preserve OOB metadata of written subpage */
2337 if (!oob_required || (step < start_step) || (step > end_step))
2338 memset(oob_buf, 0xff, oob_bytes);
2339
2340 buf += ecc_size;
2341 ecc_calc += ecc_bytes;
2342 oob_buf += oob_bytes;
2343 }
2344
2345 /* copy calculated ECC for whole page to chip->buffer->oob */
2346 /* this include masked-value(0xFF) for unwritten subpages */
2347 ecc_calc = chip->buffers->ecccalc;
2348 for (i = 0; i < chip->ecc.total; i++)
2349 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2350
2351 /* write OOB buffer to NAND device */
2352 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2353
2354 return 0;
2355 }
2356
2357
2358 /**
2359 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2360 * @mtd: mtd info structure
2361 * @chip: nand chip info structure
2362 * @buf: data buffer
2363 * @oob_required: must write chip->oob_poi to OOB
2364 * @page: page number to write
2365 *
2366 * The hw generator calculates the error syndrome automatically. Therefore we
2367 * need a special oob layout and handling.
2368 */
nand_write_page_syndrome(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2369 static int nand_write_page_syndrome(struct mtd_info *mtd,
2370 struct nand_chip *chip,
2371 const uint8_t *buf, int oob_required,
2372 int page)
2373 {
2374 int i, eccsize = chip->ecc.size;
2375 int eccbytes = chip->ecc.bytes;
2376 int eccsteps = chip->ecc.steps;
2377 const uint8_t *p = buf;
2378 uint8_t *oob = chip->oob_poi;
2379
2380 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2381
2382 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2383 chip->write_buf(mtd, p, eccsize);
2384
2385 if (chip->ecc.prepad) {
2386 chip->write_buf(mtd, oob, chip->ecc.prepad);
2387 oob += chip->ecc.prepad;
2388 }
2389
2390 chip->ecc.calculate(mtd, p, oob);
2391 chip->write_buf(mtd, oob, eccbytes);
2392 oob += eccbytes;
2393
2394 if (chip->ecc.postpad) {
2395 chip->write_buf(mtd, oob, chip->ecc.postpad);
2396 oob += chip->ecc.postpad;
2397 }
2398 }
2399
2400 /* Calculate remaining oob bytes */
2401 i = mtd->oobsize - (oob - chip->oob_poi);
2402 if (i)
2403 chip->write_buf(mtd, oob, i);
2404
2405 return 0;
2406 }
2407
2408 /**
2409 * nand_write_page - [REPLACEABLE] write one page
2410 * @mtd: MTD device structure
2411 * @chip: NAND chip descriptor
2412 * @offset: address offset within the page
2413 * @data_len: length of actual data to be written
2414 * @buf: the data to write
2415 * @oob_required: must write chip->oob_poi to OOB
2416 * @page: page number to write
2417 * @raw: use _raw version of write_page
2418 */
nand_write_page(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,int data_len,const uint8_t * buf,int oob_required,int page,int raw)2419 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2420 uint32_t offset, int data_len, const uint8_t *buf,
2421 int oob_required, int page, int raw)
2422 {
2423 int status, subpage;
2424
2425 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2426 chip->ecc.write_subpage)
2427 subpage = offset || (data_len < mtd->writesize);
2428 else
2429 subpage = 0;
2430
2431 if (nand_standard_page_accessors(&chip->ecc))
2432 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2433
2434 if (unlikely(raw))
2435 status = chip->ecc.write_page_raw(mtd, chip, buf,
2436 oob_required, page);
2437 else if (subpage)
2438 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2439 buf, oob_required, page);
2440 else
2441 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2442 page);
2443
2444 if (status < 0)
2445 return status;
2446
2447 if (nand_standard_page_accessors(&chip->ecc)) {
2448 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2449
2450 status = chip->waitfunc(mtd, chip);
2451 if (status & NAND_STATUS_FAIL)
2452 return -EIO;
2453 }
2454
2455 return 0;
2456 }
2457
2458 /**
2459 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2460 * @mtd: MTD device structure
2461 * @oob: oob data buffer
2462 * @len: oob data write length
2463 * @ops: oob ops structure
2464 */
nand_fill_oob(struct mtd_info * mtd,uint8_t * oob,size_t len,struct mtd_oob_ops * ops)2465 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2466 struct mtd_oob_ops *ops)
2467 {
2468 struct nand_chip *chip = mtd_to_nand(mtd);
2469
2470 /*
2471 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2472 * data from a previous OOB read.
2473 */
2474 memset(chip->oob_poi, 0xff, mtd->oobsize);
2475
2476 switch (ops->mode) {
2477
2478 case MTD_OPS_PLACE_OOB:
2479 case MTD_OPS_RAW:
2480 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2481 return oob + len;
2482
2483 case MTD_OPS_AUTO_OOB: {
2484 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2485 uint32_t boffs = 0, woffs = ops->ooboffs;
2486 size_t bytes = 0;
2487
2488 for (; free->length && len; free++, len -= bytes) {
2489 /* Write request not from offset 0? */
2490 if (unlikely(woffs)) {
2491 if (woffs >= free->length) {
2492 woffs -= free->length;
2493 continue;
2494 }
2495 boffs = free->offset + woffs;
2496 bytes = min_t(size_t, len,
2497 (free->length - woffs));
2498 woffs = 0;
2499 } else {
2500 bytes = min_t(size_t, len, free->length);
2501 boffs = free->offset;
2502 }
2503 memcpy(chip->oob_poi + boffs, oob, bytes);
2504 oob += bytes;
2505 }
2506 return oob;
2507 }
2508 default:
2509 BUG();
2510 }
2511 return NULL;
2512 }
2513
2514 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2515
2516 /**
2517 * nand_do_write_ops - [INTERN] NAND write with ECC
2518 * @mtd: MTD device structure
2519 * @to: offset to write to
2520 * @ops: oob operations description structure
2521 *
2522 * NAND write with ECC.
2523 */
nand_do_write_ops(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)2524 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2525 struct mtd_oob_ops *ops)
2526 {
2527 int chipnr, realpage, page, column;
2528 struct nand_chip *chip = mtd_to_nand(mtd);
2529 uint32_t writelen = ops->len;
2530
2531 uint32_t oobwritelen = ops->ooblen;
2532 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
2533
2534 uint8_t *oob = ops->oobbuf;
2535 uint8_t *buf = ops->datbuf;
2536 int ret;
2537 int oob_required = oob ? 1 : 0;
2538
2539 ops->retlen = 0;
2540 if (!writelen)
2541 return 0;
2542
2543 /* Reject writes, which are not page aligned */
2544 if (NOTALIGNED(to)) {
2545 pr_notice("%s: attempt to write non page aligned data\n",
2546 __func__);
2547 return -EINVAL;
2548 }
2549
2550 column = to & (mtd->writesize - 1);
2551
2552 chipnr = (int)(to >> chip->chip_shift);
2553 chip->select_chip(mtd, chipnr);
2554
2555 /* Check, if it is write protected */
2556 if (nand_check_wp(mtd)) {
2557 ret = -EIO;
2558 goto err_out;
2559 }
2560
2561 realpage = (int)(to >> chip->page_shift);
2562 page = realpage & chip->pagemask;
2563
2564 /* Invalidate the page cache, when we write to the cached page */
2565 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2566 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2567 chip->pagebuf = -1;
2568
2569 /* Don't allow multipage oob writes with offset */
2570 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2571 ret = -EINVAL;
2572 goto err_out;
2573 }
2574
2575 while (1) {
2576 int bytes = mtd->writesize;
2577 uint8_t *wbuf = buf;
2578 int use_bufpoi;
2579 int part_pagewr = (column || writelen < mtd->writesize);
2580
2581 if (part_pagewr)
2582 use_bufpoi = 1;
2583 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2584 use_bufpoi = !IS_ALIGNED((unsigned long)buf,
2585 chip->buf_align);
2586 else
2587 use_bufpoi = 0;
2588
2589 WATCHDOG_RESET();
2590 /* Partial page write?, or need to use bounce buffer */
2591 if (use_bufpoi) {
2592 pr_debug("%s: using write bounce buffer for buf@%p\n",
2593 __func__, buf);
2594 if (part_pagewr)
2595 bytes = min_t(int, bytes - column, writelen);
2596 chip->pagebuf = -1;
2597 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2598 memcpy(&chip->buffers->databuf[column], buf, bytes);
2599 wbuf = chip->buffers->databuf;
2600 }
2601
2602 if (unlikely(oob)) {
2603 size_t len = min(oobwritelen, oobmaxlen);
2604 oob = nand_fill_oob(mtd, oob, len, ops);
2605 oobwritelen -= len;
2606 } else {
2607 /* We still need to erase leftover OOB data */
2608 memset(chip->oob_poi, 0xff, mtd->oobsize);
2609 }
2610 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2611 oob_required, page,
2612 (ops->mode == MTD_OPS_RAW));
2613 if (ret)
2614 break;
2615
2616 writelen -= bytes;
2617 if (!writelen)
2618 break;
2619
2620 column = 0;
2621 buf += bytes;
2622 realpage++;
2623
2624 page = realpage & chip->pagemask;
2625 /* Check, if we cross a chip boundary */
2626 if (!page) {
2627 chipnr++;
2628 chip->select_chip(mtd, -1);
2629 chip->select_chip(mtd, chipnr);
2630 }
2631 }
2632
2633 ops->retlen = ops->len - writelen;
2634 if (unlikely(oob))
2635 ops->oobretlen = ops->ooblen;
2636
2637 err_out:
2638 chip->select_chip(mtd, -1);
2639 return ret;
2640 }
2641
2642 /**
2643 * panic_nand_write - [MTD Interface] NAND write with ECC
2644 * @mtd: MTD device structure
2645 * @to: offset to write to
2646 * @len: number of bytes to write
2647 * @retlen: pointer to variable to store the number of written bytes
2648 * @buf: the data to write
2649 *
2650 * NAND write with ECC. Used when performing writes in interrupt context, this
2651 * may for example be called by mtdoops when writing an oops while in panic.
2652 */
panic_nand_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const uint8_t * buf)2653 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2654 size_t *retlen, const uint8_t *buf)
2655 {
2656 struct nand_chip *chip = mtd_to_nand(mtd);
2657 struct mtd_oob_ops ops;
2658 int ret;
2659
2660 /* Wait for the device to get ready */
2661 panic_nand_wait(mtd, chip, 400);
2662
2663 /* Grab the device */
2664 panic_nand_get_device(chip, mtd, FL_WRITING);
2665
2666 memset(&ops, 0, sizeof(ops));
2667 ops.len = len;
2668 ops.datbuf = (uint8_t *)buf;
2669 ops.mode = MTD_OPS_PLACE_OOB;
2670
2671 ret = nand_do_write_ops(mtd, to, &ops);
2672
2673 *retlen = ops.retlen;
2674 return ret;
2675 }
2676
2677 /**
2678 * nand_write - [MTD Interface] NAND write with ECC
2679 * @mtd: MTD device structure
2680 * @to: offset to write to
2681 * @len: number of bytes to write
2682 * @retlen: pointer to variable to store the number of written bytes
2683 * @buf: the data to write
2684 *
2685 * NAND write with ECC.
2686 */
nand_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const uint8_t * buf)2687 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2688 size_t *retlen, const uint8_t *buf)
2689 {
2690 struct mtd_oob_ops ops;
2691 int ret;
2692
2693 nand_get_device(mtd, FL_WRITING);
2694 memset(&ops, 0, sizeof(ops));
2695 ops.len = len;
2696 ops.datbuf = (uint8_t *)buf;
2697 ops.mode = MTD_OPS_PLACE_OOB;
2698 ret = nand_do_write_ops(mtd, to, &ops);
2699 *retlen = ops.retlen;
2700 nand_release_device(mtd);
2701 return ret;
2702 }
2703
2704 /**
2705 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2706 * @mtd: MTD device structure
2707 * @to: offset to write to
2708 * @ops: oob operation description structure
2709 *
2710 * NAND write out-of-band.
2711 */
nand_do_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)2712 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2713 struct mtd_oob_ops *ops)
2714 {
2715 int chipnr, page, status, len;
2716 struct nand_chip *chip = mtd_to_nand(mtd);
2717
2718 pr_debug("%s: to = 0x%08x, len = %i\n",
2719 __func__, (unsigned int)to, (int)ops->ooblen);
2720
2721 len = mtd_oobavail(mtd, ops);
2722
2723 /* Do not allow write past end of page */
2724 if ((ops->ooboffs + ops->ooblen) > len) {
2725 pr_debug("%s: attempt to write past end of page\n",
2726 __func__);
2727 return -EINVAL;
2728 }
2729
2730 if (unlikely(ops->ooboffs >= len)) {
2731 pr_debug("%s: attempt to start write outside oob\n",
2732 __func__);
2733 return -EINVAL;
2734 }
2735
2736 /* Do not allow write past end of device */
2737 if (unlikely(to >= mtd->size ||
2738 ops->ooboffs + ops->ooblen >
2739 ((mtd->size >> chip->page_shift) -
2740 (to >> chip->page_shift)) * len)) {
2741 pr_debug("%s: attempt to write beyond end of device\n",
2742 __func__);
2743 return -EINVAL;
2744 }
2745
2746 chipnr = (int)(to >> chip->chip_shift);
2747
2748 /*
2749 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2750 * of my DiskOnChip 2000 test units) will clear the whole data page too
2751 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2752 * it in the doc2000 driver in August 1999. dwmw2.
2753 */
2754 nand_reset(chip, chipnr);
2755
2756 chip->select_chip(mtd, chipnr);
2757
2758 /* Shift to get page */
2759 page = (int)(to >> chip->page_shift);
2760
2761 /* Check, if it is write protected */
2762 if (nand_check_wp(mtd)) {
2763 chip->select_chip(mtd, -1);
2764 return -EROFS;
2765 }
2766
2767 /* Invalidate the page cache, if we write to the cached page */
2768 if (page == chip->pagebuf)
2769 chip->pagebuf = -1;
2770
2771 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2772
2773 if (ops->mode == MTD_OPS_RAW)
2774 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2775 else
2776 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2777
2778 chip->select_chip(mtd, -1);
2779
2780 if (status)
2781 return status;
2782
2783 ops->oobretlen = ops->ooblen;
2784
2785 return 0;
2786 }
2787
2788 /**
2789 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2790 * @mtd: MTD device structure
2791 * @to: offset to write to
2792 * @ops: oob operation description structure
2793 */
nand_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)2794 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2795 struct mtd_oob_ops *ops)
2796 {
2797 int ret = -ENOTSUPP;
2798
2799 ops->retlen = 0;
2800
2801 /* Do not allow writes past end of device */
2802 if (ops->datbuf && (to + ops->len) > mtd->size) {
2803 pr_debug("%s: attempt to write beyond end of device\n",
2804 __func__);
2805 return -EINVAL;
2806 }
2807
2808 nand_get_device(mtd, FL_WRITING);
2809
2810 switch (ops->mode) {
2811 case MTD_OPS_PLACE_OOB:
2812 case MTD_OPS_AUTO_OOB:
2813 case MTD_OPS_RAW:
2814 break;
2815
2816 default:
2817 goto out;
2818 }
2819
2820 if (!ops->datbuf)
2821 ret = nand_do_write_oob(mtd, to, ops);
2822 else
2823 ret = nand_do_write_ops(mtd, to, ops);
2824
2825 out:
2826 nand_release_device(mtd);
2827 return ret;
2828 }
2829
2830 /**
2831 * single_erase - [GENERIC] NAND standard block erase command function
2832 * @mtd: MTD device structure
2833 * @page: the page address of the block which will be erased
2834 *
2835 * Standard erase command for NAND chips. Returns NAND status.
2836 */
single_erase(struct mtd_info * mtd,int page)2837 static int single_erase(struct mtd_info *mtd, int page)
2838 {
2839 struct nand_chip *chip = mtd_to_nand(mtd);
2840 /* Send commands to erase a block */
2841 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2842 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2843
2844 return chip->waitfunc(mtd, chip);
2845 }
2846
2847 /**
2848 * nand_erase - [MTD Interface] erase block(s)
2849 * @mtd: MTD device structure
2850 * @instr: erase instruction
2851 *
2852 * Erase one ore more blocks.
2853 */
nand_erase(struct mtd_info * mtd,struct erase_info * instr)2854 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2855 {
2856 return nand_erase_nand(mtd, instr, 0);
2857 }
2858
2859 /**
2860 * nand_erase_nand - [INTERN] erase block(s)
2861 * @mtd: MTD device structure
2862 * @instr: erase instruction
2863 * @allowbbt: allow erasing the bbt area
2864 *
2865 * Erase one ore more blocks.
2866 */
nand_erase_nand(struct mtd_info * mtd,struct erase_info * instr,int allowbbt)2867 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2868 int allowbbt)
2869 {
2870 int page, status, pages_per_block, ret, chipnr;
2871 struct nand_chip *chip = mtd_to_nand(mtd);
2872 loff_t len;
2873
2874 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2875 __func__, (unsigned long long)instr->addr,
2876 (unsigned long long)instr->len);
2877
2878 if (check_offs_len(mtd, instr->addr, instr->len))
2879 return -EINVAL;
2880
2881 /* Grab the lock and see if the device is available */
2882 nand_get_device(mtd, FL_ERASING);
2883
2884 /* Shift to get first page */
2885 page = (int)(instr->addr >> chip->page_shift);
2886 chipnr = (int)(instr->addr >> chip->chip_shift);
2887
2888 /* Calculate pages in each block */
2889 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2890
2891 /* Select the NAND device */
2892 chip->select_chip(mtd, chipnr);
2893
2894 /* Check, if it is write protected */
2895 if (nand_check_wp(mtd)) {
2896 pr_debug("%s: device is write protected!\n",
2897 __func__);
2898 instr->state = MTD_ERASE_FAILED;
2899 goto erase_exit;
2900 }
2901
2902 /* Loop through the pages */
2903 len = instr->len;
2904
2905 instr->state = MTD_ERASING;
2906
2907 while (len) {
2908 WATCHDOG_RESET();
2909
2910 /* Check if we have a bad block, we do not erase bad blocks! */
2911 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2912 chip->page_shift, allowbbt)) {
2913 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2914 __func__, page);
2915 instr->state = MTD_ERASE_FAILED;
2916 goto erase_exit;
2917 }
2918
2919 /*
2920 * Invalidate the page cache, if we erase the block which
2921 * contains the current cached page.
2922 */
2923 if (page <= chip->pagebuf && chip->pagebuf <
2924 (page + pages_per_block))
2925 chip->pagebuf = -1;
2926
2927 status = chip->erase(mtd, page & chip->pagemask);
2928
2929 /* See if block erase succeeded */
2930 if (status & NAND_STATUS_FAIL) {
2931 pr_debug("%s: failed erase, page 0x%08x\n",
2932 __func__, page);
2933 instr->state = MTD_ERASE_FAILED;
2934 instr->fail_addr =
2935 ((loff_t)page << chip->page_shift);
2936 goto erase_exit;
2937 }
2938
2939 /* Increment page address and decrement length */
2940 len -= (1ULL << chip->phys_erase_shift);
2941 page += pages_per_block;
2942
2943 /* Check, if we cross a chip boundary */
2944 if (len && !(page & chip->pagemask)) {
2945 chipnr++;
2946 chip->select_chip(mtd, -1);
2947 chip->select_chip(mtd, chipnr);
2948 }
2949 }
2950 instr->state = MTD_ERASE_DONE;
2951
2952 erase_exit:
2953
2954 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2955
2956 /* Deselect and wake up anyone waiting on the device */
2957 chip->select_chip(mtd, -1);
2958 nand_release_device(mtd);
2959
2960 /* Do call back function */
2961 if (!ret)
2962 mtd_erase_callback(instr);
2963
2964 /* Return more or less happy */
2965 return ret;
2966 }
2967
2968 /**
2969 * nand_sync - [MTD Interface] sync
2970 * @mtd: MTD device structure
2971 *
2972 * Sync is actually a wait for chip ready function.
2973 */
nand_sync(struct mtd_info * mtd)2974 static void nand_sync(struct mtd_info *mtd)
2975 {
2976 pr_debug("%s: called\n", __func__);
2977
2978 /* Grab the lock and see if the device is available */
2979 nand_get_device(mtd, FL_SYNCING);
2980 /* Release it and go back */
2981 nand_release_device(mtd);
2982 }
2983
2984 /**
2985 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2986 * @mtd: MTD device structure
2987 * @offs: offset relative to mtd start
2988 */
nand_block_isbad(struct mtd_info * mtd,loff_t offs)2989 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2990 {
2991 struct nand_chip *chip = mtd_to_nand(mtd);
2992 int chipnr = (int)(offs >> chip->chip_shift);
2993 int ret;
2994
2995 /* Select the NAND device */
2996 nand_get_device(mtd, FL_READING);
2997 chip->select_chip(mtd, chipnr);
2998
2999 ret = nand_block_checkbad(mtd, offs, 0);
3000
3001 chip->select_chip(mtd, -1);
3002 nand_release_device(mtd);
3003
3004 return ret;
3005 }
3006
3007 /**
3008 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3009 * @mtd: MTD device structure
3010 * @ofs: offset relative to mtd start
3011 */
nand_block_markbad(struct mtd_info * mtd,loff_t ofs)3012 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3013 {
3014 int ret;
3015
3016 ret = nand_block_isbad(mtd, ofs);
3017 if (ret) {
3018 /* If it was bad already, return success and do nothing */
3019 if (ret > 0)
3020 return 0;
3021 return ret;
3022 }
3023
3024 return nand_block_markbad_lowlevel(mtd, ofs);
3025 }
3026
3027 /**
3028 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3029 * @mtd: MTD device structure
3030 * @chip: nand chip info structure
3031 * @addr: feature address.
3032 * @subfeature_param: the subfeature parameters, a four bytes array.
3033 */
nand_onfi_set_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,uint8_t * subfeature_param)3034 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3035 int addr, uint8_t *subfeature_param)
3036 {
3037 int status;
3038 int i;
3039
3040 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3041 if (!chip->onfi_version ||
3042 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3043 & ONFI_OPT_CMD_SET_GET_FEATURES))
3044 return -EINVAL;
3045 #endif
3046
3047 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3048 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3049 chip->write_byte(mtd, subfeature_param[i]);
3050
3051 status = chip->waitfunc(mtd, chip);
3052 if (status & NAND_STATUS_FAIL)
3053 return -EIO;
3054 return 0;
3055 }
3056
3057 /**
3058 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3059 * @mtd: MTD device structure
3060 * @chip: nand chip info structure
3061 * @addr: feature address.
3062 * @subfeature_param: the subfeature parameters, a four bytes array.
3063 */
nand_onfi_get_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,uint8_t * subfeature_param)3064 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3065 int addr, uint8_t *subfeature_param)
3066 {
3067 int i;
3068
3069 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3070 if (!chip->onfi_version ||
3071 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3072 & ONFI_OPT_CMD_SET_GET_FEATURES))
3073 return -EINVAL;
3074 #endif
3075
3076 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3077 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3078 *subfeature_param++ = chip->read_byte(mtd);
3079 return 0;
3080 }
3081
3082 /* Set default functions */
nand_set_defaults(struct nand_chip * chip,int busw)3083 static void nand_set_defaults(struct nand_chip *chip, int busw)
3084 {
3085 /* check for proper chip_delay setup, set 20us if not */
3086 if (!chip->chip_delay)
3087 chip->chip_delay = 20;
3088
3089 /* check, if a user supplied command function given */
3090 if (chip->cmdfunc == NULL)
3091 chip->cmdfunc = nand_command;
3092
3093 /* check, if a user supplied wait function given */
3094 if (chip->waitfunc == NULL)
3095 chip->waitfunc = nand_wait;
3096
3097 if (!chip->select_chip)
3098 chip->select_chip = nand_select_chip;
3099
3100 /* set for ONFI nand */
3101 if (!chip->onfi_set_features)
3102 chip->onfi_set_features = nand_onfi_set_features;
3103 if (!chip->onfi_get_features)
3104 chip->onfi_get_features = nand_onfi_get_features;
3105
3106 /* If called twice, pointers that depend on busw may need to be reset */
3107 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3108 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3109 if (!chip->read_word)
3110 chip->read_word = nand_read_word;
3111 if (!chip->block_bad)
3112 chip->block_bad = nand_block_bad;
3113 if (!chip->block_markbad)
3114 chip->block_markbad = nand_default_block_markbad;
3115 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3116 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3117 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3118 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3119 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3120 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3121 if (!chip->scan_bbt)
3122 chip->scan_bbt = nand_default_bbt;
3123
3124 if (!chip->controller) {
3125 chip->controller = &chip->hwcontrol;
3126 spin_lock_init(&chip->controller->lock);
3127 init_waitqueue_head(&chip->controller->wq);
3128 }
3129
3130 if (!chip->buf_align)
3131 chip->buf_align = 1;
3132 }
3133
3134 /* Sanitize ONFI strings so we can safely print them */
sanitize_string(char * s,size_t len)3135 static void sanitize_string(char *s, size_t len)
3136 {
3137 ssize_t i;
3138
3139 /* Null terminate */
3140 s[len - 1] = 0;
3141
3142 /* Remove non printable chars */
3143 for (i = 0; i < len - 1; i++) {
3144 if (s[i] < ' ' || s[i] > 127)
3145 s[i] = '?';
3146 }
3147
3148 /* Remove trailing spaces */
3149 strim(s);
3150 }
3151
onfi_crc16(u16 crc,u8 const * p,size_t len)3152 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3153 {
3154 int i;
3155 while (len--) {
3156 crc ^= *p++ << 8;
3157 for (i = 0; i < 8; i++)
3158 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3159 }
3160
3161 return crc;
3162 }
3163
3164 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3165 /* Parse the Extended Parameter Page. */
nand_flash_detect_ext_param_page(struct mtd_info * mtd,struct nand_chip * chip,struct nand_onfi_params * p)3166 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3167 struct nand_chip *chip, struct nand_onfi_params *p)
3168 {
3169 struct onfi_ext_param_page *ep;
3170 struct onfi_ext_section *s;
3171 struct onfi_ext_ecc_info *ecc;
3172 uint8_t *cursor;
3173 int ret = -EINVAL;
3174 int len;
3175 int i;
3176
3177 len = le16_to_cpu(p->ext_param_page_length) * 16;
3178 ep = kmalloc(len, GFP_KERNEL);
3179 if (!ep)
3180 return -ENOMEM;
3181
3182 /* Send our own NAND_CMD_PARAM. */
3183 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3184
3185 /* Use the Change Read Column command to skip the ONFI param pages. */
3186 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3187 sizeof(*p) * p->num_of_param_pages , -1);
3188
3189 /* Read out the Extended Parameter Page. */
3190 chip->read_buf(mtd, (uint8_t *)ep, len);
3191 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3192 != le16_to_cpu(ep->crc))) {
3193 pr_debug("fail in the CRC.\n");
3194 goto ext_out;
3195 }
3196
3197 /*
3198 * Check the signature.
3199 * Do not strictly follow the ONFI spec, maybe changed in future.
3200 */
3201 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3202 pr_debug("The signature is invalid.\n");
3203 goto ext_out;
3204 }
3205
3206 /* find the ECC section. */
3207 cursor = (uint8_t *)(ep + 1);
3208 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3209 s = ep->sections + i;
3210 if (s->type == ONFI_SECTION_TYPE_2)
3211 break;
3212 cursor += s->length * 16;
3213 }
3214 if (i == ONFI_EXT_SECTION_MAX) {
3215 pr_debug("We can not find the ECC section.\n");
3216 goto ext_out;
3217 }
3218
3219 /* get the info we want. */
3220 ecc = (struct onfi_ext_ecc_info *)cursor;
3221
3222 if (!ecc->codeword_size) {
3223 pr_debug("Invalid codeword size\n");
3224 goto ext_out;
3225 }
3226
3227 chip->ecc_strength_ds = ecc->ecc_bits;
3228 chip->ecc_step_ds = 1 << ecc->codeword_size;
3229 ret = 0;
3230
3231 ext_out:
3232 kfree(ep);
3233 return ret;
3234 }
3235
nand_setup_read_retry_micron(struct mtd_info * mtd,int retry_mode)3236 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3237 {
3238 struct nand_chip *chip = mtd_to_nand(mtd);
3239 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3240
3241 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3242 feature);
3243 }
3244
3245 /*
3246 * Configure chip properties from Micron vendor-specific ONFI table
3247 */
nand_onfi_detect_micron(struct nand_chip * chip,struct nand_onfi_params * p)3248 static void nand_onfi_detect_micron(struct nand_chip *chip,
3249 struct nand_onfi_params *p)
3250 {
3251 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3252
3253 if (le16_to_cpu(p->vendor_revision) < 1)
3254 return;
3255
3256 chip->read_retries = micron->read_retry_options;
3257 chip->setup_read_retry = nand_setup_read_retry_micron;
3258 }
3259
3260 /*
3261 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3262 */
nand_flash_detect_onfi(struct mtd_info * mtd,struct nand_chip * chip,int * busw)3263 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3264 int *busw)
3265 {
3266 struct nand_onfi_params *p = &chip->onfi_params;
3267 int i, j;
3268 int val;
3269
3270 /* Try ONFI for unknown chip or LP */
3271 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3272 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3273 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3274 return 0;
3275
3276 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3277 for (i = 0; i < 3; i++) {
3278 for (j = 0; j < sizeof(*p); j++)
3279 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3280 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3281 le16_to_cpu(p->crc)) {
3282 break;
3283 }
3284 }
3285
3286 if (i == 3) {
3287 pr_err("Could not find valid ONFI parameter page; aborting\n");
3288 return 0;
3289 }
3290
3291 /* Check version */
3292 val = le16_to_cpu(p->revision);
3293 if (val & (1 << 5))
3294 chip->onfi_version = 23;
3295 else if (val & (1 << 4))
3296 chip->onfi_version = 22;
3297 else if (val & (1 << 3))
3298 chip->onfi_version = 21;
3299 else if (val & (1 << 2))
3300 chip->onfi_version = 20;
3301 else if (val & (1 << 1))
3302 chip->onfi_version = 10;
3303
3304 if (!chip->onfi_version) {
3305 pr_info("unsupported ONFI version: %d\n", val);
3306 return 0;
3307 }
3308
3309 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3310 sanitize_string(p->model, sizeof(p->model));
3311 if (!mtd->name)
3312 mtd->name = p->model;
3313
3314 mtd->writesize = le32_to_cpu(p->byte_per_page);
3315
3316 /*
3317 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3318 * (don't ask me who thought of this...). MTD assumes that these
3319 * dimensions will be power-of-2, so just truncate the remaining area.
3320 */
3321 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3322 mtd->erasesize *= mtd->writesize;
3323
3324 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3325
3326 /* See erasesize comment */
3327 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3328 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3329 chip->bits_per_cell = p->bits_per_cell;
3330
3331 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3332 *busw = NAND_BUSWIDTH_16;
3333 else
3334 *busw = 0;
3335
3336 if (p->ecc_bits != 0xff) {
3337 chip->ecc_strength_ds = p->ecc_bits;
3338 chip->ecc_step_ds = 512;
3339 } else if (chip->onfi_version >= 21 &&
3340 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3341
3342 /*
3343 * The nand_flash_detect_ext_param_page() uses the
3344 * Change Read Column command which maybe not supported
3345 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3346 * now. We do not replace user supplied command function.
3347 */
3348 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3349 chip->cmdfunc = nand_command_lp;
3350
3351 /* The Extended Parameter Page is supported since ONFI 2.1. */
3352 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3353 pr_warn("Failed to detect ONFI extended param page\n");
3354 } else {
3355 pr_warn("Could not retrieve ONFI ECC requirements\n");
3356 }
3357
3358 if (p->jedec_id == NAND_MFR_MICRON)
3359 nand_onfi_detect_micron(chip, p);
3360
3361 return 1;
3362 }
3363 #else
nand_flash_detect_onfi(struct mtd_info * mtd,struct nand_chip * chip,int * busw)3364 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3365 int *busw)
3366 {
3367 return 0;
3368 }
3369 #endif
3370
3371 /*
3372 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3373 */
nand_flash_detect_jedec(struct mtd_info * mtd,struct nand_chip * chip,int * busw)3374 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3375 int *busw)
3376 {
3377 struct nand_jedec_params *p = &chip->jedec_params;
3378 struct jedec_ecc_info *ecc;
3379 int val;
3380 int i, j;
3381
3382 /* Try JEDEC for unknown chip or LP */
3383 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3384 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3385 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3386 chip->read_byte(mtd) != 'C')
3387 return 0;
3388
3389 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3390 for (i = 0; i < 3; i++) {
3391 for (j = 0; j < sizeof(*p); j++)
3392 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3393
3394 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3395 le16_to_cpu(p->crc))
3396 break;
3397 }
3398
3399 if (i == 3) {
3400 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3401 return 0;
3402 }
3403
3404 /* Check version */
3405 val = le16_to_cpu(p->revision);
3406 if (val & (1 << 2))
3407 chip->jedec_version = 10;
3408 else if (val & (1 << 1))
3409 chip->jedec_version = 1; /* vendor specific version */
3410
3411 if (!chip->jedec_version) {
3412 pr_info("unsupported JEDEC version: %d\n", val);
3413 return 0;
3414 }
3415
3416 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3417 sanitize_string(p->model, sizeof(p->model));
3418 if (!mtd->name)
3419 mtd->name = p->model;
3420
3421 mtd->writesize = le32_to_cpu(p->byte_per_page);
3422
3423 /* Please reference to the comment for nand_flash_detect_onfi. */
3424 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3425 mtd->erasesize *= mtd->writesize;
3426
3427 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3428
3429 /* Please reference to the comment for nand_flash_detect_onfi. */
3430 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3431 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3432 chip->bits_per_cell = p->bits_per_cell;
3433
3434 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3435 *busw = NAND_BUSWIDTH_16;
3436 else
3437 *busw = 0;
3438
3439 /* ECC info */
3440 ecc = &p->ecc_info[0];
3441
3442 if (ecc->codeword_size >= 9) {
3443 chip->ecc_strength_ds = ecc->ecc_bits;
3444 chip->ecc_step_ds = 1 << ecc->codeword_size;
3445 } else {
3446 pr_warn("Invalid codeword size\n");
3447 }
3448
3449 return 1;
3450 }
3451
3452 /*
3453 * nand_id_has_period - Check if an ID string has a given wraparound period
3454 * @id_data: the ID string
3455 * @arrlen: the length of the @id_data array
3456 * @period: the period of repitition
3457 *
3458 * Check if an ID string is repeated within a given sequence of bytes at
3459 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3460 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3461 * if the repetition has a period of @period; otherwise, returns zero.
3462 */
nand_id_has_period(u8 * id_data,int arrlen,int period)3463 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3464 {
3465 int i, j;
3466 for (i = 0; i < period; i++)
3467 for (j = i + period; j < arrlen; j += period)
3468 if (id_data[i] != id_data[j])
3469 return 0;
3470 return 1;
3471 }
3472
3473 /*
3474 * nand_id_len - Get the length of an ID string returned by CMD_READID
3475 * @id_data: the ID string
3476 * @arrlen: the length of the @id_data array
3477
3478 * Returns the length of the ID string, according to known wraparound/trailing
3479 * zero patterns. If no pattern exists, returns the length of the array.
3480 */
nand_id_len(u8 * id_data,int arrlen)3481 static int nand_id_len(u8 *id_data, int arrlen)
3482 {
3483 int last_nonzero, period;
3484
3485 /* Find last non-zero byte */
3486 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3487 if (id_data[last_nonzero])
3488 break;
3489
3490 /* All zeros */
3491 if (last_nonzero < 0)
3492 return 0;
3493
3494 /* Calculate wraparound period */
3495 for (period = 1; period < arrlen; period++)
3496 if (nand_id_has_period(id_data, arrlen, period))
3497 break;
3498
3499 /* There's a repeated pattern */
3500 if (period < arrlen)
3501 return period;
3502
3503 /* There are trailing zeros */
3504 if (last_nonzero < arrlen - 1)
3505 return last_nonzero + 1;
3506
3507 /* No pattern detected */
3508 return arrlen;
3509 }
3510
3511 /* Extract the bits of per cell from the 3rd byte of the extended ID */
nand_get_bits_per_cell(u8 cellinfo)3512 static int nand_get_bits_per_cell(u8 cellinfo)
3513 {
3514 int bits;
3515
3516 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3517 bits >>= NAND_CI_CELLTYPE_SHIFT;
3518 return bits + 1;
3519 }
3520
3521 /*
3522 * Many new NAND share similar device ID codes, which represent the size of the
3523 * chip. The rest of the parameters must be decoded according to generic or
3524 * manufacturer-specific "extended ID" decoding patterns.
3525 */
nand_decode_ext_id(struct mtd_info * mtd,struct nand_chip * chip,u8 id_data[8],int * busw)3526 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3527 u8 id_data[8], int *busw)
3528 {
3529 int extid, id_len;
3530 /* The 3rd id byte holds MLC / multichip data */
3531 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3532 /* The 4th id byte is the important one */
3533 extid = id_data[3];
3534
3535 id_len = nand_id_len(id_data, 8);
3536
3537 /*
3538 * Field definitions are in the following datasheets:
3539 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3540 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3541 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3542 *
3543 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3544 * ID to decide what to do.
3545 */
3546 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3547 !nand_is_slc(chip) && id_data[5] != 0x00) {
3548 /* Calc pagesize */
3549 mtd->writesize = 2048 << (extid & 0x03);
3550 extid >>= 2;
3551 /* Calc oobsize */
3552 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3553 case 1:
3554 mtd->oobsize = 128;
3555 break;
3556 case 2:
3557 mtd->oobsize = 218;
3558 break;
3559 case 3:
3560 mtd->oobsize = 400;
3561 break;
3562 case 4:
3563 mtd->oobsize = 436;
3564 break;
3565 case 5:
3566 mtd->oobsize = 512;
3567 break;
3568 case 6:
3569 mtd->oobsize = 640;
3570 break;
3571 case 7:
3572 default: /* Other cases are "reserved" (unknown) */
3573 mtd->oobsize = 1024;
3574 break;
3575 }
3576 extid >>= 2;
3577 /* Calc blocksize */
3578 mtd->erasesize = (128 * 1024) <<
3579 (((extid >> 1) & 0x04) | (extid & 0x03));
3580 *busw = 0;
3581 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3582 !nand_is_slc(chip)) {
3583 unsigned int tmp;
3584
3585 /* Calc pagesize */
3586 mtd->writesize = 2048 << (extid & 0x03);
3587 extid >>= 2;
3588 /* Calc oobsize */
3589 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3590 case 0:
3591 mtd->oobsize = 128;
3592 break;
3593 case 1:
3594 mtd->oobsize = 224;
3595 break;
3596 case 2:
3597 mtd->oobsize = 448;
3598 break;
3599 case 3:
3600 mtd->oobsize = 64;
3601 break;
3602 case 4:
3603 mtd->oobsize = 32;
3604 break;
3605 case 5:
3606 mtd->oobsize = 16;
3607 break;
3608 default:
3609 mtd->oobsize = 640;
3610 break;
3611 }
3612 extid >>= 2;
3613 /* Calc blocksize */
3614 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3615 if (tmp < 0x03)
3616 mtd->erasesize = (128 * 1024) << tmp;
3617 else if (tmp == 0x03)
3618 mtd->erasesize = 768 * 1024;
3619 else
3620 mtd->erasesize = (64 * 1024) << tmp;
3621 *busw = 0;
3622 } else {
3623 /* Calc pagesize */
3624 mtd->writesize = 1024 << (extid & 0x03);
3625 extid >>= 2;
3626 /* Calc oobsize */
3627 mtd->oobsize = (8 << (extid & 0x01)) *
3628 (mtd->writesize >> 9);
3629 extid >>= 2;
3630 /* Calc blocksize. Blocksize is multiples of 64KiB */
3631 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3632 extid >>= 2;
3633 /* Get buswidth information */
3634 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3635
3636 /*
3637 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3638 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3639 * follows:
3640 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3641 * 110b -> 24nm
3642 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3643 */
3644 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3645 nand_is_slc(chip) &&
3646 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3647 !(id_data[4] & 0x80) /* !BENAND */) {
3648 mtd->oobsize = 32 * mtd->writesize >> 9;
3649 }
3650
3651 }
3652 }
3653
3654 /*
3655 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3656 * decodes a matching ID table entry and assigns the MTD size parameters for
3657 * the chip.
3658 */
nand_decode_id(struct mtd_info * mtd,struct nand_chip * chip,struct nand_flash_dev * type,u8 id_data[8],int * busw)3659 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3660 struct nand_flash_dev *type, u8 id_data[8],
3661 int *busw)
3662 {
3663 int maf_id = id_data[0];
3664
3665 mtd->erasesize = type->erasesize;
3666 mtd->writesize = type->pagesize;
3667 mtd->oobsize = mtd->writesize / 32;
3668 *busw = type->options & NAND_BUSWIDTH_16;
3669
3670 /* All legacy ID NAND are small-page, SLC */
3671 chip->bits_per_cell = 1;
3672
3673 /*
3674 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3675 * some Spansion chips have erasesize that conflicts with size
3676 * listed in nand_ids table.
3677 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3678 */
3679 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3680 && id_data[6] == 0x00 && id_data[7] == 0x00
3681 && mtd->writesize == 512) {
3682 mtd->erasesize = 128 * 1024;
3683 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3684 }
3685 }
3686
3687 /*
3688 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3689 * heuristic patterns using various detected parameters (e.g., manufacturer,
3690 * page size, cell-type information).
3691 */
nand_decode_bbm_options(struct mtd_info * mtd,struct nand_chip * chip,u8 id_data[8])3692 static void nand_decode_bbm_options(struct mtd_info *mtd,
3693 struct nand_chip *chip, u8 id_data[8])
3694 {
3695 int maf_id = id_data[0];
3696
3697 /* Set the bad block position */
3698 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3699 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3700 else
3701 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3702
3703 /*
3704 * Bad block marker is stored in the last page of each block on Samsung
3705 * and Hynix MLC devices; stored in first two pages of each block on
3706 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3707 * AMD/Spansion, and Macronix. All others scan only the first page.
3708 */
3709 if (!nand_is_slc(chip) &&
3710 (maf_id == NAND_MFR_SAMSUNG ||
3711 maf_id == NAND_MFR_HYNIX))
3712 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3713 else if ((nand_is_slc(chip) &&
3714 (maf_id == NAND_MFR_SAMSUNG ||
3715 maf_id == NAND_MFR_HYNIX ||
3716 maf_id == NAND_MFR_TOSHIBA ||
3717 maf_id == NAND_MFR_AMD ||
3718 maf_id == NAND_MFR_MACRONIX)) ||
3719 (mtd->writesize == 2048 &&
3720 maf_id == NAND_MFR_MICRON))
3721 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3722 }
3723
is_full_id_nand(struct nand_flash_dev * type)3724 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3725 {
3726 return type->id_len;
3727 }
3728
find_full_id_nand(struct mtd_info * mtd,struct nand_chip * chip,struct nand_flash_dev * type,u8 * id_data,int * busw)3729 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3730 struct nand_flash_dev *type, u8 *id_data, int *busw)
3731 {
3732 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3733 mtd->writesize = type->pagesize;
3734 mtd->erasesize = type->erasesize;
3735 mtd->oobsize = type->oobsize;
3736
3737 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3738 chip->chipsize = (uint64_t)type->chipsize << 20;
3739 chip->options |= type->options;
3740 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3741 chip->ecc_step_ds = NAND_ECC_STEP(type);
3742 chip->onfi_timing_mode_default =
3743 type->onfi_timing_mode_default;
3744
3745 *busw = type->options & NAND_BUSWIDTH_16;
3746
3747 if (!mtd->name)
3748 mtd->name = type->name;
3749
3750 return true;
3751 }
3752 return false;
3753 }
3754
3755 /*
3756 * Get the flash and manufacturer id and lookup if the type is supported.
3757 */
nand_get_flash_type(struct mtd_info * mtd,struct nand_chip * chip,int * maf_id,int * dev_id,struct nand_flash_dev * type)3758 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3759 struct nand_chip *chip,
3760 int *maf_id, int *dev_id,
3761 struct nand_flash_dev *type)
3762 {
3763 int busw;
3764 int i, maf_idx;
3765 u8 id_data[8];
3766
3767 /*
3768 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3769 * after power-up.
3770 */
3771 nand_reset(chip, 0);
3772
3773 /* Select the device */
3774 chip->select_chip(mtd, 0);
3775
3776 /* Send the command for reading device ID */
3777 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3778
3779 /* Read manufacturer and device IDs */
3780 *maf_id = chip->read_byte(mtd);
3781 *dev_id = chip->read_byte(mtd);
3782
3783 /*
3784 * Try again to make sure, as some systems the bus-hold or other
3785 * interface concerns can cause random data which looks like a
3786 * possibly credible NAND flash to appear. If the two results do
3787 * not match, ignore the device completely.
3788 */
3789
3790 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3791
3792 /* Read entire ID string */
3793 for (i = 0; i < 8; i++)
3794 id_data[i] = chip->read_byte(mtd);
3795
3796 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3797 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3798 *maf_id, *dev_id, id_data[0], id_data[1]);
3799 return ERR_PTR(-ENODEV);
3800 }
3801
3802 if (!type)
3803 type = nand_flash_ids;
3804
3805 for (; type->name != NULL; type++) {
3806 if (is_full_id_nand(type)) {
3807 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3808 goto ident_done;
3809 } else if (*dev_id == type->dev_id) {
3810 break;
3811 }
3812 }
3813
3814 chip->onfi_version = 0;
3815 if (!type->name || !type->pagesize) {
3816 /* Check if the chip is ONFI compliant */
3817 if (nand_flash_detect_onfi(mtd, chip, &busw))
3818 goto ident_done;
3819
3820 /* Check if the chip is JEDEC compliant */
3821 if (nand_flash_detect_jedec(mtd, chip, &busw))
3822 goto ident_done;
3823 }
3824
3825 if (!type->name)
3826 return ERR_PTR(-ENODEV);
3827
3828 if (!mtd->name)
3829 mtd->name = type->name;
3830
3831 chip->chipsize = (uint64_t)type->chipsize << 20;
3832
3833 if (!type->pagesize) {
3834 /* Decode parameters from extended ID */
3835 nand_decode_ext_id(mtd, chip, id_data, &busw);
3836 } else {
3837 nand_decode_id(mtd, chip, type, id_data, &busw);
3838 }
3839 /* Get chip options */
3840 chip->options |= type->options;
3841
3842 /*
3843 * Check if chip is not a Samsung device. Do not clear the
3844 * options for chips which do not have an extended id.
3845 */
3846 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3847 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3848 ident_done:
3849
3850 /* Try to identify manufacturer */
3851 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3852 if (nand_manuf_ids[maf_idx].id == *maf_id)
3853 break;
3854 }
3855
3856 if (chip->options & NAND_BUSWIDTH_AUTO) {
3857 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3858 chip->options |= busw;
3859 nand_set_defaults(chip, busw);
3860 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3861 /*
3862 * Check, if buswidth is correct. Hardware drivers should set
3863 * chip correct!
3864 */
3865 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3866 *maf_id, *dev_id);
3867 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3868 pr_warn("bus width %d instead %d bit\n",
3869 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3870 busw ? 16 : 8);
3871 return ERR_PTR(-EINVAL);
3872 }
3873
3874 nand_decode_bbm_options(mtd, chip, id_data);
3875
3876 /* Calculate the address shift from the page size */
3877 chip->page_shift = ffs(mtd->writesize) - 1;
3878 /* Convert chipsize to number of pages per chip -1 */
3879 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3880
3881 chip->bbt_erase_shift = chip->phys_erase_shift =
3882 ffs(mtd->erasesize) - 1;
3883 if (chip->chipsize & 0xffffffff)
3884 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3885 else {
3886 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3887 chip->chip_shift += 32 - 1;
3888 }
3889
3890 if (chip->chip_shift - chip->page_shift > 16)
3891 chip->options |= NAND_ROW_ADDR_3;
3892
3893 chip->badblockbits = 8;
3894 chip->erase = single_erase;
3895
3896 /* Do not replace user supplied command function! */
3897 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3898 chip->cmdfunc = nand_command_lp;
3899
3900 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3901 *maf_id, *dev_id);
3902
3903 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3904 if (chip->onfi_version)
3905 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3906 chip->onfi_params.model);
3907 else if (chip->jedec_version)
3908 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3909 chip->jedec_params.model);
3910 else
3911 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3912 type->name);
3913 #else
3914 if (chip->jedec_version)
3915 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3916 chip->jedec_params.model);
3917 else
3918 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3919 type->name);
3920
3921 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3922 type->name);
3923 #endif
3924
3925 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3926 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3927 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
3928 return type;
3929 }
3930 EXPORT_SYMBOL(nand_get_flash_type);
3931
3932 #if CONFIG_IS_ENABLED(OF_CONTROL)
3933 DECLARE_GLOBAL_DATA_PTR;
3934
nand_dt_init(struct mtd_info * mtd,struct nand_chip * chip,int node)3935 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
3936 {
3937 int ret, ecc_mode = -1, ecc_strength, ecc_step;
3938 const void *blob = gd->fdt_blob;
3939 const char *str;
3940
3941 ret = fdtdec_get_int(blob, node, "nand-bus-width", -1);
3942 if (ret == 16)
3943 chip->options |= NAND_BUSWIDTH_16;
3944
3945 if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt"))
3946 chip->bbt_options |= NAND_BBT_USE_FLASH;
3947
3948 str = fdt_getprop(blob, node, "nand-ecc-mode", NULL);
3949 if (str) {
3950 if (!strcmp(str, "none"))
3951 ecc_mode = NAND_ECC_NONE;
3952 else if (!strcmp(str, "soft"))
3953 ecc_mode = NAND_ECC_SOFT;
3954 else if (!strcmp(str, "hw"))
3955 ecc_mode = NAND_ECC_HW;
3956 else if (!strcmp(str, "hw_syndrome"))
3957 ecc_mode = NAND_ECC_HW_SYNDROME;
3958 else if (!strcmp(str, "hw_oob_first"))
3959 ecc_mode = NAND_ECC_HW_OOB_FIRST;
3960 else if (!strcmp(str, "soft_bch"))
3961 ecc_mode = NAND_ECC_SOFT_BCH;
3962 }
3963
3964
3965 ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1);
3966 ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1);
3967
3968 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
3969 (!(ecc_step >= 0) && ecc_strength >= 0)) {
3970 pr_err("must set both strength and step size in DT\n");
3971 return -EINVAL;
3972 }
3973
3974 if (ecc_mode >= 0)
3975 chip->ecc.mode = ecc_mode;
3976
3977 if (ecc_strength >= 0)
3978 chip->ecc.strength = ecc_strength;
3979
3980 if (ecc_step > 0)
3981 chip->ecc.size = ecc_step;
3982
3983 if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL))
3984 chip->ecc.options |= NAND_ECC_MAXIMIZE;
3985
3986 return 0;
3987 }
3988 #else
nand_dt_init(struct mtd_info * mtd,struct nand_chip * chip,int node)3989 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
3990 {
3991 return 0;
3992 }
3993 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
3994
3995 /**
3996 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3997 * @mtd: MTD device structure
3998 * @maxchips: number of chips to scan for
3999 * @table: alternative NAND ID table
4000 *
4001 * This is the first phase of the normal nand_scan() function. It reads the
4002 * flash ID and sets up MTD fields accordingly.
4003 *
4004 */
nand_scan_ident(struct mtd_info * mtd,int maxchips,struct nand_flash_dev * table)4005 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4006 struct nand_flash_dev *table)
4007 {
4008 int i, nand_maf_id, nand_dev_id;
4009 struct nand_chip *chip = mtd_to_nand(mtd);
4010 struct nand_flash_dev *type;
4011 int ret;
4012
4013 if (chip->flash_node) {
4014 ret = nand_dt_init(mtd, chip, chip->flash_node);
4015 if (ret)
4016 return ret;
4017 }
4018
4019 /* Set the default functions */
4020 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
4021
4022 /* Read the flash type */
4023 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4024 &nand_dev_id, table);
4025
4026 if (IS_ERR(type)) {
4027 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
4028 pr_warn("No NAND device found\n");
4029 chip->select_chip(mtd, -1);
4030 return PTR_ERR(type);
4031 }
4032
4033 /* Initialize the ->data_interface field. */
4034 ret = nand_init_data_interface(chip);
4035 if (ret)
4036 return ret;
4037
4038 /*
4039 * Setup the data interface correctly on the chip and controller side.
4040 * This explicit call to nand_setup_data_interface() is only required
4041 * for the first die, because nand_reset() has been called before
4042 * ->data_interface and ->default_onfi_timing_mode were set.
4043 * For the other dies, nand_reset() will automatically switch to the
4044 * best mode for us.
4045 */
4046 ret = nand_setup_data_interface(chip, 0);
4047 if (ret)
4048 return ret;
4049
4050 chip->select_chip(mtd, -1);
4051
4052 /* Check for a chip array */
4053 for (i = 1; i < maxchips; i++) {
4054 /* See comment in nand_get_flash_type for reset */
4055 nand_reset(chip, i);
4056
4057 chip->select_chip(mtd, i);
4058 /* Send the command for reading device ID */
4059 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4060 /* Read manufacturer and device IDs */
4061 if (nand_maf_id != chip->read_byte(mtd) ||
4062 nand_dev_id != chip->read_byte(mtd)) {
4063 chip->select_chip(mtd, -1);
4064 break;
4065 }
4066 chip->select_chip(mtd, -1);
4067 }
4068
4069 #ifdef DEBUG
4070 if (i > 1)
4071 pr_info("%d chips detected\n", i);
4072 #endif
4073
4074 /* Store the number of chips and calc total size for mtd */
4075 chip->numchips = i;
4076 mtd->size = i * chip->chipsize;
4077
4078 return 0;
4079 }
4080 EXPORT_SYMBOL(nand_scan_ident);
4081
4082 /**
4083 * nand_check_ecc_caps - check the sanity of preset ECC settings
4084 * @chip: nand chip info structure
4085 * @caps: ECC caps info structure
4086 * @oobavail: OOB size that the ECC engine can use
4087 *
4088 * When ECC step size and strength are already set, check if they are supported
4089 * by the controller and the calculated ECC bytes fit within the chip's OOB.
4090 * On success, the calculated ECC bytes is set.
4091 */
nand_check_ecc_caps(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)4092 int nand_check_ecc_caps(struct nand_chip *chip,
4093 const struct nand_ecc_caps *caps, int oobavail)
4094 {
4095 struct mtd_info *mtd = nand_to_mtd(chip);
4096 const struct nand_ecc_step_info *stepinfo;
4097 int preset_step = chip->ecc.size;
4098 int preset_strength = chip->ecc.strength;
4099 int nsteps, ecc_bytes;
4100 int i, j;
4101
4102 if (WARN_ON(oobavail < 0))
4103 return -EINVAL;
4104
4105 if (!preset_step || !preset_strength)
4106 return -ENODATA;
4107
4108 nsteps = mtd->writesize / preset_step;
4109
4110 for (i = 0; i < caps->nstepinfos; i++) {
4111 stepinfo = &caps->stepinfos[i];
4112
4113 if (stepinfo->stepsize != preset_step)
4114 continue;
4115
4116 for (j = 0; j < stepinfo->nstrengths; j++) {
4117 if (stepinfo->strengths[j] != preset_strength)
4118 continue;
4119
4120 ecc_bytes = caps->calc_ecc_bytes(preset_step,
4121 preset_strength);
4122 if (WARN_ON_ONCE(ecc_bytes < 0))
4123 return ecc_bytes;
4124
4125 if (ecc_bytes * nsteps > oobavail) {
4126 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4127 preset_step, preset_strength);
4128 return -ENOSPC;
4129 }
4130
4131 chip->ecc.bytes = ecc_bytes;
4132
4133 return 0;
4134 }
4135 }
4136
4137 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4138 preset_step, preset_strength);
4139
4140 return -ENOTSUPP;
4141 }
4142 EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
4143
4144 /**
4145 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
4146 * @chip: nand chip info structure
4147 * @caps: ECC engine caps info structure
4148 * @oobavail: OOB size that the ECC engine can use
4149 *
4150 * If a chip's ECC requirement is provided, try to meet it with the least
4151 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
4152 * On success, the chosen ECC settings are set.
4153 */
nand_match_ecc_req(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)4154 int nand_match_ecc_req(struct nand_chip *chip,
4155 const struct nand_ecc_caps *caps, int oobavail)
4156 {
4157 struct mtd_info *mtd = nand_to_mtd(chip);
4158 const struct nand_ecc_step_info *stepinfo;
4159 int req_step = chip->ecc_step_ds;
4160 int req_strength = chip->ecc_strength_ds;
4161 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
4162 int best_step, best_strength, best_ecc_bytes;
4163 int best_ecc_bytes_total = INT_MAX;
4164 int i, j;
4165
4166 if (WARN_ON(oobavail < 0))
4167 return -EINVAL;
4168
4169 /* No information provided by the NAND chip */
4170 if (!req_step || !req_strength)
4171 return -ENOTSUPP;
4172
4173 /* number of correctable bits the chip requires in a page */
4174 req_corr = mtd->writesize / req_step * req_strength;
4175
4176 for (i = 0; i < caps->nstepinfos; i++) {
4177 stepinfo = &caps->stepinfos[i];
4178 step_size = stepinfo->stepsize;
4179
4180 for (j = 0; j < stepinfo->nstrengths; j++) {
4181 strength = stepinfo->strengths[j];
4182
4183 /*
4184 * If both step size and strength are smaller than the
4185 * chip's requirement, it is not easy to compare the
4186 * resulted reliability.
4187 */
4188 if (step_size < req_step && strength < req_strength)
4189 continue;
4190
4191 if (mtd->writesize % step_size)
4192 continue;
4193
4194 nsteps = mtd->writesize / step_size;
4195
4196 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4197 if (WARN_ON_ONCE(ecc_bytes < 0))
4198 continue;
4199 ecc_bytes_total = ecc_bytes * nsteps;
4200
4201 if (ecc_bytes_total > oobavail ||
4202 strength * nsteps < req_corr)
4203 continue;
4204
4205 /*
4206 * We assume the best is to meet the chip's requrement
4207 * with the least number of ECC bytes.
4208 */
4209 if (ecc_bytes_total < best_ecc_bytes_total) {
4210 best_ecc_bytes_total = ecc_bytes_total;
4211 best_step = step_size;
4212 best_strength = strength;
4213 best_ecc_bytes = ecc_bytes;
4214 }
4215 }
4216 }
4217
4218 if (best_ecc_bytes_total == INT_MAX)
4219 return -ENOTSUPP;
4220
4221 chip->ecc.size = best_step;
4222 chip->ecc.strength = best_strength;
4223 chip->ecc.bytes = best_ecc_bytes;
4224
4225 return 0;
4226 }
4227 EXPORT_SYMBOL_GPL(nand_match_ecc_req);
4228
4229 /**
4230 * nand_maximize_ecc - choose the max ECC strength available
4231 * @chip: nand chip info structure
4232 * @caps: ECC engine caps info structure
4233 * @oobavail: OOB size that the ECC engine can use
4234 *
4235 * Choose the max ECC strength that is supported on the controller, and can fit
4236 * within the chip's OOB. On success, the chosen ECC settings are set.
4237 */
nand_maximize_ecc(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)4238 int nand_maximize_ecc(struct nand_chip *chip,
4239 const struct nand_ecc_caps *caps, int oobavail)
4240 {
4241 struct mtd_info *mtd = nand_to_mtd(chip);
4242 const struct nand_ecc_step_info *stepinfo;
4243 int step_size, strength, nsteps, ecc_bytes, corr;
4244 int best_corr = 0;
4245 int best_step = 0;
4246 int best_strength, best_ecc_bytes;
4247 int i, j;
4248
4249 if (WARN_ON(oobavail < 0))
4250 return -EINVAL;
4251
4252 for (i = 0; i < caps->nstepinfos; i++) {
4253 stepinfo = &caps->stepinfos[i];
4254 step_size = stepinfo->stepsize;
4255
4256 /* If chip->ecc.size is already set, respect it */
4257 if (chip->ecc.size && step_size != chip->ecc.size)
4258 continue;
4259
4260 for (j = 0; j < stepinfo->nstrengths; j++) {
4261 strength = stepinfo->strengths[j];
4262
4263 if (mtd->writesize % step_size)
4264 continue;
4265
4266 nsteps = mtd->writesize / step_size;
4267
4268 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4269 if (WARN_ON_ONCE(ecc_bytes < 0))
4270 continue;
4271
4272 if (ecc_bytes * nsteps > oobavail)
4273 continue;
4274
4275 corr = strength * nsteps;
4276
4277 /*
4278 * If the number of correctable bits is the same,
4279 * bigger step_size has more reliability.
4280 */
4281 if (corr > best_corr ||
4282 (corr == best_corr && step_size > best_step)) {
4283 best_corr = corr;
4284 best_step = step_size;
4285 best_strength = strength;
4286 best_ecc_bytes = ecc_bytes;
4287 }
4288 }
4289 }
4290
4291 if (!best_corr)
4292 return -ENOTSUPP;
4293
4294 chip->ecc.size = best_step;
4295 chip->ecc.strength = best_strength;
4296 chip->ecc.bytes = best_ecc_bytes;
4297
4298 return 0;
4299 }
4300 EXPORT_SYMBOL_GPL(nand_maximize_ecc);
4301
4302 /*
4303 * Check if the chip configuration meet the datasheet requirements.
4304
4305 * If our configuration corrects A bits per B bytes and the minimum
4306 * required correction level is X bits per Y bytes, then we must ensure
4307 * both of the following are true:
4308 *
4309 * (1) A / B >= X / Y
4310 * (2) A >= X
4311 *
4312 * Requirement (1) ensures we can correct for the required bitflip density.
4313 * Requirement (2) ensures we can correct even when all bitflips are clumped
4314 * in the same sector.
4315 */
nand_ecc_strength_good(struct mtd_info * mtd)4316 static bool nand_ecc_strength_good(struct mtd_info *mtd)
4317 {
4318 struct nand_chip *chip = mtd_to_nand(mtd);
4319 struct nand_ecc_ctrl *ecc = &chip->ecc;
4320 int corr, ds_corr;
4321
4322 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4323 /* Not enough information */
4324 return true;
4325
4326 /*
4327 * We get the number of corrected bits per page to compare
4328 * the correction density.
4329 */
4330 corr = (mtd->writesize * ecc->strength) / ecc->size;
4331 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4332
4333 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4334 }
4335
invalid_ecc_page_accessors(struct nand_chip * chip)4336 static bool invalid_ecc_page_accessors(struct nand_chip *chip)
4337 {
4338 struct nand_ecc_ctrl *ecc = &chip->ecc;
4339
4340 if (nand_standard_page_accessors(ecc))
4341 return false;
4342
4343 /*
4344 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4345 * controller driver implements all the page accessors because
4346 * default helpers are not suitable when the core does not
4347 * send the READ0/PAGEPROG commands.
4348 */
4349 return (!ecc->read_page || !ecc->write_page ||
4350 !ecc->read_page_raw || !ecc->write_page_raw ||
4351 (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
4352 (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
4353 ecc->hwctl && ecc->calculate));
4354 }
4355
4356 /**
4357 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4358 * @mtd: MTD device structure
4359 *
4360 * This is the second phase of the normal nand_scan() function. It fills out
4361 * all the uninitialized function pointers with the defaults and scans for a
4362 * bad block table if appropriate.
4363 */
nand_scan_tail(struct mtd_info * mtd)4364 int nand_scan_tail(struct mtd_info *mtd)
4365 {
4366 int i;
4367 struct nand_chip *chip = mtd_to_nand(mtd);
4368 struct nand_ecc_ctrl *ecc = &chip->ecc;
4369 struct nand_buffers *nbuf;
4370
4371 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4372 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4373 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4374
4375 if (invalid_ecc_page_accessors(chip)) {
4376 pr_err("Invalid ECC page accessors setup\n");
4377 return -EINVAL;
4378 }
4379
4380 if (!(chip->options & NAND_OWN_BUFFERS)) {
4381 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4382 chip->buffers = nbuf;
4383 } else {
4384 if (!chip->buffers)
4385 return -ENOMEM;
4386 }
4387
4388 /* Set the internal oob buffer location, just after the page data */
4389 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4390
4391 /*
4392 * If no default placement scheme is given, select an appropriate one.
4393 */
4394 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4395 switch (mtd->oobsize) {
4396 case 8:
4397 ecc->layout = &nand_oob_8;
4398 break;
4399 case 16:
4400 ecc->layout = &nand_oob_16;
4401 break;
4402 case 64:
4403 ecc->layout = &nand_oob_64;
4404 break;
4405 case 128:
4406 ecc->layout = &nand_oob_128;
4407 break;
4408 default:
4409 pr_warn("No oob scheme defined for oobsize %d\n",
4410 mtd->oobsize);
4411 BUG();
4412 }
4413 }
4414
4415 if (!chip->write_page)
4416 chip->write_page = nand_write_page;
4417
4418 /*
4419 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4420 * selected and we have 256 byte pagesize fallback to software ECC
4421 */
4422
4423 switch (ecc->mode) {
4424 case NAND_ECC_HW_OOB_FIRST:
4425 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4426 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4427 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4428 BUG();
4429 }
4430 if (!ecc->read_page)
4431 ecc->read_page = nand_read_page_hwecc_oob_first;
4432
4433 case NAND_ECC_HW:
4434 /* Use standard hwecc read page function? */
4435 if (!ecc->read_page)
4436 ecc->read_page = nand_read_page_hwecc;
4437 if (!ecc->write_page)
4438 ecc->write_page = nand_write_page_hwecc;
4439 if (!ecc->read_page_raw)
4440 ecc->read_page_raw = nand_read_page_raw;
4441 if (!ecc->write_page_raw)
4442 ecc->write_page_raw = nand_write_page_raw;
4443 if (!ecc->read_oob)
4444 ecc->read_oob = nand_read_oob_std;
4445 if (!ecc->write_oob)
4446 ecc->write_oob = nand_write_oob_std;
4447 if (!ecc->read_subpage)
4448 ecc->read_subpage = nand_read_subpage;
4449 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
4450 ecc->write_subpage = nand_write_subpage_hwecc;
4451
4452 case NAND_ECC_HW_SYNDROME:
4453 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4454 (!ecc->read_page ||
4455 ecc->read_page == nand_read_page_hwecc ||
4456 !ecc->write_page ||
4457 ecc->write_page == nand_write_page_hwecc)) {
4458 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4459 BUG();
4460 }
4461 /* Use standard syndrome read/write page function? */
4462 if (!ecc->read_page)
4463 ecc->read_page = nand_read_page_syndrome;
4464 if (!ecc->write_page)
4465 ecc->write_page = nand_write_page_syndrome;
4466 if (!ecc->read_page_raw)
4467 ecc->read_page_raw = nand_read_page_raw_syndrome;
4468 if (!ecc->write_page_raw)
4469 ecc->write_page_raw = nand_write_page_raw_syndrome;
4470 if (!ecc->read_oob)
4471 ecc->read_oob = nand_read_oob_syndrome;
4472 if (!ecc->write_oob)
4473 ecc->write_oob = nand_write_oob_syndrome;
4474
4475 if (mtd->writesize >= ecc->size) {
4476 if (!ecc->strength) {
4477 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4478 BUG();
4479 }
4480 break;
4481 }
4482 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4483 ecc->size, mtd->writesize);
4484 ecc->mode = NAND_ECC_SOFT;
4485
4486 case NAND_ECC_SOFT:
4487 ecc->calculate = nand_calculate_ecc;
4488 ecc->correct = nand_correct_data;
4489 ecc->read_page = nand_read_page_swecc;
4490 ecc->read_subpage = nand_read_subpage;
4491 ecc->write_page = nand_write_page_swecc;
4492 ecc->read_page_raw = nand_read_page_raw;
4493 ecc->write_page_raw = nand_write_page_raw;
4494 ecc->read_oob = nand_read_oob_std;
4495 ecc->write_oob = nand_write_oob_std;
4496 if (!ecc->size)
4497 ecc->size = 256;
4498 ecc->bytes = 3;
4499 ecc->strength = 1;
4500 break;
4501
4502 case NAND_ECC_SOFT_BCH:
4503 if (!mtd_nand_has_bch()) {
4504 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4505 BUG();
4506 }
4507 ecc->calculate = nand_bch_calculate_ecc;
4508 ecc->correct = nand_bch_correct_data;
4509 ecc->read_page = nand_read_page_swecc;
4510 ecc->read_subpage = nand_read_subpage;
4511 ecc->write_page = nand_write_page_swecc;
4512 ecc->read_page_raw = nand_read_page_raw;
4513 ecc->write_page_raw = nand_write_page_raw;
4514 ecc->read_oob = nand_read_oob_std;
4515 ecc->write_oob = nand_write_oob_std;
4516 /*
4517 * Board driver should supply ecc.size and ecc.strength values
4518 * to select how many bits are correctable. Otherwise, default
4519 * to 4 bits for large page devices.
4520 */
4521 if (!ecc->size && (mtd->oobsize >= 64)) {
4522 ecc->size = 512;
4523 ecc->strength = 4;
4524 }
4525
4526 /* See nand_bch_init() for details. */
4527 ecc->bytes = 0;
4528 ecc->priv = nand_bch_init(mtd);
4529 if (!ecc->priv) {
4530 pr_warn("BCH ECC initialization failed!\n");
4531 BUG();
4532 }
4533 break;
4534
4535 case NAND_ECC_NONE:
4536 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4537 ecc->read_page = nand_read_page_raw;
4538 ecc->write_page = nand_write_page_raw;
4539 ecc->read_oob = nand_read_oob_std;
4540 ecc->read_page_raw = nand_read_page_raw;
4541 ecc->write_page_raw = nand_write_page_raw;
4542 ecc->write_oob = nand_write_oob_std;
4543 ecc->size = mtd->writesize;
4544 ecc->bytes = 0;
4545 ecc->strength = 0;
4546 break;
4547
4548 default:
4549 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4550 BUG();
4551 }
4552
4553 /* For many systems, the standard OOB write also works for raw */
4554 if (!ecc->read_oob_raw)
4555 ecc->read_oob_raw = ecc->read_oob;
4556 if (!ecc->write_oob_raw)
4557 ecc->write_oob_raw = ecc->write_oob;
4558
4559 /*
4560 * The number of bytes available for a client to place data into
4561 * the out of band area.
4562 */
4563 mtd->oobavail = 0;
4564 if (ecc->layout) {
4565 for (i = 0; ecc->layout->oobfree[i].length; i++)
4566 mtd->oobavail += ecc->layout->oobfree[i].length;
4567 }
4568
4569 /* ECC sanity check: warn if it's too weak */
4570 if (!nand_ecc_strength_good(mtd))
4571 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4572 mtd->name);
4573
4574 /*
4575 * Set the number of read / write steps for one page depending on ECC
4576 * mode.
4577 */
4578 ecc->steps = mtd->writesize / ecc->size;
4579 if (ecc->steps * ecc->size != mtd->writesize) {
4580 pr_warn("Invalid ECC parameters\n");
4581 BUG();
4582 }
4583 ecc->total = ecc->steps * ecc->bytes;
4584
4585 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4586 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4587 switch (ecc->steps) {
4588 case 2:
4589 mtd->subpage_sft = 1;
4590 break;
4591 case 4:
4592 case 8:
4593 case 16:
4594 mtd->subpage_sft = 2;
4595 break;
4596 }
4597 }
4598 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4599
4600 /* Initialize state */
4601 chip->state = FL_READY;
4602
4603 /* Invalidate the pagebuffer reference */
4604 chip->pagebuf = -1;
4605
4606 /* Large page NAND with SOFT_ECC should support subpage reads */
4607 switch (ecc->mode) {
4608 case NAND_ECC_SOFT:
4609 case NAND_ECC_SOFT_BCH:
4610 if (chip->page_shift > 9)
4611 chip->options |= NAND_SUBPAGE_READ;
4612 break;
4613
4614 default:
4615 break;
4616 }
4617
4618 /* Fill in remaining MTD driver data */
4619 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4620 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4621 MTD_CAP_NANDFLASH;
4622 mtd->_erase = nand_erase;
4623 mtd->_read = nand_read;
4624 mtd->_write = nand_write;
4625 mtd->_panic_write = panic_nand_write;
4626 mtd->_read_oob = nand_read_oob;
4627 mtd->_write_oob = nand_write_oob;
4628 mtd->_sync = nand_sync;
4629 mtd->_lock = NULL;
4630 mtd->_unlock = NULL;
4631 mtd->_block_isreserved = nand_block_isreserved;
4632 mtd->_block_isbad = nand_block_isbad;
4633 mtd->_block_markbad = nand_block_markbad;
4634 mtd->writebufsize = mtd->writesize;
4635
4636 /* propagate ecc info to mtd_info */
4637 mtd->ecclayout = ecc->layout;
4638 mtd->ecc_strength = ecc->strength;
4639 mtd->ecc_step_size = ecc->size;
4640 /*
4641 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4642 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4643 * properly set.
4644 */
4645 if (!mtd->bitflip_threshold)
4646 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4647
4648 return 0;
4649 }
4650 EXPORT_SYMBOL(nand_scan_tail);
4651
4652 /**
4653 * nand_scan - [NAND Interface] Scan for the NAND device
4654 * @mtd: MTD device structure
4655 * @maxchips: number of chips to scan for
4656 *
4657 * This fills out all the uninitialized function pointers with the defaults.
4658 * The flash ID is read and the mtd/chip structures are filled with the
4659 * appropriate values.
4660 */
nand_scan(struct mtd_info * mtd,int maxchips)4661 int nand_scan(struct mtd_info *mtd, int maxchips)
4662 {
4663 int ret;
4664
4665 ret = nand_scan_ident(mtd, maxchips, NULL);
4666 if (!ret)
4667 ret = nand_scan_tail(mtd);
4668 return ret;
4669 }
4670 EXPORT_SYMBOL(nand_scan);
4671
4672 MODULE_LICENSE("GPL");
4673 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4674 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4675 MODULE_DESCRIPTION("Generic NAND flash driver code");
4676