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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2012 Samsung Electronics
4  *
5  * Author: InKi Dae <inki.dae@samsung.com>
6  * Author: Donghwa Lee <dh09.lee@samsung.com>
7  */
8 
9 #include <common.h>
10 #include <lcd.h>
11 #include <linux/err.h>
12 #include <asm/arch/dsim.h>
13 #include <asm/arch/mipi_dsim.h>
14 
15 #include "exynos_mipi_dsi_lowlevel.h"
16 
17 #define MHZ			(1000 * 1000)
18 #define FIN_HZ			(24 * MHZ)
19 
20 #define DFIN_PLL_MIN_HZ		(6 * MHZ)
21 #define DFIN_PLL_MAX_HZ		(12 * MHZ)
22 
23 #define DFVCO_MIN_HZ		(500 * MHZ)
24 #define DFVCO_MAX_HZ		(1000 * MHZ)
25 
26 #define TRY_GET_FIFO_TIMEOUT	(5000 * 2)
27 
28 /* MIPI-DSIM status types. */
29 enum {
30 	DSIM_STATE_INIT,	/* should be initialized. */
31 	DSIM_STATE_STOP,	/* CPU and LCDC are LP mode. */
32 	DSIM_STATE_HSCLKEN,	/* HS clock was enabled. */
33 	DSIM_STATE_ULPS
34 };
35 
36 /* define DSI lane types. */
37 enum {
38 	DSIM_LANE_CLOCK = (1 << 0),
39 	DSIM_LANE_DATA0 = (1 << 1),
40 	DSIM_LANE_DATA1 = (1 << 2),
41 	DSIM_LANE_DATA2 = (1 << 3),
42 	DSIM_LANE_DATA3 = (1 << 4)
43 };
44 
45 static unsigned int dpll_table[15] = {
46 	100, 120, 170, 220, 270,
47 	320, 390, 450, 510, 560,
48 	640, 690, 770, 870, 950
49 };
50 
exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device * dsim,const unsigned char * data0,unsigned int data1)51 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
52 		const unsigned char *data0, unsigned int data1)
53 {
54 	unsigned int data_cnt = 0, payload = 0;
55 
56 	/* in case that data count is more then 4 */
57 	for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
58 		/*
59 		 * after sending 4bytes per one time,
60 		 * send remainder data less then 4.
61 		 */
62 		if ((data1 - data_cnt) < 4) {
63 			if ((data1 - data_cnt) == 3) {
64 				payload = data0[data_cnt] |
65 					data0[data_cnt + 1] << 8 |
66 					data0[data_cnt + 2] << 16;
67 			debug("count = 3 payload = %x, %x %x %x\n",
68 				payload, data0[data_cnt],
69 				data0[data_cnt + 1],
70 				data0[data_cnt + 2]);
71 			} else if ((data1 - data_cnt) == 2) {
72 				payload = data0[data_cnt] |
73 					data0[data_cnt + 1] << 8;
74 			debug("count = 2 payload = %x, %x %x\n", payload,
75 				data0[data_cnt], data0[data_cnt + 1]);
76 			} else if ((data1 - data_cnt) == 1) {
77 				payload = data0[data_cnt];
78 			}
79 		} else {
80 			/* send 4bytes per one time. */
81 			payload = data0[data_cnt] |
82 				data0[data_cnt + 1] << 8 |
83 				data0[data_cnt + 2] << 16 |
84 				data0[data_cnt + 3] << 24;
85 
86 			debug("count = 4 payload = %x, %x %x %x %x\n",
87 				payload, *(u8 *)(data0 + data_cnt),
88 				data0[data_cnt + 1],
89 				data0[data_cnt + 2],
90 				data0[data_cnt + 3]);
91 		}
92 		exynos_mipi_dsi_wr_tx_data(dsim, payload);
93 	}
94 }
95 
exynos_mipi_dsi_wr_data(struct mipi_dsim_device * dsim,unsigned int data_id,const unsigned char * data0,unsigned int data1)96 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
97 	const unsigned char *data0, unsigned int data1)
98 {
99 	unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
100 	unsigned long delay_val, delay;
101 	unsigned int check_rx_ack = 0;
102 
103 	if (dsim->state == DSIM_STATE_ULPS) {
104 		debug("state is ULPS.\n");
105 
106 		return -EINVAL;
107 	}
108 
109 	delay_val = MHZ / dsim->dsim_config->esc_clk;
110 	delay = 10 * delay_val;
111 
112 	mdelay(delay);
113 
114 	/* only if transfer mode is LPDT, wait SFR becomes empty. */
115 	if (dsim->state == DSIM_STATE_STOP) {
116 		while (!(exynos_mipi_dsi_get_fifo_state(dsim) &
117 				SFR_HEADER_EMPTY)) {
118 			if ((timeout--) > 0)
119 				mdelay(1);
120 			else {
121 				debug("SRF header fifo is not empty.\n");
122 				return -EINVAL;
123 			}
124 		}
125 	}
126 
127 	switch (data_id) {
128 	/* short packet types of packet types for command. */
129 	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
130 	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
131 	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
132 	case MIPI_DSI_DCS_SHORT_WRITE:
133 	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
134 	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
135 		debug("data0 = %x data1 = %x\n",
136 				data0[0], data0[1]);
137 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
138 		if (check_rx_ack) {
139 			/* process response func should be implemented */
140 			return 0;
141 		} else {
142 			return -EINVAL;
143 		}
144 
145 	/* general command */
146 	case MIPI_DSI_COLOR_MODE_OFF:
147 	case MIPI_DSI_COLOR_MODE_ON:
148 	case MIPI_DSI_SHUTDOWN_PERIPHERAL:
149 	case MIPI_DSI_TURN_ON_PERIPHERAL:
150 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
151 		if (check_rx_ack) {
152 			/* process response func should be implemented. */
153 			return 0;
154 		} else {
155 			return -EINVAL;
156 		}
157 
158 	/* packet types for video data */
159 	case MIPI_DSI_V_SYNC_START:
160 	case MIPI_DSI_V_SYNC_END:
161 	case MIPI_DSI_H_SYNC_START:
162 	case MIPI_DSI_H_SYNC_END:
163 	case MIPI_DSI_END_OF_TRANSMISSION:
164 		return 0;
165 
166 	/* short and response packet types for command */
167 	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
168 	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
169 	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
170 	case MIPI_DSI_DCS_READ:
171 		exynos_mipi_dsi_clear_all_interrupt(dsim);
172 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
173 		/* process response func should be implemented. */
174 		return 0;
175 
176 	/* long packet type and null packet */
177 	case MIPI_DSI_NULL_PACKET:
178 	case MIPI_DSI_BLANKING_PACKET:
179 		return 0;
180 	case MIPI_DSI_GENERIC_LONG_WRITE:
181 	case MIPI_DSI_DCS_LONG_WRITE:
182 	{
183 		unsigned int payload = 0;
184 
185 		/* if data count is less then 4, then send 3bytes data.  */
186 		if (data1 < 4) {
187 			payload = data0[0] |
188 				data0[1] << 8 |
189 				data0[2] << 16;
190 
191 			exynos_mipi_dsi_wr_tx_data(dsim, payload);
192 
193 			debug("count = %d payload = %x,%x %x %x\n",
194 				data1, payload, data0[0],
195 				data0[1], data0[2]);
196 		} else {
197 			/* in case that data count is more then 4 */
198 			exynos_mipi_dsi_long_data_wr(dsim, data0, data1);
199 		}
200 
201 		/* put data into header fifo */
202 		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,
203 			(data1 & 0xff00) >> 8);
204 
205 	}
206 	if (check_rx_ack)
207 		/* process response func should be implemented. */
208 		return 0;
209 	else
210 		return -EINVAL;
211 
212 	/* packet typo for video data */
213 	case MIPI_DSI_PACKED_PIXEL_STREAM_16:
214 	case MIPI_DSI_PACKED_PIXEL_STREAM_18:
215 	case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
216 	case MIPI_DSI_PACKED_PIXEL_STREAM_24:
217 		if (check_rx_ack) {
218 			/* process response func should be implemented. */
219 			return 0;
220 		} else {
221 			return -EINVAL;
222 		}
223 	default:
224 		debug("data id %x is not supported current DSI spec.\n",
225 			data_id);
226 
227 		return -EINVAL;
228 	}
229 
230 	return 0;
231 }
232 
exynos_mipi_dsi_pll_on(struct mipi_dsim_device * dsim,unsigned int enable)233 int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)
234 {
235 	int sw_timeout;
236 
237 	if (enable) {
238 		sw_timeout = 1000;
239 
240 		exynos_mipi_dsi_clear_interrupt(dsim);
241 		exynos_mipi_dsi_enable_pll(dsim, 1);
242 		while (1) {
243 			sw_timeout--;
244 			if (exynos_mipi_dsi_is_pll_stable(dsim))
245 				return 0;
246 			if (sw_timeout == 0)
247 				return -EINVAL;
248 		}
249 	} else
250 		exynos_mipi_dsi_enable_pll(dsim, 0);
251 
252 	return 0;
253 }
254 
exynos_mipi_dsi_change_pll(struct mipi_dsim_device * dsim,unsigned int pre_divider,unsigned int main_divider,unsigned int scaler)255 unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
256 	unsigned int pre_divider, unsigned int main_divider,
257 	unsigned int scaler)
258 {
259 	unsigned long dfin_pll, dfvco, dpll_out;
260 	unsigned int i, freq_band = 0xf;
261 
262 	dfin_pll = (FIN_HZ / pre_divider);
263 
264 	/******************************************************
265 	 *	Serial Clock(=ByteClk X 8)	FreqBand[3:0] *
266 	 ******************************************************
267 	 *	~ 99.99 MHz			0000
268 	 *	100 ~ 119.99 MHz		0001
269 	 *	120 ~ 159.99 MHz		0010
270 	 *	160 ~ 199.99 MHz		0011
271 	 *	200 ~ 239.99 MHz		0100
272 	 *	140 ~ 319.99 MHz		0101
273 	 *	320 ~ 389.99 MHz		0110
274 	 *	390 ~ 449.99 MHz		0111
275 	 *	450 ~ 509.99 MHz		1000
276 	 *	510 ~ 559.99 MHz		1001
277 	 *	560 ~ 639.99 MHz		1010
278 	 *	640 ~ 689.99 MHz		1011
279 	 *	690 ~ 769.99 MHz		1100
280 	 *	770 ~ 869.99 MHz		1101
281 	 *	870 ~ 949.99 MHz		1110
282 	 *	950 ~ 1000 MHz			1111
283 	 ******************************************************/
284 	if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
285 		debug("fin_pll range should be 6MHz ~ 12MHz\n");
286 		exynos_mipi_dsi_enable_afc(dsim, 0, 0);
287 	} else {
288 		if (dfin_pll < 7 * MHZ)
289 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
290 		else if (dfin_pll < 8 * MHZ)
291 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
292 		else if (dfin_pll < 9 * MHZ)
293 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
294 		else if (dfin_pll < 10 * MHZ)
295 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
296 		else if (dfin_pll < 11 * MHZ)
297 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
298 		else
299 			exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
300 	}
301 
302 	dfvco = dfin_pll * main_divider;
303 	debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
304 				dfvco, dfin_pll, main_divider);
305 	if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
306 		debug("fvco range should be 500MHz ~ 1000MHz\n");
307 
308 	dpll_out = dfvco / (1 << scaler);
309 	debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n",
310 		dpll_out, dfvco, scaler);
311 
312 	for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
313 		if (dpll_out < dpll_table[i] * MHZ) {
314 			freq_band = i;
315 			break;
316 		}
317 	}
318 
319 	debug("freq_band = %d\n", freq_band);
320 
321 	exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
322 
323 	exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
324 	exynos_mipi_dsi_prep_ctrl(dsim, 0);
325 
326 	/* Freq Band */
327 	exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
328 
329 	/* Stable time */
330 	exynos_mipi_dsi_pll_stable_time(dsim,
331 				dsim->dsim_config->pll_stable_time);
332 
333 	/* Enable PLL */
334 	debug("FOUT of mipi dphy pll is %luMHz\n",
335 		(dpll_out / MHZ));
336 
337 	return dpll_out;
338 }
339 
exynos_mipi_dsi_set_clock(struct mipi_dsim_device * dsim,unsigned int byte_clk_sel,unsigned int enable)340 int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
341 	unsigned int byte_clk_sel, unsigned int enable)
342 {
343 	unsigned int esc_div;
344 	unsigned long esc_clk_error_rate;
345 	unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
346 
347 	if (enable) {
348 		dsim->e_clk_src = byte_clk_sel;
349 
350 		/* Escape mode clock and byte clock source */
351 		exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
352 
353 		/* DPHY, DSIM Link : D-PHY clock out */
354 		if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
355 			hs_clk = exynos_mipi_dsi_change_pll(dsim,
356 				dsim->dsim_config->p, dsim->dsim_config->m,
357 				dsim->dsim_config->s);
358 			if (hs_clk == 0) {
359 				debug("failed to get hs clock.\n");
360 				return -EINVAL;
361 			}
362 
363 			byte_clk = hs_clk / 8;
364 			exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
365 			exynos_mipi_dsi_pll_on(dsim, 1);
366 		/* DPHY : D-PHY clock out, DSIM link : external clock out */
367 		} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
368 			debug("not support EXT CLK source for MIPI DSIM\n");
369 		else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
370 			debug("not support EXT CLK source for MIPI DSIM\n");
371 
372 		/* escape clock divider */
373 		esc_div = byte_clk / (dsim->dsim_config->esc_clk);
374 		debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
375 			esc_div, byte_clk, dsim->dsim_config->esc_clk);
376 		if ((byte_clk / esc_div) >= (20 * MHZ) ||
377 			(byte_clk / esc_div) > dsim->dsim_config->esc_clk)
378 			esc_div += 1;
379 
380 		escape_clk = byte_clk / esc_div;
381 		debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
382 			escape_clk, byte_clk, esc_div);
383 
384 		/* enable escape clock. */
385 		exynos_mipi_dsi_enable_byte_clock(dsim, 1);
386 
387 		/* enable byte clk and escape clock */
388 		exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
389 		/* escape clock on lane */
390 		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
391 			(DSIM_LANE_CLOCK | dsim->data_lane), 1);
392 
393 		debug("byte clock is %luMHz\n",
394 			(byte_clk / MHZ));
395 		debug("escape clock that user's need is %lu\n",
396 			(dsim->dsim_config->esc_clk / MHZ));
397 		debug("escape clock divider is %x\n", esc_div);
398 		debug("escape clock is %luMHz\n",
399 			((byte_clk / esc_div) / MHZ));
400 
401 		if ((byte_clk / esc_div) > escape_clk) {
402 			esc_clk_error_rate = escape_clk /
403 				(byte_clk / esc_div);
404 			debug("error rate is %lu over.\n",
405 				(esc_clk_error_rate / 100));
406 		} else if ((byte_clk / esc_div) < (escape_clk)) {
407 			esc_clk_error_rate = (byte_clk / esc_div) /
408 				escape_clk;
409 			debug("error rate is %lu under.\n",
410 				(esc_clk_error_rate / 100));
411 		}
412 	} else {
413 		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
414 			(DSIM_LANE_CLOCK | dsim->data_lane), 0);
415 		exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
416 
417 		/* disable escape clock. */
418 		exynos_mipi_dsi_enable_byte_clock(dsim, 0);
419 
420 		if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
421 			exynos_mipi_dsi_pll_on(dsim, 0);
422 	}
423 
424 	return 0;
425 }
426 
exynos_mipi_dsi_init_dsim(struct mipi_dsim_device * dsim)427 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
428 {
429 	dsim->state = DSIM_STATE_INIT;
430 
431 	switch (dsim->dsim_config->e_no_data_lane) {
432 	case DSIM_DATA_LANE_1:
433 		dsim->data_lane = DSIM_LANE_DATA0;
434 		break;
435 	case DSIM_DATA_LANE_2:
436 		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
437 		break;
438 	case DSIM_DATA_LANE_3:
439 		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
440 			DSIM_LANE_DATA2;
441 		break;
442 	case DSIM_DATA_LANE_4:
443 		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
444 			DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
445 		break;
446 	default:
447 		debug("data lane is invalid.\n");
448 		return -EINVAL;
449 	};
450 
451 	exynos_mipi_dsi_sw_reset(dsim);
452 	exynos_mipi_dsi_dp_dn_swap(dsim, 0);
453 
454 	return 0;
455 }
456 
exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device * dsim,unsigned int enable)457 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
458 	unsigned int enable)
459 {
460 	/* enable only frame done interrupt */
461 	exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
462 
463 	return 0;
464 }
465 
convert_to_fb_videomode(struct fb_videomode * mode1,struct vidinfo * mode2)466 static void convert_to_fb_videomode(struct fb_videomode *mode1,
467 				    struct vidinfo *mode2)
468 {
469 	mode1->xres = mode2->vl_width;
470 	mode1->yres = mode2->vl_height;
471 	mode1->upper_margin = mode2->vl_vfpd;
472 	mode1->lower_margin = mode2->vl_vbpd;
473 	mode1->left_margin = mode2->vl_hfpd;
474 	mode1->right_margin = mode2->vl_hbpd;
475 	mode1->vsync_len = mode2->vl_vspw;
476 	mode1->hsync_len = mode2->vl_hspw;
477 }
478 
exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device * dsim,struct mipi_dsim_config * dsim_config)479 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
480 	struct mipi_dsim_config *dsim_config)
481 {
482 	struct exynos_platform_mipi_dsim *dsim_pd;
483 	struct fb_videomode lcd_video;
484 	struct vidinfo *vid;
485 
486 	dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
487 	vid = (struct vidinfo *)dsim_pd->lcd_panel_info;
488 
489 	convert_to_fb_videomode(&lcd_video, vid);
490 
491 	/* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
492 	if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) {
493 		if (dsim->dsim_config->auto_vertical_cnt == 0) {
494 			exynos_mipi_dsi_set_main_disp_vporch(dsim,
495 				vid->vl_cmd_allow_len,
496 				lcd_video.upper_margin,
497 				lcd_video.lower_margin);
498 			exynos_mipi_dsi_set_main_disp_hporch(dsim,
499 				lcd_video.left_margin,
500 				lcd_video.right_margin);
501 			exynos_mipi_dsi_set_main_disp_sync_area(dsim,
502 				lcd_video.vsync_len,
503 				lcd_video.hsync_len);
504 		}
505 	}
506 
507 	exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres,
508 			lcd_video.yres);
509 
510 	exynos_mipi_dsi_display_config(dsim, dsim->dsim_config);
511 
512 	debug("lcd panel ==> width = %d, height = %d\n",
513 			lcd_video.xres, lcd_video.yres);
514 
515 	return 0;
516 }
517 
exynos_mipi_dsi_init_link(struct mipi_dsim_device * dsim)518 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
519 {
520 	unsigned int time_out = 100;
521 
522 	switch (dsim->state) {
523 	case DSIM_STATE_INIT:
524 		exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
525 
526 		/* dsi configuration */
527 		exynos_mipi_dsi_init_config(dsim);
528 		exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
529 		exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
530 
531 		/* set clock configuration */
532 		exynos_mipi_dsi_set_clock(dsim,
533 					dsim->dsim_config->e_byte_clk, 1);
534 
535 		/* check clock and data lane state are stop state */
536 		while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
537 			time_out--;
538 			if (time_out == 0) {
539 				debug("DSI Master is not stop state.\n");
540 				debug("Check initialization process\n");
541 
542 				return -EINVAL;
543 			}
544 		}
545 
546 		dsim->state = DSIM_STATE_STOP;
547 
548 		/* BTA sequence counters */
549 		exynos_mipi_dsi_set_stop_state_counter(dsim,
550 			dsim->dsim_config->stop_holding_cnt);
551 		exynos_mipi_dsi_set_bta_timeout(dsim,
552 			dsim->dsim_config->bta_timeout);
553 		exynos_mipi_dsi_set_lpdr_timeout(dsim,
554 			dsim->dsim_config->rx_timeout);
555 
556 		return 0;
557 	default:
558 		debug("DSI Master is already init.\n");
559 		return 0;
560 	}
561 
562 	return 0;
563 }
564 
exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device * dsim)565 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
566 {
567 	if (dsim->state == DSIM_STATE_STOP) {
568 		if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
569 			dsim->state = DSIM_STATE_HSCLKEN;
570 
571 			 /* set LCDC and CPU transfer mode to HS. */
572 			exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
573 			exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
574 
575 			exynos_mipi_dsi_enable_hs_clock(dsim, 1);
576 
577 			return 0;
578 		} else
579 			debug("clock source is external bypass.\n");
580 	} else
581 		debug("DSIM is not stop state.\n");
582 
583 	return 0;
584 }
585 
exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device * dsim,unsigned int mode)586 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
587 		unsigned int mode)
588 {
589 	if (mode) {
590 		if (dsim->state != DSIM_STATE_HSCLKEN) {
591 			debug("HS Clock lane is not enabled.\n");
592 			return -EINVAL;
593 		}
594 
595 		exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
596 	} else {
597 		if (dsim->state == DSIM_STATE_INIT || dsim->state ==
598 			DSIM_STATE_ULPS) {
599 			debug("DSI Master is not STOP or HSDT state.\n");
600 			return -EINVAL;
601 		}
602 
603 		exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
604 	}
605 
606 	return 0;
607 }
608 
exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device * dsim)609 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
610 {
611 	return _exynos_mipi_dsi_get_frame_done_status(dsim);
612 }
613 
exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device * dsim)614 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
615 {
616 	_exynos_mipi_dsi_clear_frame_done(dsim);
617 
618 	return 0;
619 }
620