| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 87 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble()
98 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble()
114 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat()
125 float Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) { in UFixedToFloat()
141 SimFloat16 Simulator::FixedToFloat16(int64_t src, int fbits, FPRounding round) { in FixedToFloat16()
153 int fbits, in UFixedToFloat16()
4762 int fbits) { in fcvts()
4790 int fbits) { in fcvtu()
5296 int fbits, in scvtf()
5318 int fbits, in ucvtf()
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| D | assembler-aarch64.cc | 2996 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs()
3015 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu()
3029 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzu()
3047 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf()
3065 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) { in scvtf()
3084 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf()
3098 void Assembler::ucvtf(const VRegister& vd, const Register& rn, int fbits) { in ucvtf()
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| D | simulator-aarch64.cc | 3043 int fbits = 64 - instr->GetFPScale(); in VisitFPFixedPointConvert() local
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| /external/v8/src/arm64/ |
| D | simulator-logic-arm64.cc | 42 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble()
52 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble()
67 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat()
77 float Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) { in UFixedToFloat()
3720 FPRounding rounding_mode, int fbits) { in fcvts()
3739 FPRounding rounding_mode, int fbits) { in fcvtu()
4155 const LogicVRegister& src, int fbits, in scvtf()
4171 const LogicVRegister& src, int fbits, in ucvtf()
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| D | assembler-arm64.cc | 3208 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf()
3218 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf()
3228 void Assembler::ucvtf(const VRegister& fd, const Register& rn, int fbits) { in ucvtf()
3349 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) { in fcvtzs()
3360 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs()
3370 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu()
3381 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzu()
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| D | macro-assembler-arm64-inl.h | 885 unsigned fbits) { in Scvtf()
973 unsigned fbits) { in Ucvtf()
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| D | simulator-arm64.cc | 2624 int fbits = 64 - instr->FPScale(); in VisitFPFixedPointConvert() local
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| /external/python/cpython3/Objects/ |
| D | floatobject.c | 2161 unsigned int fbits; in _PyFloat_Pack4() local
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| /external/python/cpython2/Objects/ |
| D | floatobject.c | 2318 unsigned int fbits; in _PyFloat_Pack4() local
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| /external/vixl/test/aarch64/ |
| D | test-simulator-aarch64.cc | 1022 for (unsigned fbits = 0; fbits <= d_size; ++fbits) { in TestFPToFixed_Helper() local
1333 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedS() local
1411 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedU() local
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| D | test-assembler-aarch64.cc | 14483 for (int fbits = 1; fbits <= 32; fbits++) { in TestUScvtfHelper() local
14496 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtfHelper() local
14510 for (int fbits = 0; fbits <= 32; fbits++) { in TestUScvtfHelper() local
14518 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtfHelper() local
14638 for (int fbits = 1; fbits <= 32; fbits++) { in TestUScvtf32Helper() local
14651 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtf32Helper() local
14665 for (int fbits = 0; fbits <= 32; fbits++) { in TestUScvtf32Helper() local
14673 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtf32Helper() local
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| /external/skqp/third_party/skcms/ |
| D | skcms.cc | 1380 float fbits = (1.0f * (1<<23)) * (x + 121.274057500f in exp2f_() local
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| /external/skia/third_party/skcms/ |
| D | skcms.cc | 1380 float fbits = (1.0f * (1<<23)) * (x + 121.274057500f in exp2f_() local
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| /external/vixl/src/aarch32/ |
| D | disasm-aarch32.cc | 4428 int32_t fbits) { in vcvt()
4439 int32_t fbits) { in vcvt()
4450 int32_t fbits) { in vcvt()
23878 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
23956 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
24224 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
24302 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
36096 uint32_t fbits = in DecodeT32() local
38262 uint32_t fbits = in DecodeT32() local
47736 uint32_t fbits = 64 - ((instr >> 16) & 0x3f); in DecodeA32() local
[all …]
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| D | macro-assembler-aarch32.h | 6308 int32_t fbits) { in Vcvt()
6318 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in Vcvt()
6327 int32_t fbits) { in Vcvt()
6337 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in Vcvt()
6346 int32_t fbits) { in Vcvt()
6356 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { in Vcvt()
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| D | assembler-aarch32.h | 4239 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in vcvt()
4250 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in vcvt()
4261 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { in vcvt()
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| D | assembler-aarch32.cc | 16279 int32_t fbits) { in vcvt()
16383 int32_t fbits) { in vcvt()
16419 int32_t fbits) { in vcvt()
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