1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33
34 #include "freedreno_draw.h"
35 #include "freedreno_state.h"
36 #include "freedreno_resource.h"
37
38 #include "fd2_gmem.h"
39 #include "fd2_context.h"
40 #include "fd2_emit.h"
41 #include "fd2_program.h"
42 #include "fd2_util.h"
43 #include "fd2_zsa.h"
44
fmt2swap(enum pipe_format format)45 static uint32_t fmt2swap(enum pipe_format format)
46 {
47 switch (format) {
48 case PIPE_FORMAT_B8G8R8A8_UNORM:
49 case PIPE_FORMAT_B8G8R8X8_UNORM:
50 case PIPE_FORMAT_B5G6R5_UNORM:
51 case PIPE_FORMAT_B5G5R5A1_UNORM:
52 case PIPE_FORMAT_B5G5R5X1_UNORM:
53 case PIPE_FORMAT_B4G4R4A4_UNORM:
54 case PIPE_FORMAT_B4G4R4X4_UNORM:
55 /* TODO probably some more.. */
56 return 1;
57 default:
58 return 0;
59 }
60 }
61
62 /* transfer from gmem to system memory (ie. normal RAM) */
63
64 static void
emit_gmem2mem_surf(struct fd_batch * batch,uint32_t base,struct pipe_surface * psurf)65 emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
66 struct pipe_surface *psurf)
67 {
68 struct fd_ringbuffer *ring = batch->gmem;
69 struct fd_resource *rsc = fd_resource(psurf->texture);
70 uint32_t swap = fmt2swap(psurf->format);
71
72 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
73 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
74 OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
75 A2XX_RB_COLOR_INFO_BASE(base) |
76 A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
77
78 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
79 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
80 OUT_RING(ring, 0x00000000); /* RB_COPY_CONTROL */
81 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_COPY_DEST_BASE */
82 OUT_RING(ring, rsc->slices[0].pitch >> 5); /* RB_COPY_DEST_PITCH */
83 OUT_RING(ring, /* RB_COPY_DEST_INFO */
84 A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
85 A2XX_RB_COPY_DEST_INFO_LINEAR |
86 A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
87 A2XX_RB_COPY_DEST_INFO_WRITE_RED |
88 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
89 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
90 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
91
92 OUT_WFI (ring);
93
94 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
95 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
96 OUT_RING(ring, 3); /* VGT_MAX_VTX_INDX */
97 OUT_RING(ring, 0); /* VGT_MIN_VTX_INDX */
98
99 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
100 DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
101 }
102
103 static void
fd2_emit_tile_gmem2mem(struct fd_batch * batch,struct fd_tile * tile)104 fd2_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
105 {
106 struct fd_context *ctx = batch->ctx;
107 struct fd2_context *fd2_ctx = fd2_context(ctx);
108 struct fd_ringbuffer *ring = batch->gmem;
109 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
110
111 fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
112 { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
113 }, 1);
114
115 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
116 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
117 OUT_RING(ring, 0x00000000); /* PA_SC_WINDOW_OFFSET */
118
119 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
120 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
121 OUT_RING(ring, 0);
122
123 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
124 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
125 OUT_RING(ring, 0x0000028f);
126
127 fd2_program_emit(ring, &ctx->solid_prog);
128
129 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
130 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
131 OUT_RING(ring, 0x0000ffff);
132
133 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
134 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
135 OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
136
137 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
138 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
139 OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */
140 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
141 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
142
143 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
144 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
145 OUT_RING(ring, xy2d(0, 0)); /* PA_SC_WINDOW_SCISSOR_TL */
146 OUT_RING(ring, xy2d(pfb->width, pfb->height)); /* PA_SC_WINDOW_SCISSOR_BR */
147
148 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
149 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
150 OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
151 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
152 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
153 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
154 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
155
156 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
157 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
158 OUT_RING(ring, 0x00000000);
159
160 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
161 OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
162 OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
163
164 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
165 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET));
166 OUT_RING(ring, A2XX_RB_COPY_DEST_OFFSET_X(tile->xoff) |
167 A2XX_RB_COPY_DEST_OFFSET_Y(tile->yoff));
168
169 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
170 emit_gmem2mem_surf(batch, tile->bin_w * tile->bin_h, pfb->zsbuf);
171
172 if (batch->resolve & FD_BUFFER_COLOR)
173 emit_gmem2mem_surf(batch, 0, pfb->cbufs[0]);
174
175 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
176 OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
177 OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
178 }
179
180 /* transfer from system memory to gmem */
181
182 static void
emit_mem2gmem_surf(struct fd_batch * batch,uint32_t base,struct pipe_surface * psurf)183 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
184 struct pipe_surface *psurf)
185 {
186 struct fd_ringbuffer *ring = batch->gmem;
187 struct fd_resource *rsc = fd_resource(psurf->texture);
188 uint32_t swiz;
189
190 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
191 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
192 OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
193 A2XX_RB_COLOR_INFO_BASE(base) |
194 A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
195
196 swiz = fd2_tex_swiz(psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
197 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
198
199 /* emit fb as a texture: */
200 OUT_PKT3(ring, CP_SET_CONSTANT, 7);
201 OUT_RING(ring, 0x00010000);
202 OUT_RING(ring, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP) |
203 A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP) |
204 A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) |
205 A2XX_SQ_TEX_0_PITCH(rsc->slices[0].pitch));
206 OUT_RELOC(ring, rsc->bo, 0,
207 fd2_pipe2surface(psurf->format) | 0x800, 0);
208 OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) |
209 A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1));
210 OUT_RING(ring, 0x01000000 | // XXX
211 swiz |
212 A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
213 A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
214 OUT_RING(ring, 0x00000000);
215 OUT_RING(ring, 0x00000200);
216
217 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
218 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
219 OUT_RING(ring, 3); /* VGT_MAX_VTX_INDX */
220 OUT_RING(ring, 0); /* VGT_MIN_VTX_INDX */
221
222 fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
223 DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
224 }
225
226 static void
fd2_emit_tile_mem2gmem(struct fd_batch * batch,struct fd_tile * tile)227 fd2_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
228 {
229 struct fd_context *ctx = batch->ctx;
230 struct fd2_context *fd2_ctx = fd2_context(ctx);
231 struct fd_ringbuffer *ring = batch->gmem;
232 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
233 unsigned bin_w = tile->bin_w;
234 unsigned bin_h = tile->bin_h;
235 float x0, y0, x1, y1;
236
237 fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
238 { .prsc = fd2_ctx->solid_vertexbuf, .size = 48, .offset = 0x30 },
239 { .prsc = fd2_ctx->solid_vertexbuf, .size = 32, .offset = 0x60 },
240 }, 2);
241
242 /* write texture coordinates to vertexbuf: */
243 x0 = ((float)tile->xoff) / ((float)pfb->width);
244 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
245 y0 = ((float)tile->yoff) / ((float)pfb->height);
246 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
247 OUT_PKT3(ring, CP_MEM_WRITE, 9);
248 OUT_RELOC(ring, fd_resource(fd2_ctx->solid_vertexbuf)->bo, 0x60, 0, 0);
249 OUT_RING(ring, fui(x0));
250 OUT_RING(ring, fui(y0));
251 OUT_RING(ring, fui(x1));
252 OUT_RING(ring, fui(y0));
253 OUT_RING(ring, fui(x0));
254 OUT_RING(ring, fui(y1));
255 OUT_RING(ring, fui(x1));
256 OUT_RING(ring, fui(y1));
257
258 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
259 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
260 OUT_RING(ring, 0);
261
262 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
263 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
264 OUT_RING(ring, 0x0000003b);
265
266 fd2_program_emit(ring, &ctx->blit_prog[0]);
267
268 OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
269 OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
270
271 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
272 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
273 OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
274
275 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
276 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
277 OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
278 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
279 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
280
281 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
282 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
283 OUT_RING(ring, 0x0000ffff);
284
285 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
286 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
287 OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
288 A2XX_RB_COLORCONTROL_BLEND_DISABLE |
289 A2XX_RB_COLORCONTROL_ROP_CODE(12) |
290 A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
291 A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
292
293 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
294 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
295 OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) |
296 A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND_DST_PLUS_SRC) |
297 A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) |
298 A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) |
299 A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND_DST_PLUS_SRC) |
300 A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO));
301
302 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
303 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
304 OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_DISABLE |
305 xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */
306 OUT_RING(ring, xy2d(bin_w, bin_h)); /* PA_SC_WINDOW_SCISSOR_BR */
307
308 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
309 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
310 OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XSCALE */
311 OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XOFFSET */
312 OUT_RING(ring, fui(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
313 OUT_RING(ring, fui((float)bin_h/2.0)); /* PA_CL_VPORT_YOFFSET */
314
315 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
316 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
317 OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT |
318 A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT | // XXX check this???
319 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
320 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
321 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
322 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
323
324 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
325 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
326 OUT_RING(ring, 0x00000000);
327
328 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
329 emit_mem2gmem_surf(batch, bin_w * bin_h, pfb->zsbuf);
330
331 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR))
332 emit_mem2gmem_surf(batch, 0, pfb->cbufs[0]);
333
334 /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
335 }
336
337 /* before first tile */
338 static void
fd2_emit_tile_init(struct fd_batch * batch)339 fd2_emit_tile_init(struct fd_batch *batch)
340 {
341 struct fd_context *ctx = batch->ctx;
342 struct fd_ringbuffer *ring = batch->gmem;
343 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
344 struct fd_gmem_stateobj *gmem = &ctx->gmem;
345 enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
346 uint32_t reg;
347
348 fd2_emit_restore(ctx, ring);
349
350 OUT_PKT3(ring, CP_SET_CONSTANT, 4);
351 OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO));
352 OUT_RING(ring, gmem->bin_w); /* RB_SURFACE_INFO */
353 OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
354 A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
355 reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(align(gmem->bin_w * gmem->bin_h, 4));
356 if (pfb->zsbuf)
357 reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
358 OUT_RING(ring, reg); /* RB_DEPTH_INFO */
359 }
360
361 /* before mem2gmem */
362 static void
fd2_emit_tile_prep(struct fd_batch * batch,struct fd_tile * tile)363 fd2_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
364 {
365 struct fd_ringbuffer *ring = batch->gmem;
366 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
367 enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
368
369 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
370 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
371 OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
372 A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
373
374 /* setup screen scissor for current tile (same for mem2gmem): */
375 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
376 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL));
377 OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_TL_X(0) |
378 A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(0));
379 OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_BR_X(tile->bin_w) |
380 A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(tile->bin_h));
381 }
382
383 /* before IB to rendering cmds: */
384 static void
fd2_emit_tile_renderprep(struct fd_batch * batch,struct fd_tile * tile)385 fd2_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
386 {
387 struct fd_ringbuffer *ring = batch->gmem;
388 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
389 enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
390
391 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
392 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
393 OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
394 A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
395
396 /* setup window scissor and offset for current tile (different
397 * from mem2gmem):
398 */
399 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
400 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
401 OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(-tile->xoff) |
402 A2XX_PA_SC_WINDOW_OFFSET_Y(-tile->yoff));
403 }
404
405 void
fd2_gmem_init(struct pipe_context * pctx)406 fd2_gmem_init(struct pipe_context *pctx)
407 {
408 struct fd_context *ctx = fd_context(pctx);
409
410 ctx->emit_tile_init = fd2_emit_tile_init;
411 ctx->emit_tile_prep = fd2_emit_tile_prep;
412 ctx->emit_tile_mem2gmem = fd2_emit_tile_mem2gmem;
413 ctx->emit_tile_renderprep = fd2_emit_tile_renderprep;
414 ctx->emit_tile_gmem2mem = fd2_emit_tile_gmem2mem;
415 }
416